}
}
-STATIC_INLINE void setdr (int nr)
+static void setdr(int nr, bool startup)
{
struct audio_channel_data *cdp = audio_channel + nr;
#if TEST_AUDIO > 0
if (debugchannel (nr) && cdp->dr)
write_log (_T("%d: DR already active (STATE=%d)\n"), nr, cdp->state);
#endif
- cdp->drhpos = current_hpos ();
+ if (dmaen(DMA_MASTER)) {
#if DEBUG_AUDIO > 0
- if (debugchannel(nr) && cdp->wlen <= 2)
- write_log(_T("DR%d=%d LEN=%d/%d PT=%08X PC=%08X\n"), nr, cdp->dr, cdp->wlen, cdp->len, cdp->pt, M68K_GETPC);
+ if (debugchannel(nr) && cdp->wlen <= 2)
+ write_log(_T("DR%d=%d LEN=%d/%d PT=%08X PC=%08X\n"), nr, cdp->dr, cdp->wlen, cdp->len, cdp->pt, M68K_GETPC);
#endif
- cdp->dr = true;
+ cdp->dr = true;
+ cdp->drhpos = current_hpos();
- if (cdp->wlen == 1) {
- cdp->dsr = true;
+ if (!startup && cdp->wlen == 1) {
+ cdp->dsr = true;
#if DEBUG_AUDIO > 0
- if (debugchannel (nr))
- write_log (_T("DSR%d=1 PT=%08X PC=%08X\n"), nr, cdp->pt, M68K_GETPC);
+ if (debugchannel(nr))
+ write_log(_T("DSR%d=1 PT=%08X PC=%08X\n"), nr, cdp->pt, M68K_GETPC);
+#endif
+ }
+ } else {
+#if DEBUG_AUDIO > 0
+ if (debugchannel(nr))
+ write_log(_T("setdr%d ignored, DMA disabled PT=%08X PC=%08X\n"), nr, cdp->pt, M68K_GETPC);
#endif
}
}
if (chan_ena) {
cdp->evtime = MAX_EV;
cdp->state = 1;
- cdp->dr = true;
- cdp->drhpos = hpos;
+ setdr(nr, true);
cdp->wlen = cdp->len;
cdp->ptx_written = false;
/* Some programs first start short empty sample and then later switch to
cdp->losample = cdp->hisample = false;
#endif
setirq (nr, 10);
- setdr (nr);
+ setdr(nr, false);
if (cdp->wlen != 1)
cdp->wlen = (cdp->wlen - 1) & 0xffff;
cdp->state = 5;
}
loaddat (nr);
if (napnav)
- setdr (nr);
+ setdr(nr, false);
cdp->state = 2;
loadper (nr);
cdp->pbufldl = true;
loaddat (nr, true);
if (chan_ena) {
if (audap)
- setdr (nr);
+ setdr(nr, false);
if (cdp->intreq2 && audap)
setirq (nr, 21);
} else {
if (cdp->intreq2 && napnav)
setirq (nr, 31);
if (napnav)
- setdr (nr);
+ setdr(nr, false);
} else {
if (isirq (nr)) {
#if DEBUG_AUDIO > 0
}
}
-static void events_dmal (int);
+static void events_dmal(int);
static uae_u16 dmal, dmal_hpos;
-static void dmal_emu (uae_u32 v)
+static void dmal_emu(uae_u32 v)
{
- // Disk and Audio DMA bits are ignored by Agnus, Agnus only checks DMAL and master bit
- if (!(dmacon & DMA_MASTER))
- return;
+ // Disk and Audio DMA bits are ignored by Agnus. Including DMA master bit.
int hpos = current_hpos ();
if (v >= 6) {
v -= 6;
}
}
-static void dmal_func (uae_u32 v)
+static void dmal_func(uae_u32 v)
{
dmal_emu (v);
events_dmal (0);
}
-static void dmal_func2 (uae_u32 v)
+static void dmal_func2(uae_u32 v)
{
while (dmal) {
if (dmal & 3)
- dmal_emu (dmal_hpos + ((dmal & 2) ? 1 : 0));
+ dmal_emu(dmal_hpos + ((dmal & 2) ? 1 : 0));
dmal_hpos += 2;
dmal >>= 2;
}
}
-static void events_dmal (int hp)
+static void events_dmal(int hp)
{
if (!dmal)
return;
dmal >>= 2;
dmal_hpos += 2;
}
- event2_newevent2 (hp, dmal_hpos + ((dmal & 2) ? 1 : 0), dmal_func);
+ event2_newevent2(hp, dmal_hpos + ((dmal & 2) ? 1 : 0), dmal_func);
dmal &= ~3;
} else if (currprefs.cachesize) {
- dmal_func2 (0);
+ dmal_func2(0);
} else {
- event2_newevent2 (hp, 13, dmal_func2);
+ event2_newevent2(hp, 13, dmal_func2);
}
}
-static void events_dmal_hsync (void)
+static void events_dmal_hsync(void)
{
if (dmal)
write_log (_T("DMAL error!? %04x\n"), dmal);
- dmal = audio_dmal ();
+ dmal = audio_dmal();
dmal <<= 6;
- dmal |= disk_dmal ();
+ dmal |= disk_dmal();
if (!dmal)
return;
dmal_hpos = 0;
if (currprefs.cpu_memory_cycle_exact) {
for (int i = 0; i < 6 + 8; i += 2) {
if (dmal & (3 << i)) {
- alloc_cycle_ext (i + 7, CYCLE_MISC);
+ alloc_cycle_ext(i + 7, CYCLE_MISC);
}
}
}
- events_dmal (7);
+ events_dmal(7);
}
static void lightpen_trigger_func(uae_u32 v)
}
}
}
- if (dmaen (DMA_DISK) && dskdmaen == DSKDMA_WRITE && dsklength > 0 && fifo_filled) {
+ if (dmaen(DMA_DISK) && dmaen(DMA_MASTER) && dskdmaen == DSKDMA_WRITE && dsklength > 0 && fifo_filled) {
bitoffset++;
bitoffset &= 15;
if (!bitoffset) {
static int doreaddma (void)
{
- if (dmaen (DMA_DISK) && bitoffset == 15 && dma_enable && dskdmaen == DSKDMA_READ && dsklength >= 0) {
+ if (dmaen(DMA_DISK) && dmaen(DMA_MASTER) && bitoffset == 15 && dma_enable && dskdmaen == DSKDMA_READ && dsklength >= 0) {
if (dsklength > 0) {
// DSKLEN == 1: finish without DMA transfer.
if (dsklength == 1 && dsklength2 == 1) {
dumpdisk(_T("DSKBYTR SYNC"));
}
}
- if (dskdmaen != DSKDMA_OFF && dmaen (DMA_DISK))
+ if (dskdmaen != DSKDMA_OFF && dmaen(DMA_DISK) && dmaen(DMA_MASTER))
v |= 0x4000;
if (dsklen & 0x4000)
v |= 0x2000;