_T("ax000_6570-036"),
NULL
};
+static const TCHAR *blcalib[] = { _T("off"), _T("on"), _T("debug"), NULL };
struct hdcontrollerconfig
{
if (p->chipset_refreshrate > 0)
cfgfile_write (f, _T("chipset_refreshrate"), _T("%f"), p->chipset_refreshrate);
cfgfile_dwrite_bool(f, _T("chipset_subpixel"), p->chipset_hr);
- cfgfile_dwrite_bool(f, _T("chipset_black_level_calibration"), p->display_calibration);
+ cfgfile_dwrite_strarr(f, _T("chipset_black_level_calibration"), blcalib, p->display_calibration);
for (int i = 0; i < MAX_CHIPSET_REFRESH_TOTAL; i++) {
struct chipset_refresh *cr = &p->cr[i];
if (cfgfile_yesno(option, value, _T("chipset_subpixel"), &p->chipset_hr)) {
return 1;
}
- if (cfgfile_yesno(option, value, _T("chipset_black_level_calibration"), &p->display_calibration)) {
+
+ if (cfgfile_strval(option, value, _T("chipset_black_level_calibration"), &p->display_calibration, blcalib, 0)) {
return 1;
}
p->blitter_cycle_exact = true;
p->chipset_mask = CSMASK_ECS_AGNUS;
p->chipset_hr = false;
- p->display_calibration = false;
+ p->display_calibration = 0;
p->genlock = 0;
p->genlock_image = 0;
p->genlock_mix = 0;
return;
}
-#if 1
- db[off] = 0xff0000;
- db[off + (clen << shift) - 1] = 0xff0000;
+ if (currprefs.display_calibration > 1) {
+ db[off] = 0xff0000;
+ db[off + (clen << shift) - 1] = 0xff0000;
- b1[off] = 0xff0000;
- b1[off + (clen << shift) - 1] = 0xff0000;
-#endif
+ b1[off] = 0xff0000;
+ b1[off + (clen << shift) - 1] = 0xff0000;
+ }
int outc[3];
for (int i = 0; i < 3; i++) {