Conditional and non-conditional single opcode instructions have different prefetch...

diff --git a/gencpu.cpp b/gencpu.cpp
index b9db312fec0343c1150dc941520258214a290052..e7b7b32036ab51f4e29c4b86707cff8349a19a83 100644 (file)
--- a/gencpu.cpp
+++ b/gencpu.cpp
@@ -3673,7 +3673,7 @@ static void gen_opcode (unsigned int opcode)
                sync_m68k_pc ();
                printf ("\tException (src + 32);\n");
                did_prefetch = 1;
-               branch_inst = 1;
+               branch_inst = 2;
                clear_m68k_offset();
                break;
        case i_MVR2USP:
@@ -3825,7 +3825,7 @@ static void gen_opcode (unsigned int opcode)
                clear_m68k_offset();
                tail_ce020_done = true;
                fill_prefetch_full ();
-               branch_inst = 1;
+               branch_inst = 2;
                break;
        case i_RTD:
                addop_ce020 (curi, 0);
@@ -3848,7 +3848,7 @@ static void gen_opcode (unsigned int opcode)
                tail_ce020_done = true;
                fill_prefetch_full ();
            need_endlabel = 1;
-               branch_inst = 1;
+               branch_inst = 2;
                break;
        case i_LINK:
                // ce confirmed
@@ -3916,7 +3916,7 @@ static void gen_opcode (unsigned int opcode)
                clear_m68k_offset();
                fill_prefetch_full ();
            need_endlabel = 1;
-               branch_inst = 1;
+               branch_inst = 2;
                break;
        case i_TRAPV:
                sync_m68k_pc ();

diff --git a/newcpu.cpp b/newcpu.cpp
index 348d0c588c3022837060202042dce9784db6d985..44ba56e1707c83843b5afc56a9fda57cb5efd1f9 100644 (file)
--- a/newcpu.cpp
+++ b/newcpu.cpp
@@ -6693,10 +6693,13 @@ static void pipeline_020(uae_u16 w, uaecptr pc)
                write_log(_T("Opcode %04x has no size PC=%08x!\n"), w, pc);
        }
 #endif
-       if (regs.pipeline_pos > 0 && cpudatatbl[w].branch) {
+       int branch = cpudatatbl[w].branch;
+       if (regs.pipeline_pos > 0 && branch) {
+               // Short branches (Bcc.s) still do one more prefetch.
+               // RTS and other unconditional single opcode instruction stop immediately.
                regs.pipeline_pos -= 1 * 2;
-               if (regs.pipeline_pos <= 0 && !regs.pipeline_r8[0] && !regs.pipeline_r8[1])
-                       regs.pipeline_stop = -1;
+               if (branch == 2)
+                       regs.pipeline_stop = -1; // immediate stop
                else
                        regs.pipeline_stop = 1;
        }