Removed unneeded cycle delays.

diff --git a/custom.cpp b/custom.cpp
index f6fb7658618f6653ffb79de1ac75cd22f56a1f82..7d4ba0f477a3961ec51737f71c80a8c717ccb84f 100644 (file)
--- a/custom.cpp
+++ b/custom.cpp
@@ -11656,7 +11656,7 @@ void wait_cpu_cycle_write_ce020 (uaecptr addr, int mode, uae_u32 v)
 
        // chipset buffer latches the write, CPU does
        // not need to wait for the chipset cycle to finish.
-       x_do_cycles_post (cpucycleunit + cpucycleunit / 2, v);
+       x_do_cycles_post (cpucycleunit, v);
 
        regs.chipset_latch_rw = regs.chipset_latch_write = v;
        SETIFCHIP

diff --git a/newcpu.cpp b/newcpu.cpp
index 09e13fcca51e446641380d91663ca9db6d230bd2..6d23b310d24672f3bb9088ce9c2c798293e05ac4 100644 (file)
--- a/newcpu.cpp
+++ b/newcpu.cpp
@@ -9612,8 +9612,8 @@ static uae_u32 get_word_ce020_prefetch_2 (int o, bool opcode)
        } else {
                regs.prefetch020[2] = (uae_u16)regs.cacheholdingdata020;
        }
-       do_cycles_ce020_internal (2);
        regs.db = regs.prefetch020[0];
+       do_cycles_ce020_internal(2);
        return v;
 }
 
@@ -10491,7 +10491,7 @@ static uae_u32 get_word_ce030_prefetch_2 (int o)
                regs.prefetch020[2] = (uae_u16)regs.cacheholdingdata020;
        }
        regs.db = regs.prefetch020[0];
-       do_cycles_ce020_internal (2);
+       do_cycles_ce020_internal(2);
        return v;
 }
 
@@ -11264,8 +11264,6 @@ void fill_prefetch_030_ntx(void)
        regs.prefetch020_valid[0] = regs.prefetch020_valid[1] = regs.prefetch020_valid[2] = 0;
 
        fill_icache030(pc);
-       if (currprefs.cpu_cycle_exact)
-               do_cycles_ce020_internal(2);
        if (pc2 & 2) {
                idx = add_prefetch_030(idx, regs.cacheholdingdata020, pc2);
        } else {
@@ -11274,8 +11272,6 @@ void fill_prefetch_030_ntx(void)
        }
 
        fill_icache030(pc + 4);
-       if (currprefs.cpu_cycle_exact)
-               do_cycles_ce020_internal(2);
        if (pc2 & 2) {
                idx = add_prefetch_030(idx, regs.cacheholdingdata020 >> 16, pc2);
                idx = add_prefetch_030(idx, regs.cacheholdingdata020, pc2);
@@ -11317,8 +11313,6 @@ void fill_prefetch_030_ntx_continue (void)
                pc &= ~3;
 
                fill_icache030(pc);
-               if (currprefs.cpu_cycle_exact)
-                       do_cycles_ce020_internal(2);
                if (pc2 & 2) {
                        idx = add_prefetch_030(idx, regs.cacheholdingdata020, pc_orig);
                } else {
@@ -11329,8 +11323,6 @@ void fill_prefetch_030_ntx_continue (void)
 
                if (idx < 3) {
                        fill_icache030(pc + 4);
-                       if (currprefs.cpu_cycle_exact)
-                               do_cycles_ce020_internal(2);
                        if (pc2 & 2) {
                                idx = add_prefetch_030(idx, regs.cacheholdingdata020 >> 16, pc_orig);
                                if (idx < 3)
@@ -11357,8 +11349,6 @@ void fill_prefetch_020_ntx(void)
        reset_pipeline_state();
 
        fill_icache020 (pc, true);
-       if (currprefs.cpu_cycle_exact)
-               do_cycles_ce020_internal(2);
        if (pc2 & 2) {
                idx = add_prefetch_030(idx, regs.cacheholdingdata020, pc);
        } else {
@@ -11367,8 +11357,6 @@ void fill_prefetch_020_ntx(void)
        }
 
        fill_icache020 (pc + 4, true);
-       if (currprefs.cpu_cycle_exact)
-               do_cycles_ce020_internal(2);
        if (pc2 & 2) {
                idx = add_prefetch_030(idx, regs.cacheholdingdata020 >> 16, pc);
                idx = add_prefetch_030(idx, regs.cacheholdingdata020, pc);