break;
case A2410_BANK_CONTROL:
v = get_a2410_control(data);
- write_log(_T("CONTROL READ %08x = %02x PC=%08x\n"), aa, v, M68K_GETPC);
+ //write_log(_T("CONTROL READ %08x = %02x PC=%08x\n"), aa, v, M68K_GETPC);
break;
case A2410_BANK_DMA:
if (valid_dma(data, addr)) {
break;
case A2410_BANK_CONTROL:
v = get_a2410_control(data);
- write_log(_T("CONTROL READ %08x = %02x PC=%08x\n"), aa, v, M68K_GETPC);
+ //write_log(_T("CONTROL READ %08x = %02x PC=%08x\n"), aa, v, M68K_GETPC);
break;
case A2410_BANK_DMA:
if (valid_dma(data, addr)) {
}
break;
case A2410_BANK_CONTROL:
- write_log(_T("CONTROL WRITE %08x = %02x PC=%08x\n"), aa, b, M68K_GETPC);
+ //write_log(_T("CONTROL WRITE %08x = %02x PC=%08x\n"), aa, b, M68K_GETPC);
data->a2410_control = b;
break;
case A2410_BANK_DMA:
}
break;
case A2410_BANK_CONTROL:
- write_log(_T("CONTROL WRITE %08x = %04x PC=%08x\n"), aa, b, M68K_GETPC);
+ //write_log(_T("CONTROL WRITE %08x = %04x PC=%08x\n"), aa, b, M68K_GETPC);
data->a2410_control = b;
break;
case A2410_BANK_DMA:
memset(m_regs, 0, sizeof(m_regs));
memset(m_IOregs, 0, sizeof(m_IOregs));
memset(m_shiftreg, 0, sizeof(m_shiftreg));
+ m_plane_mask = 0x00000000;
+ m_plane_mask_inv = 0xffffffff;
/* fetch the initial PC and reset the state */
m_pc = RLONG(0xffffffe0) & 0xfffffff0;