unsigned int evtime;
bool dmaenstore;
bool intreq2;
- bool irqcheck;
+ int irqcheck;
bool dr;
bool dsr;
bool pbufldl;
write_log (_T("%d: ZEROSTATE\n"), nr);
#endif
cdp->state = 0;
- cdp->irqcheck = false;
+ cdp->irqcheck = 0;
cdp->evtime = MAX_EV;
cdp->intreq2 = 0;
cdp->dmaenstore = false;
if (usehacks() && (currprefs.cachesize || (regs.instruction_cnt - cdp->dmaofftime_cpu_cnt) >= 60)) {
if (warned >= 0) {
warned--;
- write_log(_T("Audio %d DMA wait hack: ENABLED. OFF=%08x, ON=%08x\n"), nr, cdp->dmaofftime_pc, M68K_GETPC);
+ write_log(_T("Audio %d DMA wait hack ENABLED. OFF=%08x, ON=%08x, PER=%d\n"), nr, cdp->dmaofftime_pc, M68K_GETPC, cdp->evtime / CYCLE_UNIT);
}
#if DEBUG_AUDIO_HACK > 0
if (debugchannel(nr))
} else {
if (warned >= 0) {
warned--;
- write_log(_T("Audio %d DMA wait hack: DISABLED. OFF=%08x, ON=%08x\n"), nr, cdp->dmaofftime_pc, M68K_GETPC);
+ write_log(_T("Audio %d DMA wait hack DISABLED. OFF=%08x, ON=%08x, PER=%d\n"), nr, cdp->dmaofftime_pc, M68K_GETPC, cdp->evtime / CYCLE_UNIT);
}
}
cdp->dmaofftime_active = false;
setirq (nr, 22);
}
cdp->pbufldl = true;
- cdp->irqcheck = false;
+ cdp->irqcheck = 0;
cdp->state = 3;
audio_state_channel2 (nr, false);
break;
cdp->state = 3;
loadper1(nr);
if (!chan_ena && isirq(nr)) {
- cdp->irqcheck = true;
+ cdp->irqcheck = 1;
+ } else {
+ cdp->irqcheck = -1;
}
return false;
if (napnav)
setdr(nr, false);
} else {
- if (cdp->irqcheck) {
+ // cycle-accurate period check was not needed, do delayed check
+ if (!cdp->irqcheck) {
+ cdp->irqcheck = isirq(nr);
+ }
+ if (cdp->irqcheck > 0) {
#if DEBUG_AUDIO > 0
if (debugchannel (nr))
write_log (_T("%d: IDLE\n"), nr);