+2009-01-01 Klaus Treichel <ktreichel@web.de>
+
+ * jit/jit-rules-x86-64.ins (JIT_OP_NFLOAT_TO_FLOAT32,
+ JIT_OP_NFLOAT_TO_FLOAT64): Add rules for the case that the
+ destination value is in the stack frame.
+ (JIT_OP_BR_ILT, JIT_OP_BR_ILE, JIT_OP_BR_IGT, JIT_OP_BR_IGE):
+ Handle the comparision with a constant 0 with a test opcode instead
+ of a cmp.
+ (JIT_OP_ISIGN, JIT_OP_LSIGN): Add handling of the integer sign
+ opcodes.
+
2008-12-21 Aleksey Demakov <ademakov@gmail.com>
* jit/jit-dump.c (jit_dump_function): dump undefined labels as such
* jit/jit-insn.c (jit_insn_call_native): extend small int return
values to full ints as native calls sometimes return garbage in MSB
- of the return rigister.
+ of the return register.
2008-12-11 Aleksey Demakov <ademakov@gmail.com>
}
JIT_OP_NFLOAT_TO_FLOAT32: stack
+ [=local, freg] -> {
+ x86_64_fstp_membase_size(inst, X86_64_RBP, $1, 4);
+ }
[=xreg, freg] -> {
#ifdef HAVE_RED_ZONE
/* Avoid modifying the stack pointer by simply using negative */
}
JIT_OP_NFLOAT_TO_FLOAT64: stack
+ [=local, freg] -> {
+ x86_64_fstp_membase_size(inst, X86_64_RBP, $1, 8);
+ }
[=xreg, freg] -> {
#ifdef HAVE_RED_ZONE
/* Avoid modifying the stack pointer by simply using negative */
JIT_OP_BR_ILT: branch
[reg, imm] -> {
- x86_64_cmp_reg_imm_size(inst, $1, $2, 4);
+ if($2 == 0)
+ {
+ x86_64_test_reg_reg_size(inst, $1, $1, 4);
+ }
+ else
+ {
+ x86_64_cmp_reg_imm_size(inst, $1, $2, 4);
+ }
inst = output_branch(func, inst, 0x7C /* lt */, insn);
}
[reg, local] -> {
JIT_OP_BR_ILE: branch
[reg, imm] -> {
- x86_64_cmp_reg_imm_size(inst, $1, $2, 4);
+ if($2 == 0)
+ {
+ x86_64_test_reg_reg_size(inst, $1, $1, 4);
+ }
+ else
+ {
+ x86_64_cmp_reg_imm_size(inst, $1, $2, 4);
+ }
inst = output_branch(func, inst, 0x7E /* le */, insn);
}
[reg, local] -> {
JIT_OP_BR_IGT: branch
[reg, imm] -> {
- x86_64_cmp_reg_imm_size(inst, $1, $2, 4);
+ if($2 == 0)
+ {
+ x86_64_test_reg_reg_size(inst, $1, $1, 4);
+ }
+ else
+ {
+ x86_64_cmp_reg_imm_size(inst, $1, $2, 4);
+ }
inst = output_branch(func, inst, 0x7F /* gt */, insn);
}
[reg, local] -> {
JIT_OP_BR_IGE: branch
[reg, imm] -> {
- x86_64_cmp_reg_imm_size(inst, $1, $2, 4);
+ if($2 == 0)
+ {
+ x86_64_test_reg_reg_size(inst, $1, $1, 4);
+ }
+ else
+ {
+ x86_64_cmp_reg_imm_size(inst, $1, $2, 4);
+ }
inst = output_branch(func, inst, 0x7D /* ge */, insn);
}
[reg, local] -> {
x86_64_cmov_reg_reg_size(inst, X86_CC_GT, $1, $2, 0, 4);
}
+JIT_OP_ISIGN:
+ [=reg, imm] -> {
+ if($2 < 0)
+ {
+ x86_64_mov_reg_imm_size(inst, $1, -1, 4);
+ }
+ else if($2 > 0)
+ {
+ x86_64_mov_reg_imm_size(inst, $1, 1, 4);
+ }
+ else
+ {
+ x86_64_clear_reg(inst, $1);
+ }
+ }
+ [=+reg, +reg] -> {
+ x86_64_clear_reg(inst, $1);
+ x86_64_test_reg_reg_size(inst, $2, $2, 4);
+ x86_64_set_reg(inst, X86_CC_NZ, $1, 0);
+ x86_64_sar_reg_imm_size(inst, $2, 31, 4);
+ x86_64_or_reg_reg_size(inst, $1, $2, 4);
+ }
+
JIT_OP_LMAX: commutative
[reg, reg] -> {
x86_64_cmp_reg_reg_size(inst, $1, $2, 8);
x86_64_cmov_reg_reg_size(inst, X86_CC_GT, $1, $2, 0, 8);
}
+JIT_OP_LSIGN:
+ [=reg, imm] -> {
+ if($2 < 0)
+ {
+ x86_64_mov_reg_imm_size(inst, $1, -1, 4);
+ }
+ else if($2 > 0)
+ {
+ x86_64_mov_reg_imm_size(inst, $1, 1, 4);
+ }
+ else
+ {
+ x86_64_clear_reg(inst, $1);
+ }
+ }
+ [=+reg, +reg] -> {
+ x86_64_clear_reg(inst, $1);
+ x86_64_test_reg_reg_size(inst, $2, $2, 8);
+ x86_64_set_reg(inst, X86_CC_NZ, $1, 0);
+ x86_64_sar_reg_imm_size(inst, $2, 63, 8);
+ x86_64_or_reg_reg_size(inst, $1, $2, 4);
+ }
+
JIT_OP_FMAX: commutative
[xreg, local] -> {
x86_64_maxss_reg_membase(inst, $1, X86_64_RBP, $2);