{
static int subqcnt;
- if (!currprefs.cs_cdtvcd || configured <= 0)
+ if (!currprefs.cs_cdtvcd || configured <= 0 || currprefs.cs_cdtvcr)
return;
cdtv_hsync++;
{
uae_u8 *dstbak, *dst;
- if (!currprefs.cs_cdtvcd)
+ if (!currprefs.cs_cdtvcd || currprefs.cs_cdtvcr)
return NULL;
if (dstptr)
dstbak = dst = dstptr;
{
uae_u8 *dstbak, *dst;
- if (!currprefs.cs_cdtvcd)
+ if (!currprefs.cs_cdtvcd || currprefs.cs_cdtvcr)
return NULL;
if (dstptr)
void restore_cdtv_finish (void)
{
- if (!currprefs.cs_cdtvcd)
+ if (!currprefs.cs_cdtvcd || currprefs.cs_cdtvcr)
return;
cdtv_init ();
get_toc ();
#include "zfile.h"
#include "gui.h"
#include "cdtvcr.h"
+#include "blkdev.h"
+#include "threaddep/thread.h"
+#include "uae.h"
+#include "custom.h"
#define CDTVCR_MASK 0xffff
#define CDTVCR_RAM_MASK (CDTVCR_RAM_SIZE - 1)
#define CDTVCR_CLOCK 0xc10
+#define CDTVCR_ID 0x9dc
+#define CDTVCR_RESET 0xc00
+
+#define CDTVCR_CD_CMD 0xc40
+#define CDTVCR_CD_CMD_DO 0xc52
+#define CDTVCR_CD_CMD_STATUS 0xc4e
+#define CDTVCR_CD_CMD_STATUS2 0xc4f
+
+#define CDTVCR_CD_STATE 0xc53
+#define CDTVCR_SYS_STATE 0xc54
+#define CDTVCR_CD_SPEED 0xc59
+#define CDTVCR_CD_PLAYING 0xc5b
+#define CDTVCR_CD_SUBCODES 0xc60
+#define CDTVCR_CD_ALLOC 0xc61
+
+#define CDTVCR_INTDISABLE 0xc04
+#define CDTVCR_INTACK 0xc05
+#define CDTVCR_INTENA 0xc55
+#define CDTVCR_INTREQ 0xc56
+#define CDTVCR_4510_TRIGGER 0x4000
+
+#define CDTVCR_SUBQ 0x906
+#define CDTVCR_SUBBANK 0x917
+#define CDTVCR_SUBC 0x918
+#define CDTVCR_TOC 0xa00
+
+static uae_u8 cdtvcr_4510_ram[CDTVCR_RAM_OFFSET];
static uae_u8 cdtvcr_ram[CDTVCR_RAM_SIZE];
+static uae_u8 cdtvcr_clock[2];
+
+static smp_comm_pipe requests;
+static uae_sem_t sub_sem;
+static volatile int thread_alive;
+static int unitnum = -1;
+static struct cd_toc_head toc;
+static int datatrack;
+static int cdtvcr_media;
+static int subqcnt;
+static int cd_audio_status;
static void cdtvcr_battram_reset (void)
{
return v;
}
-static void cdtvcr_bput2 (uaecptr addr, uae_u32 b)
+static int ismedia (void)
+{
+ cdtvcr_4510_ram[CDTVCR_SYS_STATE] &= ~8;
+ if (unitnum < 0)
+ return 0;
+ if (sys_command_ismedia (unitnum, 0)) {
+ cdtvcr_4510_ram[CDTVCR_SYS_STATE] |= 8;
+ return 1;
+ }
+ return 0;
+}
+
+static int get_qcode (void)
+{
+#if 0
+ if (!sys_command_cd_qcode (unitnum, cdrom_qcode))
+ return 0;
+ cdrom_qcode[1] = cd_audio_status;
+#endif
+ return 1;
+}
+
+static int get_toc (void)
+{
+ uae_u32 msf;
+ uae_u8 *p;
+
+ cdtvcr_4510_ram[CDTVCR_SYS_STATE] &= ~4;
+ datatrack = 0;
+ if (!sys_command_cd_toc (unitnum, &toc))
+ return 0;
+ cdtvcr_4510_ram[CDTVCR_SYS_STATE] |= 4 | 8;
+ if (toc.first_track == 1 && (toc.toc[toc.first_track_offset].control & 0x0c) == 0x04)
+ datatrack = 1;
+ p = &cdtvcr_4510_ram[CDTVCR_TOC];
+ p[0] = toc.first_track;
+ p[1] = toc.last_track;
+ msf = lsn2msf(toc.lastaddress);
+ p[2] = msf >> 16;
+ p[3] = msf >> 8;
+ p[4] = msf >> 0;
+ p += 5;
+ for (int j = toc.first_track_offset; j <= toc.last_track_offset; j++) {
+ struct cd_toc *s = &toc.toc[j];
+ p[0] = (s->adr << 0) | (s->control << 4);
+ p[1] = s->track;
+ msf = lsn2msf(s->address);
+ p[2] = msf >> 16;
+ p[3] = msf >> 8;
+ p[4] = msf >> 0;
+ p += 5;
+ }
+ return 1;
+}
+
+static void cdtvcr_4510_reset(uae_u8 v)
+{
+ cdtvcr_4510_ram[CDTVCR_ID + 0] = 'C';
+ cdtvcr_4510_ram[CDTVCR_ID + 1] = 'D';
+ cdtvcr_4510_ram[CDTVCR_ID + 2] = 'T';
+ cdtvcr_4510_ram[CDTVCR_ID + 3] = 'V';
+
+ if (v == 3) {
+ sys_command_cd_pause (unitnum, 0);
+ sys_command_cd_stop (unitnum);
+ cdtvcr_4510_ram[CDTVCR_CD_PLAYING] = 0;
+ cdtvcr_4510_ram[CDTVCR_CD_STATE] = 0;
+ return;
+ } else if (v == 2 || v == 1) {
+ cdtvcr_4510_ram[CDTVCR_INTENA] = 0;
+ cdtvcr_4510_ram[CDTVCR_INTREQ] = 0;
+ if (v == 1) {
+ memset(cdtvcr_4510_ram, 0, 4096);
+ }
+ cdtvcr_4510_ram[CDTVCR_INTDISABLE] = 1;
+ cdtvcr_4510_ram[CDTVCR_CD_STATE] = 2;
+ }
+
+ if (ismedia())
+ get_toc();
+}
+
+void rethink_cdtvcr(void)
+{
+ if ((cdtvcr_4510_ram[CDTVCR_INTREQ] & cdtvcr_4510_ram[CDTVCR_INTENA]) && !cdtvcr_4510_ram[CDTVCR_INTDISABLE])
+ INTREQ_0 (0x8000 | 0x0008);
+}
+
+static void cdtvcr_cmd_done(void)
+{
+ cdtvcr_4510_ram[CDTVCR_SYS_STATE] &= ~1;
+ cdtvcr_4510_ram[CDTVCR_CD_CMD_DO] = 0;
+ cdtvcr_4510_ram[CDTVCR_INTREQ] |= 0x40;
+ cdtvcr_4510_ram[CDTVCR_CD_CMD_STATUS] = 0;
+ cdtvcr_4510_ram[CDTVCR_CD_CMD_STATUS2] = 0;
+}
+
+static void cdtvcr_play_done(void)
+{
+ cdtvcr_4510_ram[CDTVCR_SYS_STATE] &= ~1;
+ cdtvcr_4510_ram[CDTVCR_CD_CMD_DO] = 0;
+ cdtvcr_4510_ram[CDTVCR_INTREQ] |= 0x80;
+ cdtvcr_4510_ram[CDTVCR_CD_CMD_STATUS] = 0;
+ cdtvcr_4510_ram[CDTVCR_CD_CMD_STATUS2] = 0;
+}
+
+static void cdtvcr_cmd_play_started(void)
+{
+ cdtvcr_cmd_done();
+ cdtvcr_4510_ram[CDTVCR_CD_CMD_STATUS + 2] = 2;
+ cdtvcr_4510_ram[CDTVCR_CD_CMD_STATUS2 + 2] = 0;
+ cdtvcr_4510_ram[CDTVCR_CD_PLAYING] = 1;
+ cdtvcr_4510_ram[CDTVCR_CD_STATE] = 8;
+}
+
+static void cdtvcr_start (void)
+{
+ if (unitnum < 0)
+ return;
+ cdtvcr_4510_ram[CDTVCR_CD_STATE] = 0;
+}
+
+static void cdtvcr_stop (void)
+{
+ if (unitnum < 0)
+ return;
+ sys_command_cd_pause (unitnum, 0);
+ sys_command_cd_stop (unitnum);
+ if (cdtvcr_4510_ram[CDTVCR_CD_PLAYING]) {
+ cdtvcr_4510_ram[CDTVCR_INTREQ] |= 0x80;
+ }
+ cdtvcr_4510_ram[CDTVCR_CD_PLAYING] = 0;
+ cdtvcr_4510_ram[CDTVCR_CD_STATE] = 2;
+}
+
+static void cdtvcr_pause(bool pause)
+{
+ sys_command_cd_pause (unitnum, pause ? 1 : 0);
+ cdtvcr_4510_ram[CDTVCR_CD_STATE] &= ~4;
+ if (pause)
+ cdtvcr_4510_ram[CDTVCR_CD_STATE] |= 4;
+ cdtvcr_cmd_done();
+}
+
+static void setsubchannel(uae_u8 *s)
+{
+ uae_u8 *d;
+
+ // subchannels
+ d = &cdtvcr_4510_ram[CDTVCR_SUBC];
+ cdtvcr_4510_ram[CDTVCR_SUBBANK] = cdtvcr_4510_ram[CDTVCR_SUBBANK] ? 0 : SUB_CHANNEL_SIZE + 2;
+ d[cdtvcr_4510_ram[CDTVCR_SUBBANK] + 0] = 0;
+ d[cdtvcr_4510_ram[CDTVCR_SUBBANK] + 1] = 0;
+ for (int i = 0; i < SUB_CHANNEL_SIZE; i++) {
+ d[cdtvcr_4510_ram[CDTVCR_SUBBANK] + i + 2] = s[i] & 0x3f;
+ }
+
+ // q-channel
+ d = &cdtvcr_4510_ram[CDTVCR_SUBQ];
+ s += SUB_ENTRY_SIZE;
+ /* CtlAdr */
+ d[0] = s[0];
+ /* Track */
+ d[1] = s[1];
+ /* Index */
+ d[2] = s[2];
+ /* TrackPos */
+ d[3] = s[3];
+ d[4] = s[4];
+ d[5] = s[5];
+ /* DiskPos */
+ d[6] = s[6];
+ d[7] = s[7];
+ d[8] = s[8];
+ d[9] = s[9];
+ cdtvcr_4510_ram[CDTVCR_SUBQ - 2] = 1; // qcode valid
+ cdtvcr_4510_ram[CDTVCR_SUBQ - 1] = 0;
+
+ if (cdtvcr_4510_ram[CDTVCR_CD_SUBCODES])
+ cdtvcr_4510_ram[CDTVCR_INTREQ] |= 2 | 4;
+}
+
+static void subfunc(uae_u8 *data, int cnt)
+{
+ uae_u8 out[SUB_CHANNEL_SIZE];
+ sub_to_deinterleaved(data, out);
+ setsubchannel(out);
+}
+
+static int statusfunc(int status)
+{
+ if (status == -1)
+ return 500;
+ if (status == -2)
+ return 75;
+ if (cd_audio_status != status) {
+ if (status == AUDIO_STATUS_PLAY_COMPLETE || status == AUDIO_STATUS_PLAY_ERROR) {
+ cdtvcr_play_done();
+ } else if (status == AUDIO_STATUS_IN_PROGRESS) {
+ cdtvcr_cmd_play_started();
+ }
+ }
+ cd_audio_status = status;
+ return 0;
+}
+
+static void cdtvcr_play(uae_u32 start, uae_u32 end)
+{
+ sys_command_cd_pause(unitnum, 0);
+ if (!sys_command_cd_play(unitnum, start, end, 0, statusfunc, subfunc))
+ cdtvcr_play_done();
+}
+
+static void cdtvcr_play_track(uae_u32 track_start, uae_u32 track_end)
+{
+ int start_found, end_found;
+ uae_u32 start, end;
+
+ start_found = end_found = 0;
+ for (int j = toc.first_track_offset; j <= toc.last_track_offset; j++) {
+ struct cd_toc *s = &toc.toc[j];
+ if (track_start == s->track) {
+ start_found++;
+ start = s->paddress;
+ }
+ if (track_end == s->track) {
+ end = s->paddress;
+ end_found++;
+ }
+ }
+ if (start_found == 0) {
+ write_log (_T("PLAY CD AUDIO: illegal start track %d\n"), track_start);
+ cdtvcr_stop();
+ cdtvcr_cmd_done();
+ return;
+ }
+ cdtvcr_play(start, end);
+}
+
+static void cdtvcr_read_data(uae_u32 start, uae_u32 addr, uae_u32 len)
+{
+ uae_u8 buffer[2048];
+ int didread;
+
+ while (len) {
+ didread = sys_command_cd_read (unitnum, buffer, start, 1);
+ if (!didread)
+ break;
+ for (int i = 0; i < 2048 && len > 0; i++) {
+ put_byte(addr + i, buffer[i]);
+ len--;
+ }
+ addr += 2048;
+ start++;
+ }
+ cdtvcr_cmd_done();
+}
+
+static void cdtvcr_do_cmd(void)
+{
+ uae_u32 addr, len, start, end, datalen;
+ uae_u32 startlsn, endlsn;
+ uae_u8 starttrack, endtrack;
+ uae_u8 *p = &cdtvcr_4510_ram[CDTVCR_CD_CMD];
+
+ cdtvcr_4510_ram[CDTVCR_SYS_STATE] |= 1;
+ cdtvcr_4510_ram[CDTVCR_CD_CMD_STATUS] = 2;
+ cdtvcr_4510_ram[CDTVCR_CD_CMD_STATUS2] = 0;
+ write_log(_T("CDTVCR CD command %02x\n"), p[0]);
+ for(int i = 0; i < 14; i++)
+ write_log(_T(".%02x"), p[i]);
+ write_log(_T("\n"));
+
+ start = (p[1] << 16) | (p[2] << 8) | (p[3] << 0);
+ startlsn = msf2lsn(start);
+ end = (p[4] << 16) | (p[5] << 8) | (p[6] << 0);
+ endlsn = msf2lsn(end);
+ addr = (p[7] << 24) | (p[8] << 16) | (p[9] << 8) | (p[10] << 0);
+ len = (p[4] << 16) | (p[5] << 8) | (p[6] << 0);
+ datalen = (p[11] << 16) | (p[12] << 8) | (p[13] << 0);
+ starttrack = p[1];
+ endtrack = p[3];
+
+ switch(p[0])
+ {
+ case 2: // start
+ cdtvcr_start();
+ cdtvcr_cmd_done();
+ break;
+ case 3: // stop
+ cdtvcr_stop();
+ cdtvcr_cmd_done();
+ break;
+ case 4: // toc
+ cdtvcr_stop();
+ get_toc();
+ cdtvcr_cmd_done();
+ break;
+ case 6: // play
+ cdtvcr_stop();
+ cdtvcr_play(startlsn, endlsn);
+ break;
+ case 7: // play track
+ cdtvcr_stop();
+ cdtvcr_play_track(starttrack, endtrack);
+ break;
+ case 8: // read
+ cdtvcr_stop();
+ cdtvcr_read_data(start, addr, datalen);
+ break;
+ case 9:
+ cdtvcr_pause(true);
+ break;
+ case 10:
+ cdtvcr_pause(false);
+ break;
+ case 11: // stop play
+ cdtvcr_stop();
+ cdtvcr_cmd_done();
+ break;
+ default:
+ write_log(_T("unsupported command!\n"));
+ break;
+ }
+}
+
+static void cdtvcr_4510_do_something(void)
+{
+ if (cdtvcr_4510_ram[CDTVCR_INTACK]) {
+ cdtvcr_4510_ram[CDTVCR_INTACK] = 0;
+ rethink_cdtvcr();
+ }
+ if (cdtvcr_4510_ram[CDTVCR_CD_CMD_DO]) {
+ cdtvcr_4510_ram[CDTVCR_SYS_STATE] |= 1;
+ write_comm_pipe_u32 (&requests, 0x0100, 1);
+ }
+}
+
+static bool cdtvcr_debug(uaecptr addr)
{
addr &= CDTVCR_MASK;
- if (addr >= CDTVCR_RAM_OFFSET && addr < CDTVCR_RAM_OFFSET + CDTVCR_RAM_SIZE) {
- addr -= CDTVCR_RAM_OFFSET;
- cdtvcr_battram_write(addr, b);
+ return !(addr >= CDTVCR_RAM_OFFSET && addr < CDTVCR_RAM_OFFSET + CDTVCR_RAM_SIZE);
+}
+
+static void cdtvcr_bput2 (uaecptr addr, uae_u8 v)
+{
+ addr &= CDTVCR_MASK;
+ if (addr == CDTVCR_4510_TRIGGER) {
+ if (v & 0x80)
+ cdtvcr_4510_do_something();
+ } else if (addr >= CDTVCR_RAM_OFFSET && addr < CDTVCR_RAM_OFFSET + CDTVCR_RAM_SIZE) {
+ cdtvcr_battram_write(addr - CDTVCR_RAM_OFFSET, v);
+ } else if (addr >= CDTVCR_CLOCK && addr < CDTVCR_CLOCK + 0x20) {
+ int reg = addr - CDTVCR_CLOCK;
+ switch (reg)
+ {
+ case 0:
+ cdtvcr_clock[0] = v;
+ case 1:
+ cdtvcr_clock[1] = v;
+ break;
+ }
+ } else {
+ switch(addr)
+ {
+ case CDTVCR_RESET:
+ cdtvcr_4510_reset(v);
+ break;
+ }
}
+ if (addr >= 0xc00 && addr < CDTVCR_RAM_OFFSET)
+ cdtvcr_4510_ram[addr] = v;
}
+
static uae_u8 cdtvcr_bget2 (uaecptr addr)
{
uae_u8 v = 0;
addr &= CDTVCR_MASK;
+ if (addr < CDTVCR_RAM_OFFSET) {
+ v = cdtvcr_4510_ram[addr];
+ }
if (addr >= CDTVCR_RAM_OFFSET && addr < CDTVCR_RAM_OFFSET + CDTVCR_RAM_SIZE) {
- addr -= CDTVCR_RAM_OFFSET;
- v = cdtvcr_battram_read(addr);
- } else if (addr == 0x9dc) {
- v = 'C';
- } else if (addr == 0x9dd) {
- v = 'D';
- } else if (addr == 0x9de) {
- v = 'T';
- } else if (addr == 0x9df) {
- v = 'V';
+ v = cdtvcr_battram_read(addr - CDTVCR_RAM_OFFSET);
} else if (addr >= CDTVCR_CLOCK && addr < CDTVCR_CLOCK + 0x20) {
int reg = addr - CDTVCR_CLOCK;
int days, mins, ticks;
{
case 0:
case 1:
- v = 0;
+ v = cdtvcr_clock[reg];
break;
case 2:
v = days >> 8;
break;
}
-
+ } else {
+ switch(addr)
+ {
+ case CDTVCR_RESET:
+ v = 0;
+ break;
+ }
}
return v;
}
v = (cdtvcr_bget2 (addr) << 24) | (cdtvcr_bget2 (addr + 1) << 16) |
(cdtvcr_bget2 (addr + 2) << 8) | (cdtvcr_bget2 (addr + 3));
#if CDTVCR_DEBUG
- write_log (_T("cdtvcr_lget %08X=%08X PC=%08X\n"), addr, v, M68K_GETPC);
+ if (cdtvcr_debug(addr))
+ write_log (_T("cdtvcr_lget %08X=%08X PC=%08X\n"), addr, v, M68K_GETPC);
#endif
return v;
}
#endif
v = (cdtvcr_bget2 (addr) << 8) | cdtvcr_bget2 (addr + 1);
#if CDTVCR_DEBUG
- write_log (_T("cdtvcr_wget %08X=%04X PC=%08X\n"), addr, v, M68K_GETPC);
+ if (cdtvcr_debug(addr))
+ write_log (_T("cdtvcr_wget %08X=%04X PC=%08X\n"), addr, v, M68K_GETPC);
#endif
return v;
}
special_mem |= S_READ;
#endif
v = cdtvcr_bget2 (addr);
+#if CDTVCR_DEBUG
+ if (cdtvcr_debug(addr))
+ write_log (_T("cdtvcr_bget %08X=%02X PC=%08X\n"), addr, v, M68K_GETPC);
+#endif
return v;
}
special_mem |= S_WRITE;
#endif
#if CDTVCR_DEBUG
- write_log (_T("cdtvcr_lput %08X=%08X PC=%08X\n"), addr, l, M68K_GETPC);
+ if (cdtvcr_debug(addr))
+ write_log (_T("cdtvcr_lput %08X=%08X PC=%08X\n"), addr, l, M68K_GETPC);
#endif
cdtvcr_bput2 (addr, l >> 24);
cdtvcr_bput2 (addr + 1, l >> 16);
special_mem |= S_WRITE;
#endif
#if CDTVCR_DEBUG
- write_log (_T("cdtvcr_wput %08X=%04X PC=%08X\n"), addr, w & 65535, M68K_GETPC);
+ if (cdtvcr_debug(addr))
+ write_log (_T("cdtvcr_wput %08X=%04X PC=%08X\n"), addr, w & 65535, M68K_GETPC);
#endif
cdtvcr_bput2 (addr, w >> 8);
cdtvcr_bput2 (addr + 1, w);
{
#ifdef JIT
special_mem |= S_WRITE;
+#endif
+#if CDTVCR_DEBUG
+ if (cdtvcr_debug(addr))
+ write_log (_T("cdtvcr_bput %08X=%02X PC=%08X\n"), addr, b & 255, M68K_GETPC);
#endif
cdtvcr_bput2 (addr, b);
}
cdtvcr_lget, cdtvcr_wget, cdtvcr_bget,
cdtvcr_lput, cdtvcr_wput, cdtvcr_bput,
default_xlate, default_check, NULL, NULL, _T("CDTV-CR"),
- cdtvcr_lgeti, cdtvcr_wgeti, ABFLAG_IO
+ cdtvcr_lgeti, cdtvcr_wgeti, ABFLAG_IO | ABFLAG_SAFE
};
+static void *dev_thread (void *p)
+{
+ write_log (_T("CDTV-CR: CD thread started\n"));
+ thread_alive = 1;
+ for (;;) {
+
+ uae_u32 b = read_comm_pipe_u32_blocking (&requests);
+ if (b == 0xffff) {
+ thread_alive = -1;
+ return NULL;
+ }
+ if (unitnum < 0)
+ continue;
+ switch (b)
+ {
+ case 0x0100:
+ cdtvcr_do_cmd();
+ break;
+ case 0x0101:
+ {
+ int m = ismedia ();
+ if (m < 0) {
+ write_log (_T("CDTV: device %d lost\n"), unitnum);
+ cdtvcr_4510_ram[CDTVCR_SYS_STATE] &= ~(4 | 8);
+ } else if (m != cdtvcr_media) {
+ cdtvcr_media = m;
+ get_toc ();
+ }
+ if (cdtvcr_media)
+ get_qcode ();
+ }
+ break;
+ }
+ }
+}
+
+void CDTVCR_hsync_handler (void)
+{
+ static int subqcnt;
+
+ if (!currprefs.cs_cdtvcr)
+ return;
+
+ subqcnt--;
+ if (subqcnt < 0) {
+ write_comm_pipe_u32 (&requests, 0x0101, 1);
+ subqcnt = 75;
+ // want subcodes but not playing?
+ if (cdtvcr_4510_ram[CDTVCR_CD_SUBCODES] && !cdtvcr_4510_ram[CDTVCR_CD_PLAYING]) {
+ // just return fake stuff, for some reason cdtv-cr driver requires something
+ // that looks validg, even when not playing or it gets in infinite loop
+ uae_u8 dst[SUB_CHANNEL_SIZE];
+ // regenerate Q-subchannel
+ uae_u8 *s = dst + 12;
+ struct cd_toc *cdtoc = &toc.toc[toc.first_track];
+ int sector = 150;
+ memset (dst, 0, SUB_CHANNEL_SIZE);
+ s[0] = (cdtoc->control << 4) | (cdtoc->adr << 0);
+ s[1] = tobcd (cdtoc->track);
+ s[2] = tobcd (1);
+ int msf = lsn2msf (sector);
+ tolongbcd (s + 7, msf);
+ msf = lsn2msf (sector - cdtoc->address - 150);
+ tolongbcd (s + 3, msf);
+ setsubchannel(dst);
+ }
+ }
+}
+
+static void open_unit (void)
+{
+ struct device_info di;
+ unitnum = get_standard_cd_unit (CD_STANDARD_UNIT_CDTV);
+ sys_command_info (unitnum, &di, 0);
+ write_log (_T("using drive %s (unit %d, media %d)\n"), di.label, unitnum, di.media_inserted);
+}
+
+static void close_unit (void)
+{
+ if (unitnum >= 0)
+ sys_command_close (unitnum);
+ unitnum = -1;
+}
+
void cdtvcr_reset(void)
{
+ close_unit ();
+ if (!thread_alive) {
+ init_comm_pipe (&requests, 100, 1);
+ uae_start_thread (_T("cdtv-cr"), dev_thread, NULL, NULL);
+ while (!thread_alive)
+ sleep_millis (10);
+ uae_sem_init (&sub_sem, 0, 1);
+ }
+ open_unit ();
+ gui_flicker_led (LED_CD, 0, -1);
+
+ cdtvcr_4510_reset(0);
cdtvcr_battram_reset();
+ cdtvcr_clock[0] = 0xe3;
+ cdtvcr_clock[1] = 0x1b;
}
void cdtvcr_free(void)
{
+ if (thread_alive > 0) {
+ write_comm_pipe_u32 (&requests, 0xffff, 1);
+ while (thread_alive > 0)
+ sleep_millis (10);
+ uae_sem_destroy (&sub_sem);
+ }
+ thread_alive = 0;
+ close_unit ();
}
cfgfile_dwrite_bool(f, _T("cd32nvram"), p->cs_cd32nvram);
cfgfile_dwrite_bool(f, _T("cd32fmv"), p->cs_cd32fmv);
cfgfile_dwrite_bool(f, _T("cdtvcd"), p->cs_cdtvcd);
+ cfgfile_dwrite_bool(f, _T("cdtv-cr"), p->cs_cdtvcr);
cfgfile_dwrite_bool (f, _T("cdtvram"), p->cs_cdtvram);
cfgfile_dwrite (f, _T("cdtvramcard"), _T("%d"), p->cs_cdtvcard);
cfgfile_dwrite_str (f, _T("ide"), p->cs_ide == IDE_A600A1200 ? _T("a600/a1200") : (p->cs_ide == IDE_A4000 ? _T("a4000") : _T("none")));
|| cfgfile_yesno(option, value, _T("cd32nvram"), &p->cs_cd32nvram)
|| cfgfile_yesno(option, value, _T("cd32fmv"), &p->cs_cd32fmv)
|| cfgfile_yesno(option, value, _T("cdtvcd"), &p->cs_cdtvcd)
+ || cfgfile_yesno(option, value, _T("cdtv-cr"), &p->cs_cdtvcr)
|| cfgfile_yesno (option, value, _T("cdtvram"), &p->cs_cdtvram)
|| cfgfile_yesno (option, value, _T("a1000ram"), &p->cs_a1000ram)
|| cfgfile_yesno (option, value, _T("pcmcia"), &p->cs_pcmcia)
p->cs_resetwarning = 0;
p->cs_ciatodbug = false;
+ _tcscpy (p->romextfile, _T(""));
+ _tcscpy (p->romextfile2, _T(""));
+
p->prtname[0] = 0;
p->sername[0] = 0;
roms[2] = -1;
if (!configure_rom (p, roms, romcheck))
return 0;
- roms[0] = 107;
- roms[1] = -1;
+ roms[0] = 108;
+ roms[1] = 107;
+ roms[2] = -1;
if (!configure_rom (p, roms, romcheck))
return 0;
return 1;
{
int roms[4];
+ if (config >= 2)
+ return bip_cdtvcr(p, config - 2, compa, romcheck);
+
p->bogomem_size = 0;
p->chipmem_size = 0x100000;
p->chipset_mask = CSMASK_ECS_AGNUS;
v = bip_cdtv (p, config, compa, romcheck);
break;
case 10:
- v = bip_cdtvcr(p, config, compa, romcheck);
- break;
- case 11:
v = bip_arcadia (p, config , compa, romcheck);
break;
- case 12:
+ case 11:
v = bip_super (p, config, compa, romcheck);
break;
}
#define P5_SET_CLEAR 0x80
/* REQ_RESET 0x00 */
-// 0x10/0x08/0x04 only work if P5_SELF_RESET is cleared
+// M68K can only reset PPC and vice versa
+// if P5_SELF_RESET is not active.
#define P5_PPC_RESET 0x10
#define P5_M68K_RESET 0x08
#define P5_AMIGA_RESET 0x04
#define CS_RAM_BASE 0x0c000000
-#define BLIZZARD_RAM_BASE 0x68000000
-#define BLIZZARD_RAM_ALIAS_BASE 0x48000000
+#define BLIZZARD_RAM_BASE_48 0x48000000
+#define BLIZZARD_RAM_BASE_68 0x68000000
+#define BLIZZARD_RAM_256M_BASE_40 0x40000000
+#define BLIZZARD_RAM_256M_BASE_70 0x70000000
#define BLIZZARD_MAPROM_BASE 0x4ff80000
#define BLIZZARD_MAPROM_ENABLE 0x80ffff00
#define BLIZZARD_BOARD_DISABLE 0x80fa0000
write_log(_T("CS: SCSI reset\n"));
map_banks(&blizzardf0_bank, 0xf00000 >> 16, 0x60000 >> 16, 0);
}
- if ((oldval & P5_PPC_RESET) && !(regval & P5_PPC_RESET)) {
- uae_ppc_cpu_stop();
- } else if (!(oldval & P5_PPC_RESET) && (regval & P5_PPC_RESET)) {
- uae_ppc_cpu_reboot();
+ if (!(io_reg[CSIII_REG_SHADOW] & P5_SELF_RESET) || uae_self_is_ppc() == false) {
+ if ((oldval & P5_PPC_RESET) && !(regval & P5_PPC_RESET)) {
+ uae_ppc_cpu_stop();
+ } else if (!(oldval & P5_PPC_RESET) && (regval & P5_PPC_RESET)) {
+ uae_ppc_cpu_reboot();
+ }
+ } else {
+ io_reg[CSIII_REG_RESET] &= ~P5_PPC_RESET;
+ io_reg[CSIII_REG_RESET] |= oldval & P5_PPC_RESET;
}
- if ((regval & P5_M68K_RESET) && !(oldval & P5_M68K_RESET)) {
- m68k_reset();
- write_log(_T("CS: M68K Reset\n"));
- } else if (!(regval & P5_M68K_RESET) && (oldval & P5_M68K_RESET)) {
- write_log(_T("CS: M68K Halted\n"));
- if (!(regval & P5_PPC_RESET)) {
- write_log(_T("CS: PPC is also halted. STOP.\n"));
- cpu_halt(5);
- } else {
- // halt 68k, leave ppc message processing active.
- cpu_halt(-1);
+ if (!(io_reg[CSIII_REG_SHADOW] & P5_SELF_RESET) || uae_self_is_ppc() == true) {
+ if ((regval & P5_M68K_RESET) && !(oldval & P5_M68K_RESET)) {
+ m68k_reset();
+ write_log(_T("CS: M68K Reset\n"));
+ } else if (!(regval & P5_M68K_RESET) && (oldval & P5_M68K_RESET)) {
+ write_log(_T("CS: M68K Halted\n"));
+ if (!(regval & P5_PPC_RESET)) {
+ write_log(_T("CS: PPC is also halted. STOP.\n"));
+ cpu_halt(5);
+ } else {
+ // halt 68k, leave ppc message processing active.
+ cpu_halt(-1);
+ }
}
+ } else {
+ io_reg[CSIII_REG_RESET] &= ~P5_M68K_RESET;
+ io_reg[CSIII_REG_RESET] |= oldval & P5_M68K_RESET;
}
if (!(io_reg[CSIII_REG_SHADOW] & P5_SELF_RESET)) {
if (!(regval & P5_AMIGA_RESET)) {
return;
if (is_blizzard() || is_blizzardppc()) {
if (cpuboard_size) {
- if (blizzard_jit) {
- map_banks(&blizzardram_bank, blizzardram_bank.start >> 16, cpuboard_size >> 16, 0);
- map_banks(&blizzardram_bank, BLIZZARD_RAM_BASE >> 16, cpuboard_size >> 16, 0);
- } else {
- for (int i = 0; i < 0x08000000; i += cpuboard_size) {
- map_banks_nojitdirect(&blizzardram_nojit_bank, (BLIZZARD_RAM_ALIAS_BASE + i) >> 16, cpuboard_size >> 16, 0);
- map_banks_nojitdirect(&blizzardram_nojit_bank, (BLIZZARD_RAM_BASE + i) >> 16, cpuboard_size >> 16, 0);
- }
- if (currprefs.maprom && !is_blizzardppc()) {
+ if (cpuboard_size < 256 * 1024 * 1024) {
+ if (blizzard_jit) {
+ map_banks(&blizzardram_bank, blizzardram_bank.start >> 16, cpuboard_size >> 16, 0);
+ map_banks(&blizzardram_bank, BLIZZARD_RAM_BASE_68 >> 16, cpuboard_size >> 16, 0);
+ } else {
for (int i = 0; i < 0x08000000; i += cpuboard_size) {
- map_banks_nojitdirect(&blizzardmaprom_bank, (BLIZZARD_RAM_ALIAS_BASE + i + cpuboard_size - 524288) >> 16, 524288 >> 16, 0);
- map_banks_nojitdirect(&blizzardmaprom_bank, (BLIZZARD_RAM_BASE + i + cpuboard_size - 524288) >> 16, 524288 >> 16, 0);
+ map_banks_nojitdirect(&blizzardram_nojit_bank, (BLIZZARD_RAM_BASE_48 + i) >> 16, cpuboard_size >> 16, 0);
+ map_banks_nojitdirect(&blizzardram_nojit_bank, (BLIZZARD_RAM_BASE_68 + i) >> 16, cpuboard_size >> 16, 0);
+ }
+ if (currprefs.maprom && !is_blizzardppc()) {
+ for (int i = 0; i < 0x08000000; i += cpuboard_size) {
+ map_banks_nojitdirect(&blizzardmaprom_bank, (BLIZZARD_RAM_BASE_48 + i + cpuboard_size - 524288) >> 16, 524288 >> 16, 0);
+ map_banks_nojitdirect(&blizzardmaprom_bank, (BLIZZARD_RAM_BASE_68 + i + cpuboard_size - 524288) >> 16, 524288 >> 16, 0);
+ }
}
}
+ } else {
+ map_banks(&blizzardram_bank, blizzardram_bank.start >> 16, cpuboard_size >> 16, 0);
}
}
if (!is_blizzardppc()) {
mapped_malloc(&blizzardea_bank);
} else if (is_blizzard() || is_blizzardppc()) {
- blizzardram_bank.start = BLIZZARD_RAM_ALIAS_BASE;
- blizzardram_bank.allocated = cpuboard_size;
- blizzardram_bank.mask = blizzardram_bank.allocated - 1;
- blizzardram_bank.startmask = BLIZZARD_RAM_BASE;
+ if (cpuboard_size < 256 * 1024 * 1024) {
+ blizzardram_bank.start = BLIZZARD_RAM_BASE_48;
+ blizzardram_bank.allocated = cpuboard_size;
+ blizzardram_bank.mask = blizzardram_bank.allocated - 1;
+ blizzardram_bank.startmask = BLIZZARD_RAM_BASE_68;
+ } else if (currprefs.z3autoconfig_start <= 0x10000000) {
+ blizzardram_bank.start = BLIZZARD_RAM_256M_BASE_40;
+ blizzardram_bank.allocated = cpuboard_size;
+ blizzardram_bank.mask = blizzardram_bank.allocated - 1;
+ blizzardram_bank.startmask = BLIZZARD_RAM_256M_BASE_40;
+ } else {
+ blizzardram_bank.start = BLIZZARD_RAM_256M_BASE_70;
+ blizzardram_bank.allocated = cpuboard_size;
+ blizzardram_bank.mask = blizzardram_bank.allocated - 1;
+ blizzardram_bank.startmask = BLIZZARD_RAM_256M_BASE_70;
+ }
blizzardram_nojit_bank.start = blizzardram_bank.start;
blizzardram_nojit_bank.allocated = blizzardram_bank.allocated;
blizzardram_nojit_bank.startmask = blizzardram_bank.startmask;
- blizzard_jit = 0 && BLIZZARD_RAM_BASE + blizzardram_bank.allocated <= max_z3fastmem && currprefs.jit_direct_compatible_memory;
+ blizzard_jit = cpuboard_jitdirectompatible(&currprefs);
if (blizzard_jit) {
if (cpuboard_size) {
- blizzardram_bank.label = _T("blizzard");
+ if (cpuboard_size < 256 * 1024 * 1024)
+ blizzardram_bank.label = _T("blizzard");
+ else
+ blizzardram_bank.label = _T("blizzard_70");
mapped_malloc(&blizzardram_bank);
}
} else {
}
return true;
}
+bool cpuboard_jitdirectompatible(struct uae_prefs *p)
+{
+ if (cpuboard_memorytype(p) == BOARD_MEMORY_BLIZZARD_12xx || cpuboard_memorytype(p) == BOARD_MEMORY_BLIZZARD_PPC) {
+ return false;
+ }
+ return true;
+}
int cpuboard_memorytype(struct uae_prefs *p)
{
case BOARD_A2630:
return BOARD_MEMORY_Z2;
case BOARD_BLIZZARD_1230_IV:
+ case BOARD_BLIZZARD_1230_IV_SCSI:
case BOARD_BLIZZARD_1260:
+ case BOARD_BLIZZARD_1260_SCSI:
+ return BOARD_MEMORY_BLIZZARD_12xx;
case BOARD_BLIZZARDPPC:
- return BOARD_MEMORY_BLIZZARD;
+ return BOARD_MEMORY_BLIZZARD_PPC;
default:
write_log(_T("Missing board type %d!\n"), p->cpuboard_type);
return BOARD_MEMORY_HIGHMEM;
}
}
+int cpuboard_maxmemory(struct uae_prefs *p)
+{
+ if (p->cpuboard_type == BOARD_BLIZZARDPPC)
+ return 256 * 1024 * 1024;
+ int type = cpuboard_memorytype(p);
+ switch (type)
+ {
+ case BOARD_MEMORY_BLIZZARD_12xx:
+ case BOARD_MEMORY_BLIZZARD_PPC:
+ return 256 * 1024 * 1024;
+ case BOARD_MEMORY_HIGHMEM:
+ return 128 * 1024 * 1024;
+ case BOARD_MEMORY_Z2:
+ return 8 * 1024 * 1024;
+ default:
+ return 0;
+ }
+}
+
void cpuboard_io_special_write(uaecptr addr, uae_u32 val)
{
blizzarde8_wput(addr, val);
#include "akiko.h"
#include "cd32_fmv.h"
#include "cdtv.h"
+#include "cdtvcr.h"
#if defined(ENFORCER)
#include "enforcer.h"
#endif
rethink_a2091 ();
#endif
#ifdef CDTV
- rethink_cdtv ();
+ rethink_cdtv();
+ rethink_cdtvcr();
#endif
#ifdef CD32
rethink_akiko ();
#endif
#ifdef CDTV
CDTV_hsync_handler ();
+ CDTVCR_hsync_handler ();
#endif
decide_blitter (-1);
if (regs.halted && ppc_state)
return false;
#endif
- return p->jit_direct_compatible_memory || cpuboard_memorytype(p) == BOARD_MEMORY_BLIZZARD;
+ return p->jit_direct_compatible_memory || cpuboard_memorytype(p) == BOARD_MEMORY_BLIZZARD_12xx;
}
/* Ugly hack for >2M chip RAM in single pool
}
#endif
#ifdef CDTV
- if (currprefs.cs_cdtvcd) {
+ if (currprefs.cs_cdtvcd && !currprefs.cs_cdtvcr) {
card_flags[cardno] = 0;
card_name[cardno] = _T("CDTV DMAC");
card_init[cardno] = expamem_init_cdtv;
void cdtvcr_reset(void);
void cdtvcr_free(void);
+void rethink_cdtvcr(void);
+
+extern void CDTVCR_hsync_handler(void);
+
extern void cpuboard_hsync(void);
extern void cpuboard_rethink(void);
extern int cpuboard_memorytype(struct uae_prefs *p);
+extern int cpuboard_maxmemory(struct uae_prefs *p);
+extern bool cpuboard_jitdirectompatible(struct uae_prefs *p);
extern bool is_ppc_cpu(struct uae_prefs *);
extern void cpuboard_io_special_write(uaecptr addr, uae_u32 val);
extern void cpuboard_overlay_override(void);
#define BOARD_MEMORY_Z2 1
#define BOARD_MEMORY_Z3 2
#define BOARD_MEMORY_HIGHMEM 3
-#define BOARD_MEMORY_BLIZZARD 4
+#define BOARD_MEMORY_BLIZZARD_12xx 4
+#define BOARD_MEMORY_BLIZZARD_PPC 5
#define BOARD_BLIZZARD_1230_IV 1
#define BOARD_BLIZZARD_1230_IV_SCSI 2
uae_u32 pcr;
uae_u32 address_space_mask;
- uae_u8 panic;
- uae_u32 panic_pc, panic_addr;
-
uae_u32 prefetch020[CPU_PIPELINE_MAX];
uae_u32 prefetch020addr;
uae_u32 cacheholdingdata020;
void uae_ppc_hsync_handler(void);
void uae_ppc_wakeup(void);
void ppc_map_banks(uae_u32, uae_u32, const TCHAR*, void*, bool);
+bool uae_self_is_ppc(void);
void uae_ppc_execute_quick(void);
void uae_ppc_execute_check(void);
mousehack_alive_cnt = 0;
vp_xoffset = vp_yoffset = 0;
tablet_data = 0;
- if (mousehack_address)
+ if (mousehack_address && valid_address(mousehack_address + MH_E, 1))
put_byte (mousehack_address + MH_E, 0);
mousehack_address = 0;
mousehack_enabled = false;
mode |= 1;
if (inputdevice_is_tablet () > 0)
mode |= 2;
- if (mousehack_address) {
+ if (mousehack_address && valid_address(mousehack_address + MH_E, 1)) {
write_log (_T("Mouse driver enabled (%s)\n"), ((mode & 3) == 3 ? _T("tablet+mousehack") : ((mode & 3) == 2) ? _T("tablet") : _T("mousehack")));
put_byte (mousehack_address + MH_E, mode);
mousehack_enabled = true;
inputdevice_update_tablet_params();
}
-
void getgfxoffset (float *dx, float *dy, float*, float*);
static void inputdevice_mh_abs (int x, int y, uae_u32 buttonbits)
if (p->cpu_cycle_exact)
p->cpu_compatible = true;
- if (cpuboard_memorytype(p) == BOARD_MEMORY_BLIZZARD && !p->comptrustbyte) {
+ if (p->cpuboard_type && cpuboard_jitdirectompatible(p) && !p->comptrustbyte) {
error_log(_T("JIT direct is not compatible with emulated Blizzard accelerator boards."));
p->comptrustbyte = 1;
p->comptrustlong = 1;
built_in_chipset_prefs (p);
fixup_cpu (p);
- if (cpuboard_memorytype(p) == BOARD_MEMORY_HIGHMEM)
+
+ if (p->cpuboard_type && p->cpuboardmem1_size > cpuboard_maxmemory(p)) {
+ error_log(_T("Unsupported accelerator board memory size %d (0x%x).\n"), p->cpuboardmem1_size, p->cpuboardmem1_size);
+ p->cpuboardmem1_size = cpuboard_maxmemory(p);
+ }
+ if (cpuboard_memorytype(p) == BOARD_MEMORY_HIGHMEM) {
p->mbresmem_high_size = p->cpuboardmem1_size;
- else if (cpuboard_memorytype(p) == BOARD_MEMORY_Z2)
+ } else if (cpuboard_memorytype(p) == BOARD_MEMORY_Z2) {
p->fastmem_size = p->cpuboardmem1_size;
+ }
if (((p->chipmem_size & (p->chipmem_size - 1)) != 0 && p->chipmem_size != 0x180000)
|| p->chipmem_size < 0x20000
static int be_cnt;
-uae_u8 *REGPARAM2 default_xlate (uaecptr a)
+uae_u8 *REGPARAM2 default_xlate (uaecptr addr)
{
+ int size = currprefs.cpu_model >= 68020 ? 4 : 2;
if (quit_program == 0) {
/* do this only in 68010+ mode, there are some tricky A500 programs.. */
if ((currprefs.cpu_model > 68000 || !currprefs.cpu_compatible) && !currprefs.mmu_model) {
#endif
if (be_cnt < 3) {
int i, j;
- uaecptr a2 = a - 32;
+ uaecptr a2 = addr - 32;
uaecptr a3 = m68k_getpc () - 32;
- write_log (_T("Your Amiga program just did something terribly stupid %08X PC=%08X\n"), a, M68K_GETPC);
+ write_log (_T("Your Amiga program just did something terribly stupid %08X PC=%08X\n"), addr, M68K_GETPC);
if (debugging || DEBUG_STUPID) {
activate_debugger ();
m68k_dumpstate (0);
}
memory_map_dump ();
}
- be_cnt++;
- if (regs.s || be_cnt > 1000) {
- cpu_halt (3);
- be_cnt = 0;
+ if (0 || (gary_toenb && (gary_nonrange(addr) || (size > 1 && gary_nonrange(addr + size - 1))))) {
+ exception2 (addr, false, size, regs.s ? 4 : 0);
} else {
- regs.panic = 4;
- regs.panic_pc = m68k_getpc ();
- regs.panic_addr = a;
- set_special (SPCFLAG_BRK);
+ cpu_halt(3);
}
}
}
}
#endif
#ifdef CDTV
- if (currprefs.cs_cdtvcr)
+ if (currprefs.cs_cdtvcr) {
map_banks(&cdtvcr_bank, 0xB8, 1, 0);
- if (currprefs.cs_cdtvcd)
+ } else if (currprefs.cs_cdtvcd) {
cdtv_check_banks ();
+ }
#endif
#ifdef A2091
if (currprefs.cs_mbdmac == 1)
return (munge24 (pc) & 0xFFFF0000) == rtarea_base && uae_boot_rom;
}
+STATIC_INLINE void wait_memory_cycles (void)
+{
+ if (regs.memory_waitstate_cycles) {
+ x_do_cycles(regs.memory_waitstate_cycles);
+ regs.memory_waitstate_cycles = 0;
+ }
+ if (regs.ce020extracycles >= 16) {
+ regs.ce020extracycles = 0;
+ x_do_cycles(4 * CYCLE_UNIT);
+ }
+}
+
+STATIC_INLINE int adjust_cycles (int cycles)
+{
+ int mc = regs.memory_waitstate_cycles;
+ regs.memory_waitstate_cycles = 0;
+ if (currprefs.m68k_speed < 0 || cycles_mult == 0)
+ return cycles + mc;
+ cpu_cycles *= cycles_mult;
+ cpu_cycles /= CYCLES_DIV;
+ return cpu_cycles + mc;
+}
+
void REGPARAM2 MakeSR (void)
{
regs.sr = ((regs.t1 << 15) | (regs.t0 << 14)
exception_trace (nr);
}
+static void add_approximate_exception_cycles(int nr)
+{
+ int cycles;
+
+ if (currprefs.cpu_model > 68000)
+ return;
+ if (nr >= 24 && nr <= 31) {
+ /* Interrupts */
+ cycles = 44 + 4;
+ } else if (nr >= 32 && nr <= 47) {
+ /* Trap (total is 34, but cpuemux.c already adds 4) */
+ cycles = 34 -4;
+ } else {
+ switch (nr)
+ {
+ case 2: cycles = 50; break; /* Bus error */
+ case 3: cycles = 50; break; /* Address error */
+ case 4: cycles = 34; break; /* Illegal instruction */
+ case 5: cycles = 38; break; /* Division by zero */
+ case 6: cycles = 40; break; /* CHK */
+ case 7: cycles = 34; break; /* TRAPV */
+ case 8: cycles = 34; break; /* Privilege violation */
+ case 9: cycles = 34; break; /* Trace */
+ case 10: cycles = 34; break; /* Line-A */
+ case 11: cycles = 34; break; /* Line-F */
+ default:
+ cycles = 4;
+ break;
+ }
+ }
+ cycles = adjust_cycles(cycles * CYCLE_UNIT / 2);
+ x_do_cycles(cycles);
+}
static void Exception_normal (int nr)
{
x_put_word (m68k_areg (regs, 7), nr * 4);
}
} else {
+ add_approximate_exception_cycles(nr);
currpc = m68k_getpc ();
if (nr == 2 || nr == 3) {
// 68000 address error
set_special(SPCFLAG_CHECK);
}
#endif
+ regs.s = 1;
v = get_long (4);
m68k_areg (regs, 7) = get_long (0);
m68k_setpc_normal(v);
- regs.s = 1;
regs.m = 0;
regs.stopped = 0;
regs.t1 = 0;
#endif
-STATIC_INLINE void wait_memory_cycles (void)
-{
- if (regs.memory_waitstate_cycles) {
- x_do_cycles(regs.memory_waitstate_cycles);
- regs.memory_waitstate_cycles = 0;
- }
- if (regs.ce020extracycles >= 16) {
- regs.ce020extracycles = 0;
- x_do_cycles(4 * CYCLE_UNIT);
- }
-}
-
-STATIC_INLINE int adjust_cycles (int cycles)
-{
- int mc = regs.memory_waitstate_cycles;
- regs.memory_waitstate_cycles = 0;
- if (currprefs.m68k_speed < 0 || cycles_mult == 0)
- return cycles + mc;
- cpu_cycles *= cycles_mult;
- cpu_cycles /= CYCLES_DIV;
- return cpu_cycles + mc;
-}
-
static void bus_error(void)
{
TRY (prb2) {
void cpu_halt (int id)
{
+ // id < 0: m68k halted, PPC active.
+ // id > 0: emulation halted.
if (!regs.halted) {
write_log (_T("CPU halted: reason = %d\n"), id);
regs.halted = id;
if (debugging)
debug ();
#endif
- if (regs.panic) {
- regs.panic = 0;
- /* program jumped to non-existing memory and cpu was >= 68020 */
- get_real_address (regs.isp); /* stack in no one's land? -> halt */
- if (regs.isp & 1)
- regs.panic = 5;
- if (!regs.panic)
- exception2_handle (regs.panic_pc, regs.panic_addr);
- if (regs.panic) {
- int id = regs.panic;
- /* system is very badly confused */
- regs.panic = 0;
- cpu_halt (id);
- }
- }
-
if (regs.spcflags & SPCFLAG_MODE_CHANGE) {
if (cpu_prefs_changed_flag & 1) {
uaecptr pc = m68k_getpc();
}
}
-void exception2_fake (uaecptr addr)
-{
- if (regs.halted)
- return;
- write_log (_T("delayed exception2!\n"));
- regs.panic_pc = m68k_getpc ();
- regs.panic_addr = addr;
- regs.panic = 6;
- set_special (SPCFLAG_BRK);
- m68k_setpc_normal (0xf80000);
-#ifdef JIT
- set_special (SPCFLAG_END_COMPILE);
-#endif
- fill_prefetch ();
-}
-
void cpureset (void)
{
/* RESET hasn't increased PC yet, 1 word offset */
uae_u32 addr = m68k_areg (regs, reg);
if (addr < 0x80000)
addr += 0xf80000;
- write_log (_T("reset/jmp (ax) combination emulated -> %x\n"), addr);
+ write_log (_T("reset/jmp (ax) combination at %08x emulated -> %x\n"), pc, addr);
m68k_setpc_normal (addr - 2);
return;
}
void *open_tablet (HWND hwnd)
{
static int initialized;
- LOGCONTEXT lc;
+ LOGCONTEXT lc = { 0 };
AXIS tx = { 0 }, ty = { 0 }, tz = { 0 };
AXIS pres = { 0 };
int xm, ym, zm;
return 0;
}
name[0] = 0;
- pWTInfoW (WTI_DEVICES, DVC_NAME, name);
+ if (!pWTInfoW (WTI_DEVICES, DVC_NAME, name)) {
+ write_log(_T("Tablet: WTInfo(DVC_NAME) returned failure\n"));
+ FreeModule(wintab);
+ wintab = NULL;
+ return 0;
+ }
+ if (name[0] == 0) {
+ write_log(_T("Tablet: WTInfo(DVC_NAME) returned NULL name\n"));
+ FreeModule(wintab);
+ wintab = NULL;
+ return 0;
+ }
axmax = aymax = azmax = -1;
tilt = pWTInfoW (WTI_DEVICES, DVC_ORIENTATION, ori);
if (tilt) {
set_expamem_z3_hack_override(false);
z3offset = 0;
- if ((changed_prefs.z3autoconfig_start == 0x10000000 || changed_prefs.z3autoconfig_start == 0x40000000) && !changed_prefs.force_0x10000000_z3 && cpuboard_memorytype(&changed_prefs) != BOARD_MEMORY_BLIZZARD) {
+ if ((changed_prefs.z3autoconfig_start == 0x10000000 || changed_prefs.z3autoconfig_start == 0x40000000) && !changed_prefs.force_0x10000000_z3 && cpuboard_memorytype(&changed_prefs) != BOARD_MEMORY_BLIZZARD_12xx) {
if (1 && natmem_size > 0x40000000 && natmem_size - 0x40000000 >= (totalsize - 0x10000000 - ((changed_prefs.z3chipmem_size + align) & ~align)) && changed_prefs.z3chipmem_size <= 512 * 1024 * 1024) {
changed_prefs.z3autoconfig_start = currprefs.z3autoconfig_start = 0x40000000;
z3offset += 0x40000000 - 0x10000000 - ((changed_prefs.z3chipmem_size + align) & ~align);
} else if (!_tcscmp(shmids[shmid].name, _T("ramsey_high"))) {
shmaddr = natmem_offset + 0x08000000;
got = TRUE;
+ } else if (!_tcscmp(shmids[shmid].name, _T("blizzard_40"))) {
+ shmaddr = natmem_offset + 0x40000000;
+ got = TRUE;
+ } else if (!_tcscmp(shmids[shmid].name, _T("blizzard_48"))) {
+ shmaddr = natmem_offset + 0x48000000;
+ got = TRUE;
+ } else if (!_tcscmp(shmids[shmid].name, _T("blizzard_68"))) {
+ shmaddr = natmem_offset + 0x68000000;
+ got = TRUE;
+ } else if (!_tcscmp(shmids[shmid].name, _T("blizzard_70"))) {
+ shmaddr = natmem_offset + 0x70000000;
+ got = TRUE;
} else if (!_tcscmp(shmids[shmid].name, _T("cyberstorm"))) {
shmaddr = natmem_offset + 0x0c000000;
got = TRUE;
#define IDS_QS_MODEL_A3000 1010
#define IDS_QS_MODEL_A4000 1011
#define IDS_QS_MODEL_A4000T 1012
-#define IDS_QS_MODEL_CDTVCR 1013
#define IDC_RESOLUTION 1021
#define IDC_SERIAL 1022
#define IDC_REFRESHRATE 1022
#define IDC_DBG_AMEM 1745
#define IDC_CS_DIPAGNUS 1745
#define IDC_DBG_SP_VBR 1746
+#define IDC_CS_CDTVRAMEXP2 1746
+#define IDC_CS_CDTVCR 1746
#define IDC_DBG_MMISC 1747
#define IDC_DBG_PC 1748
#define IDC_DBG_PREFETCH 1749
CONTROL "DF0: ID Hardware",IDC_CS_DF0IDHW,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,264,102,125,11
CONTROL "CD32 NVRAM",IDC_CS_CD32NVRAM,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,264,116,125,11
CONTROL "CDTV SRAM Expansion",IDC_CS_CDTVRAMEXP,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,264,129,125,11
- CONTROL "PCMCIA",IDC_CS_PCMCIA,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,264,143,125,11
- CONTROL "C00000 is Fast RAM",IDC_CS_SLOWISFAST,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,264,157,125,11
- CONTROL "A1000 Agnus (8361/8367)",IDC_CS_DIPAGNUS,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,264,171,125,11
+ CONTROL "PCMCIA",IDC_CS_PCMCIA,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,264,156,125,11
+ CONTROL "C00000 is Fast RAM",IDC_CS_SLOWISFAST,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,264,170,125,11
+ CONTROL "A1000 Agnus (8361/8367)",IDC_CS_DIPAGNUS,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,264,184,125,11
GROUPBOX "Internal SCSI Hardware",IDC_STATIC,0,201,393,45
CONTROL "A3000 WD33C93 SCSI",IDC_CS_DMAC,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,34,216,121,11
CONTROL "CDTV WD33C93 SCSI",IDC_CS_CDTVSCSI,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,34,229,121,11
EDITTEXT IDC_CS_AGNUSREV,311,260,45,13,ES_AUTOHSCROLL
EDITTEXT IDC_CS_DENISEREV,311,275,45,13,ES_AUTOHSCROLL
CONTROL "Z3 Autoconfig",IDC_CS_Z3AUTOCONFIG,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,127,184,104,11
+ CONTROL "CDTV-CR",IDC_CS_CDTVCR,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,264,143,123,11
END
IDD_AVIOUTPUT DIALOGEX 0, 0, 396, 260
STRINGTABLE
BEGIN
- IDS_QS_MODELS "A500\nA500+\nA600\nA1000\nA1200\nA3000\nA4000\nCD32\nCDTV\nCDTV-CR\nArcadia Multi Select system\nExpanded WinUAE example configuration"
+ IDS_QS_MODELS "A500\nA500+\nA600\nA1000\nA1200\nA3000\nA4000\nCD32\nCDTV\nArcadia Multi Select system\nExpanded WinUAE example configuration"
IDS_QS_MODEL_A500 "1.3 ROM, OCS, 512 KB Chip + 512 KB Slow RAM (most common)\nThis configuration is capable of running most games and demos produced for first-generation hardware. Only few exceptions need a different configuration (e.g. the oldest games tend to be incompatible with this configuration).\n1.3 ROM, ECS Agnus, 512 KB Chip RAM + 512 KB Slow RAM\nLater hardware revision of the A500. Nearly 100% compatible with the previous configuration.\n1.3 ROM, ECS Agnus, 1 MB Chip RAM\nFew newer games and demos require this configuration.\n1.3 ROM, OCS Agnus, 512 KB Chip RAM\nVery old (e.g. pre-1988) games and demos may require this configuration.\n1.2 ROM, OCS Agnus, 512 KB Chip RAM\nAs available for the A1000, and installed on the first A500 and A2000 series. Some very old programs only work correctly with this configuration. Note: This system ROM version can only boot from floppy disk (no hard disk boot support).\n1.2 ROM, OCS Agnus, 512 KB Chip RAM + 512 KB Slow RAM\nThis configuration adds expansion memory to the first A500 produced. Try this if your game does not work with newer configurations, but works with the previous one. It could add some features to the game, including faster loading times. Note: This system ROM version can only boot from floppy disk (no hard disk boot support)."
IDS_QS_MODEL_A500P "Basic non-expanded configuration\nThe A500+ adds an ECS Agnus chip, 1 MB of Chip RAM and a 2.0 ROM to the A500. Many A500 games and demos don't work properly on an A500+.\n2 MB Chip RAM expanded configuration\n\n4 MB Fast RAM expanded configuration\n"
IDS_QS_MODEL_A600 "Basic non-expanded configuration\nThe A600 is smaller than the A500+ and has an updated 2.0 ROM.\n2 MB Chip RAM expanded configuration\n\n4 MB Fast RAM expanded configuration\n"
IDS_QS_MODEL_A1000 "512 KB Chip RAM\nThe A1000 was the first model produced, with a configuration equivalent to that of an A500 with OCS chipset. You normally don't need to use this configuration, unless you are nostalgic and would like to hear the short A1000 boot tune\n""ICS"" Denise without EHB support\nVery first A1000 models had Denise without EHB capability.\n256 KB Chip RAM\n Unexpanded A1000. All later A1000 models were sold with a 256 KB RAM expansion built-in."
IDS_QS_MODEL_A1200 "Basic non-expanded configuration\nUse this configuration to run most AGA demos and games\n4 MB Fast RAM expanded configuration\nSome newer AGA games and demos need an expanded A1200 to run."
IDS_QS_MODEL_CD32 "CD32\nThe CD32 was one the first 32-bit consoles on the market. It is basically an A1200 with a built-in CD-ROM drive. Insert your CD32 or CDTV CD-ROM into a free CD-ROM drive before starting the emulation.\nCD32 with Full Motion Video cartridge\n"
- IDS_QS_MODEL_CDTV "CDTV\nThe CDTV was the first model with a built-in CD-ROM drive. Looking like a black CD player, it featured a configuration equivalent to that of an A500 with 1 MB RAM and an ECS chipset.\nFloppy drive and 64KB SRAM card expanded CDTV\n"
+ IDS_QS_MODEL_CDTV "CDTV\nThe CDTV was the first model with a built-in CD-ROM drive. Looking like a black CD player, it featured a configuration equivalent to that of an A500 with 1 MB RAM and an ECS chipset.\nFloppy drive and 64KB SRAM card expanded CDTV\n\nCDTV-CR\n"
END
STRINGTABLE
IDS_QS_MODEL_A3000 "1.4 ROM, 2MB Chip + 8MB Fast\n\n2.04 ROM, 2MB Chip + 8MB Fast\n\n3.1 ROM, 2MB Chip + 8MB Fast\n"
IDS_QS_MODEL_A4000 "68030, 3.1 ROM, 2MB Chip + 8MB Fast\n\n68040, 3.1 ROM, 2MB Chip + 8MB Fast\n"
IDS_QS_MODEL_A4000T "A4000T (test)\nA4000T"
- IDS_QS_MODEL_CDTVCR "CDTV-CR\nCDTV-CR"
END
STRINGTABLE
prevpc = (uae_u8*)ppc;
}
m68k_setpc ((uaecptr)p);
- exception2_fake (opc);
+ exception2(opc, er->ExceptionInformation[0] == 0, 4, regs.s ? 4 : 0);
lRet = EXCEPTION_CONTINUE_EXECUTION;
}
}
#define LANG_DLL_FULL_VERSION_MATCH 1
#if WINUAEPUBLICBETA
-#define WINUAEBETA _T("20")
+#define WINUAEBETA _T("21")
#else
#define WINUAEBETA _T("")
#endif
-#define WINUAEDATE MAKEBD(2014, 10, 12)
+#define WINUAEDATE MAKEBD(2014, 10, 19)
//#define WINUAEEXTRA _T("AmiKit Preview")
//#define WINUAEEXTRA _T("Amiga Forever Edition")
}
static int quickstart_model = 0, quickstart_conf = 0, quickstart_compa = 1;
+static int quickstart_model_confstore[16];
static int quickstart_floppy = 1, quickstart_cd = 0, quickstart_ntsc = 0;
static int quickstart_cdtype = 0;
static TCHAR quickstart_cddrive[16];
static int msi_z3fast[] = { 0, 5, 6, 7, 8, 9, 10, 11, 12, 13, 19, 14, 20, 15, 21, 18, 22, 23 };
static int msi_z3chip[] = { 0, 9, 10, 11, 12, 13, 19, 14, 20, 15 };
static int msi_gfx[] = { 0, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 };
+static int msi_cpuboard[] = { 0, 5, 6, 7, 8, 9, 10, 11, 12, 13 };
#define MIN_CHIP_MEM 0
#define MAX_CHIP_MEM 6
#define MAX_MBL_MEM 7
#define MAX_MBH_MEM 8
#define MIN_CB_MEM 0
-#define MAX_CB_MEM 8
+#define MAX_CB_MEM_Z2 4
+#define MAX_CB_MEM_128M 8
+#define MAX_CB_MEM_256M 9
#define MIN_M68K_PRIORITY 1
#define MAX_M68K_PRIORITY 16
17, -1, -1, // A4000T
18, -1, 19, -1, -1, // CD32
20, 21, 22, -1, 6, 32, -1, -1, // CDTV
- 9, 10, -1, 107, -1, -1, // CDTV-CR
+ 9, 10, -1, 107, 108, -1, -1, // CDTV-CR
49, 50, 75, 51, 76, 77, -1, 5, 4, -1, -2, // ARCADIA
53, 54, 55, 56, -1, -1, // A590/A2091
{ 0, }, //{ 1, IDS_QS_MODEL_A4000T }, // "Amiga 4000T"
{ 3, IDS_QS_MODEL_CD32 }, // "CD32"
{ 4, IDS_QS_MODEL_CDTV }, // "CDTV"
- { 4, IDS_QS_MODEL_CDTVCR }, // "CDTVCR"
{ 4, IDS_QS_MODEL_ARCADIA }, // "Arcadia"
{ 1, IDS_QS_MODEL_UAE }, // "Expanded UAE example configuration"
{ -1 }
workprefs.nr_floppies = quickstart_floppy;
quickstart_ok = built_in_prefs (&workprefs, quickstart_model, quickstart_conf, quickstart_compa, romcheck);
workprefs.ntscmode = quickstart_ntsc != 0;
- quickstart_cd = workprefs.floppyslots[1].dfxtype == DRV_NONE && (quickstart_model == 8 || quickstart_model == 9 || quickstart_model == 10);
+ quickstart_cd = workprefs.floppyslots[1].dfxtype == DRV_NONE && (quickstart_model == 8 || quickstart_model == 9);
enable_for_quickstart (hDlg);
addfloppytype (hDlg, 0);
addfloppytype (hDlg, 1);
if (firsttime == 0 && workprefs.start_gui) {
regqueryint (NULL, _T("QuickStartModel"), &quickstart_model);
regqueryint (NULL, _T("QuickStartConfiguration"), &quickstart_conf);
+ quickstart_model_confstore[quickstart_model] = quickstart_conf;
regqueryint (NULL, _T("QuickStartCompatibility"), &quickstart_compa);
regqueryint (NULL, _T("QuickStartFloppies"), &quickstart_floppy);
regqueryint (NULL, _T("QuickStartCDType"), &quickstart_cdtype);
}
if (i != quickstart_model) {
quickstart_model = i;
+ quickstart_conf = quickstart_model_confstore[quickstart_model];
init_quickstartdlg (hDlg);
if (quickstart)
load_quickstart (hDlg, 1);
val = SendDlgItemMessage (hDlg, IDC_QUICKSTART_CONFIGURATION, CB_GETCURSEL, 0, 0L);
if (val != CB_ERR && val != quickstart_conf) {
quickstart_conf = val;
+ quickstart_model_confstore[quickstart_model] = quickstart_conf;
init_quickstartdlg (hDlg);
if (quickstart)
load_quickstart (hDlg, 1);
CheckDlgButton (hDlg, IDC_CS_CD32C2P, workprefs.cs_cd32c2p);
CheckDlgButton (hDlg, IDC_CS_CD32NVRAM, workprefs.cs_cd32nvram);
CheckDlgButton (hDlg, IDC_CS_CDTVCD, workprefs.cs_cdtvcd);
+ CheckDlgButton (hDlg, IDC_CS_CDTVCR, workprefs.cs_cdtvcr);
CheckDlgButton (hDlg, IDC_CS_CDTVRAM, workprefs.cs_cdtvram);
CheckDlgButton (hDlg, IDC_CS_CDTVRAMEXP, workprefs.cs_cdtvcard);
CheckDlgButton (hDlg, IDC_CS_A1000RAM, workprefs.cs_a1000ram);
workprefs.cs_cd32c2p = ischecked (hDlg, IDC_CS_CD32C2P);
workprefs.cs_cd32nvram = ischecked (hDlg, IDC_CS_CD32NVRAM);
workprefs.cs_cdtvcd = ischecked (hDlg, IDC_CS_CDTVCD);
+ workprefs.cs_cdtvcr = ischecked (hDlg, IDC_CS_CDTVCR);
workprefs.cs_cdtvram = ischecked (hDlg, IDC_CS_CDTVRAM);
workprefs.cs_cdtvcard = ischecked (hDlg, IDC_CS_CDTVRAMEXP) ? 64 : 0;
workprefs.cs_a1000ram = ischecked (hDlg, IDC_CS_A1000RAM);
ew (hDlg, IDC_CS_CD32NVRAM, e);
ew (hDlg, IDC_CS_CD32C2P, e);
ew (hDlg, IDC_CS_CDTVCD, e);
+ ew (hDlg, IDC_CS_CDTVCR, e);
ew (hDlg, IDC_CS_CDTVRAM, e);
ew (hDlg, IDC_CS_CDTVRAMEXP, e);
ew (hDlg, IDC_CS_RESETWARNING, e);
SetDlgItemText (hDlg, IDC_MAX32RAM, tmp);
}
+static void setcpuboardmemsize(HWND hDlg)
+{
+ int maxmem = cpuboard_maxmemory(&workprefs);
+ if (workprefs.cpuboardmem1_size > maxmem) {
+ workprefs.cpuboardmem1_size = maxmem;
+ }
+ if (maxmem <= 8 * 1024 * 1024)
+ SendDlgItemMessage (hDlg, IDC_CPUBOARDMEM, TBM_SETRANGE, TRUE, MAKELONG (MIN_CB_MEM, MAX_CB_MEM_Z2));
+ else if (maxmem <= 128 * 1024 * 1024)
+ SendDlgItemMessage (hDlg, IDC_CPUBOARDMEM, TBM_SETRANGE, TRUE, MAKELONG (MIN_CB_MEM, MAX_CB_MEM_128M));
+ else
+ SendDlgItemMessage (hDlg, IDC_CPUBOARDMEM, TBM_SETRANGE, TRUE, MAKELONG (MIN_CB_MEM, MAX_CB_MEM_256M));
+
+ int mem_size = 0;
+ switch (workprefs.cpuboardmem1_size) {
+ case 0x00000000: mem_size = 0; break;
+ case 0x00100000: mem_size = 1; break;
+ case 0x00200000: mem_size = 2; break;
+ case 0x00400000: mem_size = 3; break;
+ case 0x00800000: mem_size = 4; break;
+ case 0x01000000: mem_size = 5; break;
+ case 0x02000000: mem_size = 6; break;
+ case 0x04000000: mem_size = 7; break;
+ case 0x08000000: mem_size = 8; break;
+ case 0x10000000: mem_size = 9; break;
+ }
+ SendDlgItemMessage (hDlg, IDC_CPUBOARDMEM, TBM_SETPOS, TRUE, mem_size);
+ SetDlgItemText (hDlg, IDC_CPUBOARDRAM, memsize_names[msi_cpuboard[mem_size]]);
+ SendDlgItemMessage (hDlg, IDC_CPUBOARD_TYPE, CB_SETCURSEL, workprefs.cpuboard_type, 0);
+}
static int manybits (int v, int mask)
{
SendDlgItemMessage (hDlg, IDC_CHIPMEM, TBM_SETPOS, TRUE, mem_size);
SetDlgItemText (hDlg, IDC_CHIPRAM, memsize_names[msi_chip[mem_size]]);
+ if (workprefs.cpuboardmem1_size > cpuboard_maxmemory(&workprefs))
+ workprefs.cpuboardmem1_size = cpuboard_maxmemory(&workprefs);
+
if (cpuboard_memorytype(&workprefs) == BOARD_MEMORY_Z2) {
- if (workprefs.cpuboardmem1_size > 8 * 1024 * 1024)
- workprefs.cpuboardmem1_size = 8 * 1024 * 1024;
workprefs.fastmem_size = workprefs.cpuboardmem1_size;
}
SendDlgItemMessage (hDlg, IDC_MBMEM2, TBM_SETPOS, TRUE, mem_size);
SetDlgItemText (hDlg, IDC_MBRAM2, memsize_names[msi_gfx[mem_size]]);
- mem_size = 0;
- switch (workprefs.cpuboardmem1_size) {
- case 0x00000000: mem_size = 0; break;
- case 0x00100000: mem_size = 1; break;
- case 0x00200000: mem_size = 2; break;
- case 0x00400000: mem_size = 3; break;
- case 0x00800000: mem_size = 4; break;
- case 0x01000000: mem_size = 5; break;
- case 0x02000000: mem_size = 6; break;
- case 0x04000000: mem_size = 7; break;
- case 0x08000000: mem_size = 8; break;
- case 0x10000000: mem_size = 9; break;
- }
- SendDlgItemMessage (hDlg, IDC_CPUBOARDMEM, TBM_SETPOS, TRUE, mem_size);
- SetDlgItemText (hDlg, IDC_CPUBOARDRAM, memsize_names[msi_gfx[mem_size]]);
- SendDlgItemMessage (hDlg, IDC_CPUBOARD_TYPE, CB_SETCURSEL, workprefs.cpuboard_type, 0);
-
+ setcpuboardmemsize(hDlg);
setmax32bitram (hDlg);
}
return FALSE;
}
-
static INT_PTR CALLBACK MemoryDlgProc (HWND hDlg, UINT msg, WPARAM wParam, LPARAM lParam)
{
static int recursive = 0;
SendDlgItemMessage (hDlg, IDC_Z3CHIPMEM, TBM_SETRANGE, TRUE, MAKELONG (MIN_Z3_MEM, MAX_Z3_CHIPMEM));
SendDlgItemMessage (hDlg, IDC_MBMEM1, TBM_SETRANGE, TRUE, MAKELONG (MIN_MB_MEM, MAX_MBL_MEM));
SendDlgItemMessage (hDlg, IDC_MBMEM2, TBM_SETRANGE, TRUE, MAKELONG (MIN_MB_MEM, MAX_MBH_MEM));
- SendDlgItemMessage (hDlg, IDC_CPUBOARDMEM, TBM_SETRANGE, TRUE, MAKELONG (MIN_CB_MEM, MAX_CB_MEM));
CheckDlgButton(hDlg, IDC_FASTMEMAUTOCONFIG, workprefs.fastmem_autoconfig);
CheckDlgButton(hDlg, IDC_Z3REALMAPPING, workprefs.jit_direct_compatible_memory);
SendDlgItemMessage (hDlg, IDC_CPUBOARD_TYPE, CB_RESETCONTENT, 0, 0);
SendDlgItemMessage(hDlg, IDC_CPUBOARD_TYPE, CB_ADDSTRING, 0, (LPARAM)_T("Warp Engine"));
SendDlgItemMessage(hDlg, IDC_CPUBOARD_TYPE, CB_ADDSTRING, 0, (LPARAM)_T("Tek Magic"));
SendDlgItemMessage(hDlg, IDC_CPUBOARD_TYPE, CB_ADDSTRING, 0, (LPARAM)_T("A2620/A2630"));
+ setcpuboardmemsize(hDlg);
case WM_USER:
workprefs.fastmem_autoconfig = ischecked (hDlg, IDC_FASTMEMAUTOCONFIG);
workprefs.ppc_mode = 0;
}
built_in_cpuboard_prefs(&workprefs);
+ setcpuboardmemsize(hDlg);
enable_for_memorydlg(hDlg);
}
break;
workprefs.z3chipmem_size = memsizes[msi_z3chip[SendMessage (GetDlgItem (hDlg, IDC_Z3CHIPMEM), TBM_GETPOS, 0, 0)]];
workprefs.mbresmem_low_size = memsizes[msi_gfx[SendMessage (GetDlgItem (hDlg, IDC_MBMEM1), TBM_GETPOS, 0, 0)]];
workprefs.mbresmem_high_size = memsizes[msi_gfx[SendMessage (GetDlgItem (hDlg, IDC_MBMEM2), TBM_GETPOS, 0, 0)]];
- workprefs.cpuboardmem1_size = memsizes[msi_gfx[SendMessage (GetDlgItem (hDlg, IDC_CPUBOARDMEM), TBM_GETPOS, 0, 0)]];
+ workprefs.cpuboardmem1_size = memsizes[msi_cpuboard[SendMessage (GetDlgItem (hDlg, IDC_CPUBOARDMEM), TBM_GETPOS, 0, 0)]];
fix_values_memorydlg ();
values_to_memorydlg (hDlg);
enable_for_memorydlg (hDlg);
- restore only single input target to default.
+Beta 21:
+
+- Moved CDTV-CR under original CDTV Quickstart option.
+- Added 3.44 CDTV-CR extended ROM.
+- CDTV-CR now boots CDTV CDs. CD audio player does not yet work and some games that play CD audio will hang.
+ Also CD reading speed is currently unlimited.
+- Added 256M (max possible) Blizzard accelerator board RAM size support. Works with 1230, 1260 and PPC.
+- CSPPC P5_SELF_RESET bit emulation fixed, M68K can only reset PPC and PPC can only reset M68K if
+ P5_SELF_RESET is not active. (Blizkick reset hang)
+- When switching quickstart modes, extended ROM was not reset if new mode didn't use extended ROM.
+- Switching Quickstart models now remembers previously selected model configuration setting.
+- Disable tablet mode if tablet name query returns error or empty name. WTInfo() with null parameters is
+ supposed to return error if tablet is not connected but it does not seem to be true with all drivers.
+ (Fixes division by zero guru at boot if tablet emulation is emulated)
+- default_xlate() system halt didn't work, broke probably when 1 second boot delay option was added.
+- default_xlate() now also generates bus error if Gary bus error bit is set instead of halting.
+- Include approximate exception startup time in non-cycle exact 68000 emulation modes.
+
Beta 20:
- A2630 rom was not unmapped completely (only first half)
}
}
+bool uae_self_is_ppc(void)
+{
+ if (ppc_state == PPC_STATE_INACTIVE)
+ return false;
+ return impl.in_cpu_thread();
+}
+
void ppc_map_banks(uae_u32 start, uae_u32 size, const TCHAR *name, void *addr, bool remove)
{
if (ppc_state == PPC_STATE_INACTIVE || !impl.map_memory)
return NULL;
}
-#define NEXT_ROM_ID 108
+#define NEXT_ROM_ID 109
static struct romheader romheaders[] = {
{ _T("Freezer Cartridges"), 1 },
ALTROM(21, 1, 2, 131072, ROMTYPE_ODD | ROMTYPE_8BIT, 0x8a54f362,0x03df800f,0x032046fd,0x892f6e7e,0xec08b76d,0x33981e8c)
{ _T("CDTV-CR extended ROM v3.32"), 3, 32, 3, 32, _T("CDTVCR\0"), 262144, 107, 0, 0, ROMTYPE_EXTCDTV, 0, 0, NULL,
0x581a85cf, 0xd6b8d3f2,0x854eba9b,0x2d514579,0x9529e8b3,0x3b85e0b4 },
+ { _T("CDTV-CR extended ROM v3.44"), 3, 44, 3, 44, _T("CDTVCR\0"), 262144, 108, 0, 0, ROMTYPE_EXTCDTV, 0, 0, NULL,
+ 0x0b7bd64f, 0x3b160c5a,0xbe79f10a,0xe6924332,0x8004bb9e,0x3162b648 },
{ _T("A1000 bootstrap ROM"), 0, 0, 0, 0, _T("A1000\0"), 65536, 24, 0, 0, ROMTYPE_KICK, 0, 0, NULL,
0x0b1ad2d0, 0xBA93B8B8,0x5CA0D83A,0x68225CC3,0x3B95050D,0x72D2FDD7 },
projects / francis / winuae.git / commitdiff