cfgfile_write_bool (f, _T("blitter_cycle_exact"), p->blitter_cycle_exact);
cfgfile_write_bool (f, _T("cycle_exact"), p->cpu_cycle_exact && p->blitter_cycle_exact ? 1 : 0);
cfgfile_dwrite_bool (f, _T("fpu_no_unimplemented"), p->fpu_no_unimplemented);
+ cfgfile_dwrite_bool (f, _T("cpu_no_unimplemented"), p->int_no_unimplemented);
cfgfile_write_bool (f, _T("rtg_nocustom"), p->picasso96_nocustom);
cfgfile_write (f, _T("rtg_modes"), _T("0x%x"), p->picasso96_modeflags);
if (cfgfile_yesno (option, value, _T("immediate_blits"), &p->immediate_blits)
|| cfgfile_yesno (option, value, _T("fpu_no_unimplemented"), &p->fpu_no_unimplemented)
+ || cfgfile_yesno (option, value, _T("cpu_no_unimplemented"), &p->int_no_unimplemented)
|| cfgfile_yesno (option, value, _T("cd32cd"), &p->cs_cd32cd)
|| cfgfile_yesno (option, value, _T("cd32c2p"), &p->cs_cd32c2p)
|| cfgfile_yesno (option, value, _T("cd32nvram"), &p->cs_cd32nvram)
p->cpu060_revision = 6;
p->fpu_revision = -1;
p->fpu_no_unimplemented = false;
+ p->int_no_unimplemented = false;
p->m68k_speed = 0;
p->cpu_compatible = 1;
p->address_space_24 = 1;
uaecptr ROM_hardfile_init;
bool uae_boot_rom;
int uae_boot_rom_size; /* size = code size only */
+static bool chipdone;
/* ********************************************************** */
static uae_u8 expamem_lo;
static uae_u16 expamem_hi;
+/* Ugly hack for >2M chip RAM in single pool
+ * We can't add it any later or early boot menu
+ * stops working because it sets kicktag at the end
+ * of chip ram...
+ */
+static void addextrachip (uae_u32 sysbase)
+{
+ if (currprefs.chipmem_size <= 0x00200000)
+ return;
+ if (sysbase & 0x80000001)
+ return;
+ if (!valid_address (sysbase, 1000))
+ return;
+ uae_u32 ml = get_long (sysbase + 322);
+ if (!valid_address (ml, 32))
+ return;
+ uae_u32 next;
+ while ((next = get_long (ml))) {
+ if (!valid_address (ml, 32))
+ return;
+ uae_u32 upper = get_long (ml + 24);
+ uae_u32 lower = get_long (ml + 20);
+ if (lower & ~0xffff) {
+ ml = next;
+ continue;
+ }
+ uae_u16 attr = get_word (ml + 14);
+ if ((attr & 0x8002) != 2) {
+ ml = next;
+ continue;
+ }
+ if (upper >= currprefs.chipmem_size)
+ return;
+ uae_u32 added = currprefs.chipmem_size - upper;
+ uae_u32 first = get_long (ml + 16);
+ put_long (ml + 24, currprefs.chipmem_size); // mh_Upper
+ put_long (ml + 28, get_long (ml + 28) + added); // mh_Free
+ uae_u32 next;
+ while (first) {
+ next = first;
+ first = get_long (next);
+ }
+ uae_u32 bytes = get_long (next + 4);
+ if (next + bytes == 0x00200000) {
+ put_long (next + 4, currprefs.chipmem_size - next);
+ } else {
+ put_long (0x00200000 + 0, 0);
+ put_long (0x00200000 + 4, added);
+ put_long (next, 0x00200000);
+ }
+ return;
+ }
+}
+
+
static uae_u32 REGPARAM3 expamem_lget (uaecptr) REGPARAM;
static uae_u32 REGPARAM3 expamem_wget (uaecptr) REGPARAM;
static uae_u32 REGPARAM3 expamem_bget (uaecptr) REGPARAM;
#ifdef JIT
special_mem |= S_READ;
#endif
+ if (!chipdone) {
+ chipdone = true;
+ addextrachip (get_long (4));
+ }
addr &= 0xFFFF;
b = expamem[addr];
#ifdef EXP_DEBUG
ecard = 0;
cardno = 0;
+ chipdone = false;
if (currprefs.uae_hide)
uae_id = commodore;
mode = SHARED_LOCK;
}
- TRACE((_T("ACTION_LOCK(0x%lx, \"%s\", %d)\n"), lock, bstr (unit, name), mode));
+ TRACE((_T("ACTION_LOCK(0x%08x, \"%s\", %d)\n"), lock, bstr (unit, name), mode));
DUMPLOCK(unit, lock);
a = find_aino (unit, lock, bstr (unit, name), &err);
int aino_created = 0;
int isvirtual = unit->volflags & (MYVOLUMEINFO_ARCHIVE | MYVOLUMEINFO_CDFS);
- TRACE((_T("ACTION_FIND_*(0x%lx,0x%lx,\"%s\",%d,%d)\n"), fh, lock, bstr (unit, name), mode, create));
+ TRACE((_T("ACTION_FIND_*(0x%08x,0x%08x,\"%s\",%d,%d)\n"), fh, lock, bstr (unit, name), mode, create));
TRACE((_T("fh=%x lock=%x name=%x\n"), fh, lock, name));
DUMPLOCK(unit, lock);
put_word (resaddr + 16, RTS);
m68k_areg (regs, 0) = residents;
+
return 1;
}
db(0x00); db(0x00); db(0x00); db(0x10); db(0x00); db(0x00); db(0x00); db(0x00);
- db(0x60); db(0x02); db(0x00); db(0x09); db(0x60); db(0x00); db(0x0b); db(0x4c);
- db(0x00); db(0x00); db(0x08); db(0xe8); db(0x00); db(0x00); db(0x00); db(0xe0);
- db(0x00); db(0x00); db(0x02); db(0xa8); db(0x00); db(0x00); db(0x00); db(0x24);
- db(0x00); db(0x00); db(0x03); db(0xb6); db(0x00); db(0x00); db(0x00); db(0x00);
- db(0x00); db(0x00); db(0x13); db(0xda); db(0x43); db(0xfa); db(0x18); db(0xe5);
+ db(0x60); db(0x02); db(0x00); db(0x09); db(0x60); db(0x00); db(0x0a); db(0xdc);
+ db(0x00); db(0x00); db(0x08); db(0x78); db(0x00); db(0x00); db(0x00); db(0xe0);
+ db(0x00); db(0x00); db(0x02); db(0x38); db(0x00); db(0x00); db(0x00); db(0x24);
+ db(0x00); db(0x00); db(0x03); db(0x46); db(0x00); db(0x00); db(0x00); db(0x00);
+ db(0x00); db(0x00); db(0x13); db(0x6a); db(0x43); db(0xfa); db(0x18); db(0x75);
db(0x4e); db(0xae); db(0xff); db(0xa0); db(0x20); db(0x40); db(0x20); db(0x28);
db(0x00); db(0x16); db(0x20); db(0x40); db(0x4e); db(0x90); db(0x4e); db(0x75);
db(0x48); db(0xe7); db(0xe0); db(0xe2); db(0x30); db(0x3c); db(0xff); db(0x38);
- db(0x72); db(0x11); db(0x61); db(0x00); db(0x17); db(0xce); db(0x4e); db(0x90);
+ db(0x72); db(0x11); db(0x61); db(0x00); db(0x17); db(0x5e); db(0x4e); db(0x90);
db(0x4a); db(0x80); db(0x67); db(0x4c); db(0x2c); db(0x78); db(0x00); db(0x04);
db(0x0c); db(0x6e); db(0x00); db(0x25); db(0x00); db(0x14); db(0x65); db(0x40);
db(0x70); db(0x14); db(0x24); db(0x00); db(0x72); db(0x01); db(0x4e); db(0xae);
db(0x20); db(0x68); db(0x00); db(0x02); db(0x2f); db(0x08); db(0x4e); db(0x90);
db(0x20); db(0x5f); db(0x58); db(0x8f); db(0x48); db(0xe7); db(0xff); db(0x7e);
db(0x22); db(0x4e); db(0x20); db(0x08); db(0x30); db(0x7c); db(0xff); db(0xb8);
- db(0x4e); db(0xae); db(0xfe); db(0x5c); db(0x61); db(0x00); db(0x13); db(0x1c);
- db(0x61); db(0x00); db(0x16); db(0xe4); db(0x4c); db(0xdf); db(0x7e); db(0xff);
+ db(0x4e); db(0xae); db(0xfe); db(0x5c); db(0x61); db(0x00); db(0x12); db(0xac);
+ db(0x61); db(0x00); db(0x16); db(0x74); db(0x4c); db(0xdf); db(0x7e); db(0xff);
db(0x4e); db(0x75); db(0x00); db(0x00); db(0x08); db(0x00); db(0x00); db(0x02);
db(0x67); db(0x06); db(0x4e); db(0xb9); db(0x00); db(0xf0); db(0x00); db(0x00);
db(0x4e); db(0xf9); db(0x00); db(0xf0); db(0x00); db(0x00); db(0x00); db(0x00);
db(0x48); db(0xe7); db(0xff); db(0xfe); db(0x2c); db(0x78); db(0x00); db(0x04);
- db(0x30); db(0x3c); db(0xff); db(0xec); db(0x61); db(0x00); db(0x17); db(0x24);
- db(0x2a); db(0x50); db(0x43); db(0xfa); db(0x18); db(0x46); db(0x70); db(0x24);
+ db(0x30); db(0x3c); db(0xff); db(0xec); db(0x61); db(0x00); db(0x16); db(0xb4);
+ db(0x2a); db(0x50); db(0x43); db(0xfa); db(0x17); db(0xd6); db(0x70); db(0x24);
db(0x7a); db(0x01); db(0x4e); db(0xae); db(0xfd); db(0xd8); db(0x4a); db(0x80);
- db(0x66); db(0x0c); db(0x43); db(0xfa); db(0x18); db(0x36); db(0x70); db(0x00);
+ db(0x66); db(0x0c); db(0x43); db(0xfa); db(0x17); db(0xc6); db(0x70); db(0x00);
db(0x7a); db(0x00); db(0x4e); db(0xae); db(0xfd); db(0xd8); db(0x28); db(0x40);
db(0x4a); db(0xad); db(0x01); db(0x0c); db(0x67); db(0x00); db(0x00); db(0x5c);
db(0x20); db(0x3c); db(0x00); db(0x00); db(0x02); db(0x34); db(0x22); db(0x3c);
db(0xbc); db(0x6d); db(0x01); db(0x0e); db(0x64); db(0x2c); db(0x2f); db(0x06);
db(0x7e); db(0x01); db(0x4a); db(0x45); db(0x67); db(0x04); db(0x08); db(0xc7);
db(0x00); db(0x02); db(0x2f); db(0x0b); db(0x20); db(0x4b); db(0x61); db(0x00);
- db(0x07); db(0xa0); db(0x26); db(0x5f); db(0x0c); db(0x80); db(0xff); db(0xff);
+ db(0x07); db(0x30); db(0x26); db(0x5f); db(0x0c); db(0x80); db(0xff); db(0xff);
db(0xff); db(0xfe); db(0x67); db(0x08); db(0x48); db(0x46); db(0x52); db(0x46);
db(0x48); db(0x46); db(0x60); db(0xdc); db(0x2c); db(0x1f); db(0x52); db(0x46);
db(0x60); db(0xce); db(0x2c); db(0x78); db(0x00); db(0x04); db(0x22); db(0x4b);
db(0x20); db(0x3c); db(0x00); db(0x00); db(0x02); db(0x34); db(0x4e); db(0xae);
db(0xff); db(0x2e); db(0x2c); db(0x78); db(0x00); db(0x04); db(0x22); db(0x4c);
db(0x4e); db(0xae); db(0xfe); db(0x62); db(0x30); db(0x3c); db(0xff); db(0x80);
- db(0x61); db(0x00); db(0x16); db(0x90); db(0x4e); db(0x90); db(0x4e); db(0xae);
- db(0xff); db(0x88); db(0x41); db(0xee); db(0x01); db(0x42); db(0x20); db(0x50);
- db(0x4a); db(0x90); db(0x67); db(0x54); db(0x22); db(0x28); db(0x00); db(0x14);
- db(0x42); db(0x41); db(0x4a); db(0x81); db(0x66); db(0xf0); db(0x32); db(0x28);
- db(0x00); db(0x0e); db(0x02); db(0x41); db(0x00); db(0x02); db(0x67); db(0xe6);
- db(0x90); db(0xa8); db(0x00); db(0x18); db(0x6b); db(0x3a); db(0x67); db(0x38);
- db(0x42); db(0x78); db(0x01); db(0x40); db(0x22); db(0x28); db(0x00); db(0x18);
- db(0xd1); db(0xa8); db(0x00); db(0x18); db(0xd1); db(0xa8); db(0x00); db(0x1c);
- db(0xd1); db(0xae); db(0x00); db(0x3e); db(0x20); db(0x68); db(0x00); db(0x10);
- db(0x4a); db(0x90); db(0x67); db(0x04); db(0x20); db(0x50); db(0x60); db(0xf8);
- db(0x24); db(0x08); db(0xd4); db(0xa8); db(0x00); db(0x04); db(0xb2); db(0x82);
- db(0x67); db(0x0a); db(0x20); db(0x81); db(0x22); db(0x41); db(0x42); db(0x99);
- db(0x22); db(0x80); db(0x60); db(0x04); db(0xd1); db(0xa8); db(0x00); db(0x04);
- db(0x4e); db(0xae); db(0xff); db(0x82); db(0x30); db(0x3c); db(0xff); db(0x80);
db(0x61); db(0x00); db(0x16); db(0x20); db(0x4e); db(0x90); db(0x20); db(0x49);
db(0x20); db(0x01); db(0x67); db(0x0c); db(0x22); db(0x04); db(0x74); db(0xfb);
db(0x43); db(0xfa); db(0x17); db(0x5e); db(0x4e); db(0xae); db(0xfd); db(0x96);
db(0x23); db(0x4a); db(0x00); db(0x0e); db(0x70); db(0x05); db(0x4e); db(0xae);
db(0xff); db(0x58); db(0x4c); db(0xdf); db(0x07); db(0x03); db(0x4e); db(0x75);
db(0x52); db(0x91); db(0x70); db(0x00); db(0x4e); db(0x75); db(0x48); db(0xe7);
- db(0xc0); db(0xc0); db(0x61); db(0x00); db(0xfc); db(0x7c); db(0x70); db(0x1a);
+ db(0xc0); db(0xc0); db(0x61); db(0x00); db(0xfc); db(0xec); db(0x70); db(0x1a);
db(0x22); db(0x3c); db(0x00); db(0x01); db(0x00); db(0x01); db(0x4e); db(0xae);
db(0xff); db(0x3a); db(0x22); db(0x40); db(0x41); db(0xfa); db(0x15); db(0x02);
db(0x23); db(0x48); db(0x00); db(0x0a); db(0x41); db(0xfa); db(0xfe); db(0xd2);
db(0x61); db(0x00); db(0x0e); db(0x58); db(0x4e); db(0x90); db(0x20); db(0x03);
db(0x16); db(0x29); db(0x00); db(0x4f); db(0x4a); db(0x80); db(0x66); db(0x1a);
db(0x27); db(0x7c); db(0x00); db(0x00); db(0x17); db(0x70); db(0x00); db(0x14);
- db(0x41); db(0xfa); db(0xf6); db(0x2a); db(0x20); db(0x08); db(0xe4); db(0x88);
+ db(0x41); db(0xfa); db(0xf6); db(0x9a); db(0x20); db(0x08); db(0xe4); db(0x88);
db(0x27); db(0x40); db(0x00); db(0x20); db(0x70); db(0xff); db(0x27); db(0x40);
db(0x00); db(0x24); db(0x08); db(0x07); db(0x00); db(0x00); db(0x67); db(0x40);
db(0x0c); db(0x03); db(0x00); db(0x80); db(0x67); db(0x3a); db(0x2c); db(0x78);
db(0x4e); db(0x75); db(0x59); db(0x8f); db(0x48); db(0xe7); db(0xc0); db(0x80);
db(0x30); db(0x3c); db(0xff); db(0x38); db(0x72); db(0x66); db(0x61); db(0x00);
db(0x00); db(0x0a); db(0x4e); db(0x90); db(0x4c); db(0xdf); db(0x01); db(0x03);
- db(0x4e); db(0x75); db(0x41); db(0xfa); db(0xe7); db(0xe0); db(0x02); db(0x80);
+ db(0x4e); db(0x75); db(0x41); db(0xfa); db(0xe8); db(0x50); db(0x02); db(0x80);
db(0x00); db(0x00); db(0xff); db(0xff); db(0xd1); db(0xc0); db(0x4e); db(0x75);
db(0x69); db(0x6e); db(0x70); db(0x75); db(0x74); db(0x2e); db(0x64); db(0x65);
db(0x76); db(0x69); db(0x63); db(0x65); db(0x00); db(0x74); db(0x69); db(0x6d);
genamode (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_LRMW);
genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_LRMW);
if (cpu_level == 5 && curi->size > 0) {
- if (!using_mmu) {
- printf ("\tif ((dsta & %d) && currprefs.cpu_compatible && get_cpu_model () == 68060) {\n", curi->size == 1 ? 1 : 3);
- } else {
- printf ("\tif ((dsta & %d) && currprefs.cpu_compatible) {\n", curi->size == 1 ? 1 : 3);
- }
+ printf ("\tif ((dsta & %d) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {\n", curi->size == 1 ? 1 : 3);
if (curi->dmode == Aipi || curi->dmode == Apdi)
printf ("\t\tm68k_areg (regs, dstreg) %c= %d;\n", curi->dmode == Aipi ? '-' : '+', 1 << curi->size);
sync_m68k_pc_noreset ();
int fpu_model;
int fpu_revision;
bool cpu_compatible;
+ bool int_no_unimplemented;
bool fpu_no_unimplemented;
bool address_space_24;
bool picasso96_nocustom;
struct uae_input_device2 {
uae_u32 buttonmask;
- int states[MAX_INPUT_DEVICE_EVENTS / 2];
+ int states[MAX_INPUT_DEVICE_EVENTS / 2][MAX_INPUT_SUB_EVENT + 1];
};
static struct uae_input_device2 joysticks2[MAX_INPUT_DEVICES];
} else {
if (!checkqualifiers (evt, flags, qualmask, NULL)) {
if (!state && !(flags & ID_FLAG_CANRELEASE)) {
- continue;
+ if (!invert)
+ continue;
} else if (state) {
continue;
}
if (!keyboards || scancode < 0)
return handled;
-// if (!state)
-// process_custom_event (NULL, 0, 0, 0, 0, 0);
-
j = 0;
while (j < MAX_INPUT_DEVICE_EVENTS && na->extra[j] >= 0) {
if (na->extra[j] == scancode) {
} else {
rqualifiers (flags, state ? true : false);
if (!checkqualifiers (evt, flags, qualmask, na->eventid[j])) {
- if (!state && !(flags & ID_FLAG_CANRELEASE))
- continue;
- else if (state)
+ if (!state && !(flags & ID_FLAG_CANRELEASE)) {
+ if (!invert)
+ continue;
+ } else if (state) {
continue;
+ }
}
if (state) {
- *flagsp |= ID_FLAG_CANRELEASE;
+ if (!invert)
+ *flagsp |= ID_FLAG_CANRELEASE;
} else {
- if (!(flags & ID_FLAG_CANRELEASE))
+ if (!(flags & ID_FLAG_CANRELEASE) && !invert)
continue;
*flagsp &= ~ID_FLAG_CANRELEASE;
}
return;
}
v1 = state;
- v2 = id2->states[axis];
+ v2 = id2->states[axis][MAX_INPUT_SUB_EVENT];
+
+ write_log (_T("new=%d old=%d state=%d max=%d\n"), v1, v2, state, max);
+
if (v1 < deadzone && v1 > -deadzone)
v1 = 0;
if (v2 < deadzone && v2 > -deadzone)
v2 = 0;
- if (v1 == v2)
- return;
- if (input_play && state)
- inprec_realtime ();
+ if (input_play && state) {
+ if (v1 != v2)
+ inprec_realtime ();
+ }
if (input_play)
return;
if (!joysticks[joy].enabled) {
- if (v1)
+ if (v1 && v1 != v2)
switchdevice (&joysticks[joy], axis * 2 + (v1 < 0 ? 0 : 1), false);
return;
}
uae_u64 flags = id->flags[ID_AXIS_OFFSET + axis][i];
if (flags & ID_FLAG_INVERT)
state = -state;
- handle_input_event (id->eventid[ID_AXIS_OFFSET + axis][i], state, max, flags & ID_FLAG_AUTOFIRE, true, false);
+ if (state != id2->states[axis][i]) {
+ write_log(_T("-> %d %d\n"), i, state);
+ handle_input_event (id->eventid[ID_AXIS_OFFSET + axis][i], state, max, flags & ID_FLAG_AUTOFIRE, true, false);
+ id2->states[axis][i] = state;
+ }
}
- id2->states[axis] = state;
+ id2->states[axis][MAX_INPUT_SUB_EVENT] = v1;
}
int getjoystickstate (int joy)
{
/* unimplemented opcode? */
if (table->unimpclev > 0 && lvl >= table->unimpclev) {
- if (currprefs.cpu_compatible && currprefs.cpu_model == 68060) {
+ if (currprefs.int_no_unimplemented && currprefs.cpu_model == 68060) {
cpufunctbl[opcode] = op_unimpl_1;
} else {
cpufunctbl[opcode] = op_illg_1;
currprefs.mmu_model = changed_prefs.mmu_model;
currprefs.cpu_compatible = changed_prefs.cpu_compatible;
currprefs.cpu_cycle_exact = changed_prefs.cpu_cycle_exact;
+ currprefs.int_no_unimplemented = changed_prefs.int_no_unimplemented;
+ currprefs.fpu_no_unimplemented = changed_prefs.fpu_no_unimplemented;
currprefs.blitter_cycle_exact = changed_prefs.blitter_cycle_exact;
}
|| currprefs.cpu_model != changed_prefs.cpu_model
|| currprefs.fpu_model != changed_prefs.fpu_model
|| currprefs.mmu_model != changed_prefs.mmu_model
+ || currprefs.int_no_unimplemented != changed_prefs.int_no_unimplemented
+ || currprefs.fpu_no_unimplemented != changed_prefs.fpu_no_unimplemented
|| currprefs.cpu_compatible != changed_prefs.cpu_compatible
|| currprefs.cpu_cycle_exact != changed_prefs.cpu_cycle_exact) {
} else {
write_log (_T(" fake prefetch"));
}
- if (currprefs.cpu_model == 68060) {
- write_log (_T(" no unimplemented integer instructions"));
- }
+ }
+ if (currprefs.int_no_unimplemented && currprefs.cpu_model == 68060) {
+ write_log (_T(" no unimplemented integer instructions"));
+ }
+ if (currprefs.fpu_no_unimplemented && currprefs.fpu_model) {
+ write_log (_T(" no unimplemented floating point instructions"));
}
if (currprefs.address_space_24) {
regs.address_space_mask = 0x00ffffff;
void m68k_divl (uae_u32 opcode, uae_u32 src, uae_u16 extra)
{
- if ((extra & 0x400) && currprefs.cpu_compatible && currprefs.cpu_model == 68060) {
+ if ((extra & 0x400) && currprefs.int_no_unimplemented && currprefs.cpu_model == 68060) {
op_unimpl (opcode);
return;
}
void m68k_mull (uae_u32 opcode, uae_u32 src, uae_u16 extra)
{
- if ((extra & 0x400) && currprefs.cpu_compatible && currprefs.cpu_model == 68060) {
+ if ((extra & 0x400) && currprefs.int_no_unimplemented && currprefs.cpu_model == 68060) {
op_unimpl (opcode);
return;
}
unset_special (SPCFLAG_INT);
return;
}
- if (currprefs.cpu_compatible)
+ if (currprefs.cpu_compatible && currprefs.cpu_model < 68020)
set_special (SPCFLAG_INT);
else
set_special (SPCFLAG_DOINT);
fill_prefetch ();
}
+
void cpureset (void)
{
+ /* RESET hasn't increased PC yet, 1 word offset */
uaecptr pc;
- uaecptr ksboot = 0xf80002 - 2; /* -2 = RESET hasn't increased PC yet */
+ uaecptr ksboot = 0xf80002 - 2;
uae_u16 ins;
+ addrbank *ab;
send_internalevent (INTERNALEVENT_CPURESET);
if ((currprefs.cpu_compatible || currprefs.cpu_cycle_exact) && currprefs.cpu_model <= 68020) {
custom_reset (false, false);
return;
}
- pc = m68k_getpc ();
- if (pc >= 0xa00000) {
- addrbank *b = &get_mem_bank (pc);
- if (b->check (pc, 2 + 2)) {
- /* We have memory, hope for the best.. */
- custom_reset (false, false);
+ pc = m68k_getpc () + 2;
+ ab = &get_mem_bank (pc);
+ if (ab->check (pc, 2)) {
+ write_log (_T("CPU reset PC=%x (%s)..\n"), pc - 2, ab->name);
+ ins = get_word (pc);
+ custom_reset (false, false);
+ // did memory disappear under us?
+ if (ab == &get_mem_bank (pc))
+ return;
+ // it did
+ if ((ins & ~7) == 0x4ed0) {
+ int reg = ins & 7;
+ uae_u32 addr = m68k_areg (regs, reg);
+ if (addr < 0x80000)
+ addr += 0xf80000;
+ write_log (_T("reset/jmp (ax) combination emulated -> %x\n"), addr);
+ m68k_setpc (addr - 2);
return;
}
- write_log (_T("M68K RESET PC=%x, rebooting..\n"), pc);
- custom_reset (false, false);
- m68k_setpc (ksboot);
- return;
- }
- /* panic, RAM is going to disappear under PC */
- ins = get_word (pc + 2);
- if ((ins & ~7) == 0x4ed0) {
- int reg = ins & 7;
- uae_u32 addr = m68k_areg (regs, reg);
- write_log (_T("reset/jmp (ax) combination emulated -> %x\n"), addr);
- custom_reset (false, false);
- if (addr < 0x80000)
- addr += 0xf80000;
- m68k_setpc (addr - 2);
- return;
}
- write_log (_T("M68K RESET PC=%x, rebooting..\n"), pc);
+ // the best we can do, jump directly to ROM entrypoint
+ // (which is probably what program wanted anyway)
+ write_log (_T("CPU Reset PC=%x (%s), invalid memory -> %x.\n"), pc, ab->name, ksboot + 2);
custom_reset (false, false);
m68k_setpc (ksboot);
}
}
static uae_u8 rawkeystate[256];
+static int rawprevkey;
static void handle_rawinput_2 (RAWINPUT *raw)
{
int i, num;
}
}
- if (rawkeystate[scancode] == pressed) {
+ // More complex press/release check because we want to support
+ // keys that never return releases, only pressed but also need
+ // handle normal keys that can repeat.
+
+#if 0
+ if (!pressed)
return;
+#endif
+
+ if (pressed) {
+ // previously pressed key and next press is same key? Repeat. Ignore it.
+ if (scancode == rawprevkey)
+ return;
+ rawprevkey = scancode;
+ if (rawkeystate[scancode] == 2) {
+ // Got press for key that is already pressed.
+ // Must be ignored. It is repeat.
+ rawkeystate[scancode] = 1;
+ return;
+ }
+ rawkeystate[scancode] = 1;
+ } else {
+ rawprevkey = -1;
+ // release without press: ignore
+ if (rawkeystate [scancode] == 0)
+ return;
+ rawkeystate[scancode] = 0;
+ // Got release, if following press is key that
+ // is currently pressed: ignore it, it is repeat.
+ // Mark all currently pressed keys.
+ for (int i = 0; i < sizeof (rawkeystate); i++) {
+ if (rawkeystate[i] == 1)
+ rawkeystate[i] = 2;
+ }
}
- rawkeystate[scancode] = pressed;
+
if (istest) {
if (pressed && (scancode == DIK_F12))
return;
}
}
memset (rawkeystate, 0, sizeof rawkeystate);
+ rawprevkey = -1;
}
#define IDC_FPU3 1227
#define IDC_FPU_UNIMPLEMENTED 1228
#define IDC_SOUNDSETTINGS 1229
+#define IDC_CPU_UNIMPLEMENTED 1229
#define IDC_8BIT 1230
#define IDC_16BIT 1231
#define IDC_11KHZ 1232
EDITTEXT IDC_MBRAM2,240,171,40,12,ES_CENTER | ES_READONLY
END
-IDD_CPU DIALOGEX 0, 0, 396, 270
+IDD_CPU DIALOGEX 0, 0, 396, 283
STYLE DS_LOCALEDIT | DS_SETFONT | DS_3DLOOK | DS_CONTROL | WS_CHILD
FONT 8, "MS Sans Serif", 0, 0, 0x0
BEGIN
- GROUPBOX "CPU",IDC_STATIC,1,1,109,160,BS_LEFT
+ GROUPBOX "CPU",IDC_STATIC,1,1,129,175,BS_LEFT
CONTROL "68000",IDC_CPU0,"Button",BS_AUTORADIOBUTTON | WS_GROUP | WS_TABSTOP,8,15,63,10
CONTROL "68010",IDC_CPU1,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,8,29,63,10
CONTROL "68020",IDC_CPU2,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,8,42,63,10
CONTROL "68030",IDC_CPU3,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,8,56,63,10
CONTROL "68040",IDC_CPU4,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,8,70,63,10
CONTROL "68060",IDC_CPU5,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,8,84,63,10
- CONTROL "24-bit addressing",IDC_COMPATIBLE24,"Button",BS_AUTOCHECKBOX | BS_LEFT | WS_GROUP | WS_TABSTOP,8,101,97,12
- CONTROL "More compatible [] Emulate 68000's prefetch registers. More compatible but slower.",IDC_COMPATIBLE,
- "Button",BS_AUTOCHECKBOX | BS_LEFT | WS_GROUP | WS_TABSTOP,8,115,97,11
+ CONTROL "24-bit addressing",IDC_COMPATIBLE24,"Button",BS_AUTOCHECKBOX | BS_LEFT | WS_GROUP | WS_TABSTOP,8,101,119,12
+ CONTROL "More compatible [] 68000: emulate prefetch. 68020+: emulate prefetch partially. More compatible but slower.",IDC_COMPATIBLE,
+ "Button",BS_AUTOCHECKBOX | BS_LEFT | WS_GROUP | WS_TABSTOP,8,115,118,11
CONTROL "JIT [] Enable just-in-time CPU emulator. Significantly increases the speed of the CPU emulation. Requires 68020 or higher CPU.",IDC_JITENABLE,
- "Button",BS_AUTOCHECKBOX | WS_TABSTOP,8,128,97,11
+ "Button",BS_AUTOCHECKBOX | WS_TABSTOP,8,128,120,11
CONTROL "MMU [] 68030, 68040 and 68060 MMU emulation. Not compatible with JIT.",IDC_MMUENABLE,
- "Button",BS_AUTOCHECKBOX | WS_TABSTOP,8,142,96,11
- GROUPBOX "CPU Emulation Speed",IDC_STATIC,120,3,274,96
- CONTROL "Fastest possible",IDC_CS_HOST,"Button",BS_AUTORADIOBUTTON | BS_LEFT | WS_GROUP | WS_TABSTOP,125,18,195,10
+ "Button",BS_AUTOCHECKBOX | WS_TABSTOP,8,142,120,11
+ GROUPBOX "CPU Emulation Speed",IDC_STATIC,136,3,258,111
+ CONTROL "Fastest possible",IDC_CS_HOST,"Button",BS_AUTORADIOBUTTON | BS_LEFT | WS_GROUP | WS_TABSTOP,143,24,195,10
CONTROL "Approximate A500/A1200 or cycle-exact",IDC_CS_68000,
- "Button",BS_AUTORADIOBUTTON | BS_LEFT | WS_TABSTOP,125,32,195,10
- CONTROL "Slider1",IDC_SPEED,"msctls_trackbar32",TBS_AUTOTICKS | TBS_TOP | WS_TABSTOP,126,50,192,20
- RTEXT "CPU Speed",IDC_STATIC,125,78,55,9,SS_CENTERIMAGE
- EDITTEXT IDC_CPUTEXT,188,77,30,12,ES_CENTER | ES_READONLY
- RTEXT "CPU Idle",IDC_STATIC,223,78,62,9
- CONTROL "",IDC_CPUIDLE,"msctls_trackbar32",TBS_AUTOTICKS | TBS_TOP | WS_TABSTOP,292,73,69,21
- GROUPBOX "Cycle-exact CPU Emulation Speed",IDC_STATIC,120,105,274,55
- RTEXT "CPU Frequency",IDC_STATIC,123,129,67,10,SS_CENTERIMAGE
- COMBOBOX IDC_CPU_FREQUENCY,199,128,46,75,CBS_DROPDOWNLIST | WS_VSCROLL | WS_TABSTOP
- EDITTEXT IDC_CPU_FREQUENCY2,252,127,70,15
- GROUPBOX "FPU",IDC_STATIC,1,167,109,99,BS_LEFT
- CONTROL "None",IDC_FPU0,"Button",BS_AUTORADIOBUTTON | WS_GROUP | WS_TABSTOP,8,182,87,10
- CONTROL "68881",IDC_FPU1,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,8,196,87,10
- CONTROL "68882",IDC_FPU2,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,8,209,87,10
- CONTROL "CPU internal",IDC_FPU3,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,8,223,93,10
+ "Button",BS_AUTORADIOBUTTON | BS_LEFT | WS_TABSTOP,143,38,195,10
+ CONTROL "Slider1",IDC_SPEED,"msctls_trackbar32",TBS_AUTOTICKS | TBS_TOP | WS_TABSTOP,142,62,192,20
+ RTEXT "CPU Speed",IDC_STATIC,141,90,55,9,SS_CENTERIMAGE
+ EDITTEXT IDC_CPUTEXT,204,89,30,12,ES_CENTER | ES_READONLY
+ RTEXT "CPU Idle",IDC_STATIC,239,90,62,9
+ CONTROL "",IDC_CPUIDLE,"msctls_trackbar32",TBS_AUTOTICKS | TBS_TOP | WS_TABSTOP,308,85,69,21
+ GROUPBOX "Cycle-exact CPU Emulation Speed",IDC_STATIC,136,121,258,55
+ RTEXT "CPU Frequency",IDC_STATIC,139,145,67,10,SS_CENTERIMAGE
+ COMBOBOX IDC_CPU_FREQUENCY,215,144,46,75,CBS_DROPDOWNLIST | WS_VSCROLL | WS_TABSTOP
+ EDITTEXT IDC_CPU_FREQUENCY2,268,143,70,15
+ GROUPBOX "FPU",IDC_STATIC,1,181,129,99,BS_LEFT
+ CONTROL "None",IDC_FPU0,"Button",BS_AUTORADIOBUTTON | WS_GROUP | WS_TABSTOP,8,195,87,10
+ CONTROL "68881",IDC_FPU1,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,8,209,87,10
+ CONTROL "68882",IDC_FPU2,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,8,222,87,10
+ CONTROL "CPU internal",IDC_FPU3,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,8,236,93,10
CONTROL "More compatible [] More compatible but slower FPU emulation.",IDC_COMPATIBLE_FPU,
- "Button",BS_AUTOCHECKBOX | BS_LEFT | WS_GROUP | WS_TABSTOP,8,239,94,10
- GROUPBOX "Advanced JIT Settings",IDC_STATIC,120,167,274,99
- RTEXT "Cache size:",IDC_STATIC,127,187,66,10,SS_CENTERIMAGE
- CONTROL "Slider1",IDC_CACHE,"msctls_trackbar32",TBS_AUTOTICKS | TBS_TOP | WS_TABSTOP,196,181,115,20
- EDITTEXT IDC_CACHETEXT,315,186,30,12,ES_CENTER | ES_READONLY
- CONTROL "Hard flush",IDC_HARDFLUSH,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,130,214,84,11
- CONTROL "Constant jump",IDC_CONSTJUMP,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,130,228,84,11
- CONTROL "FPU support",IDC_JITFPU,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,130,242,84,11
- CONTROL "No flags",IDC_NOFLAGS,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,227,214,68,11
- CONTROL "Direct",IDC_TRUST0,"Button",BS_AUTORADIOBUTTON | WS_GROUP | WS_TABSTOP,299,214,72,10
- CONTROL "Indirect",IDC_TRUST1,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,299,228,72,10
- CONTROL "Unimplemented emu [] Emulate 68040/060 FPU unimplemented instructions",IDC_FPU_UNIMPLEMENTED,
- "Button",BS_AUTOCHECKBOX | BS_LEFT | WS_GROUP | WS_TABSTOP,8,252,96,10
+ "Button",BS_AUTOCHECKBOX | BS_LEFT | WS_GROUP | WS_TABSTOP,8,252,117,10
+ GROUPBOX "Advanced JIT Settings",IDC_STATIC,136,181,258,99
+ RTEXT "Cache size:",IDC_STATIC,143,200,66,10,SS_CENTERIMAGE
+ CONTROL "Slider1",IDC_CACHE,"msctls_trackbar32",TBS_AUTOTICKS | TBS_TOP | WS_TABSTOP,212,194,115,20
+ EDITTEXT IDC_CACHETEXT,331,199,30,12,ES_CENTER | ES_READONLY
+ CONTROL "Hard flush",IDC_HARDFLUSH,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,146,227,84,11
+ CONTROL "Constant jump",IDC_CONSTJUMP,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,146,241,84,11
+ CONTROL "FPU support",IDC_JITFPU,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,146,255,84,11
+ CONTROL "No flags",IDC_NOFLAGS,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,243,227,68,11
+ CONTROL "Direct",IDC_TRUST0,"Button",BS_AUTORADIOBUTTON | WS_GROUP | WS_TABSTOP,315,227,72,10
+ CONTROL "Indirect",IDC_TRUST1,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,315,241,72,10
+ CONTROL "Unimplemented FPU emu [] Emulate FPU unimplemented instructions",IDC_FPU_UNIMPLEMENTED,
+ "Button",BS_AUTOCHECKBOX | BS_LEFT | WS_GROUP | WS_TABSTOP,8,265,116,10
+ CONTROL "Unimplemented CPU emu [] Emulate 68060 unimplemented integer instructions",IDC_CPU_UNIMPLEMENTED,
+ "Button",BS_AUTOCHECKBOX | BS_LEFT | WS_GROUP | WS_TABSTOP,8,156,118,10
END
IDD_FLOPPY DIALOGEX 0, 0, 396, 261
IDD_CPU, DIALOG
BEGIN
+ BOTTOMMARGIN, 282
END
IDD_FLOPPY, DIALOG
IDS_KICKSTART "ROM"
IDS_DISK "Disk swapper"
IDS_DISPLAY "Display"
- IDS_HARDDISK "Hard drives"
+ IDS_HARDDISK "CD & Hard drives"
IDS_FLOPPY "Floppy drives"
IDS_ABOUT "About"
IDS_LOADSAVE "Configurations"
#define LANG_DLL 1
#if WINUAEPUBLICBETA
-#define WINUAEBETA _T("1")
+#define WINUAEBETA _T("2")
#else
#define WINUAEBETA _T("")
#endif
-#define WINUAEDATE MAKEBD(2013, 6, 3)
+#define WINUAEDATE MAKEBD(2013, 6, 12)
#define WINUAEEXTRA _T("")
//#define WINUAEEXTRA _T("AmiKit Preview")
//#define WINUAEEXTRA _T("Amiga Forever Edition")
ew (hDlg, IDC_COMPATIBLE, !workprefs.cpu_cycle_exact);
ew (hDlg, IDC_COMPATIBLE_FPU, workprefs.fpu_model > 0);
ew (hDlg, IDC_FPU_UNIMPLEMENTED, workprefs.fpu_model);
+ ew (hDlg, IDC_CPU_UNIMPLEMENTED, workprefs.cpu_model == 68060);
#if 0
ew (hDlg, IDC_CPU_MULTIPLIER, workprefs.cpu_cycle_exact);
#endif
CheckDlgButton (hDlg, IDC_COMPATIBLE24, workprefs.address_space_24);
CheckDlgButton (hDlg, IDC_COMPATIBLE_FPU, workprefs.fpu_strict);
CheckDlgButton (hDlg, IDC_FPU_UNIMPLEMENTED, !workprefs.fpu_no_unimplemented);
+ CheckDlgButton (hDlg, IDC_CPU_UNIMPLEMENTED, !workprefs.int_no_unimplemented);
SendDlgItemMessage (hDlg, IDC_CPUIDLE, TBM_SETPOS, TRUE, workprefs.cpu_idle == 0 ? 0 : 12 - workprefs.cpu_idle / 15);
cpu = (workprefs.cpu_model - 68000) / 10;
if (cpu >= 5)
workprefs.cpu_compatible = workprefs.cpu_cycle_exact | (ischecked (hDlg, IDC_COMPATIBLE) ? 1 : 0);
workprefs.fpu_strict = ischecked (hDlg, IDC_COMPATIBLE_FPU) ? 1 : 0;
workprefs.fpu_no_unimplemented = ischecked (hDlg, IDC_FPU_UNIMPLEMENTED) ? 0 : 1;
+ workprefs.int_no_unimplemented = ischecked (hDlg, IDC_CPU_UNIMPLEMENTED) ? 0 : 1;
workprefs.address_space_24 = ischecked (hDlg, IDC_COMPATIBLE24) ? 1 : 0;
workprefs.m68k_speed = ischecked (hDlg, IDC_CS_HOST) ? -1 : 0;
workprefs.m68k_speed_throttle = SendMessage (GetDlgItem (hDlg, IDC_SPEED), TBM_GETPOS, 0, 0) * 100;
- restore only single input target to default.
+Beta 2:
+
+- Moved >2M Chip RAM merge earlier in boot process. Previous was too late and it broke
+ early boot menu. (It sets reset proof resident positioned at the end of chip ram and
+ if chip ram is not available early enough, exec assumes resident is invalid and
+ ignores it). Now nearly complete unfragmented Chip RAM is available, even if booting
+ with Chip RAM only configuration.
+- Do not filter all keyboard presses without matching releases, only filter repeats.
+ (Which isn't that simple because press and repeating press are identical events)
+- Inverted keyboard releases (=press) required matching release before next press
+ event was accepted. (This update wasn't really needed but maybe in future it will
+ be more useful)
+- Added separate 68060 unimplemented integer emulation checkbox. More compatible
+ should only enable/disable prefetch emulation. (approximate/partial or 68000 exact)
+- 68060 MOVEP was not marked as unimplemented.
+- Non-prefetch CPU mode now fully checks if memory disappears after reset by
+ checking memory "bank" pointers instead of using hardcoded addresses. Program
+ doing software reset by executing RESET + JMP (An) now always works. (If opcode
+ is something else or PC points to non-existing memory for some reason, it assumes
+ program attempted normal software reset and jumps to start of ROM code). Makes
+ aros arosbootstrap softkick more reliable under emulation.
+- Tree view "Hard drives" -> "CD & Hard drives"
+- Delay 68020+ interrupt detection by one instruction unless cycle exact is enabled.
+ (For example Skeleton Krew CD32 first enables interrupt and then updates interrupt
+ vector. Game code even guarantees request is active while enabling interrupts..)
+- 68040 MMU PTEST and 68060 MMU PLPA instructions were shown incorrectly by debugger.
+ (Read was shown as write and vice versa. Emulation was working fine)
+
+Beta 1:
+
- KS 1.3 OFS hardfile fix. Apparently 1.3 L:FastFileSystem does not support OFS.
Use ROM built-in FS if OFS partition and hardfile FileSys path is empty. (2.6.0)
- Added emulation of unimplemented FPU instruction exceptions.
0000 1110 11ss sSSS:200:?????:?????:13: CAS.L #1,s[!Dreg,Areg,Immd,PC8r,PC16]
0000 1110 1111 1100:250:?????:?????:10: CAS2.L #2
-0000 rrr1 00dd dDDD:000:-----:-----:12: MVPMR.W d[Areg-Ad16],Dr
-0000 rrr1 01dd dDDD:000:-----:-----:12: MVPMR.L d[Areg-Ad16],Dr
-0000 rrr1 10dd dDDD:000:-----:-----:12: MVPRM.W Dr,d[Areg-Ad16]
-0000 rrr1 11dd dDDD:000:-----:-----:12: MVPRM.L Dr,d[Areg-Ad16]
+0000 rrr1 00dd dDDD:050:-----:-----:12: MVPMR.W d[Areg-Ad16],Dr
+0000 rrr1 01dd dDDD:050:-----:-----:12: MVPMR.L d[Areg-Ad16],Dr
+0000 rrr1 10dd dDDD:050:-----:-----:12: MVPRM.W Dr,d[Areg-Ad16]
+0000 rrr1 11dd dDDD:050:-----:-----:12: MVPRM.L Dr,d[Areg-Ad16]
0000 rrr1 00ss sSSS:000:--Z--:-----:11: BTST Dr,s[!Areg]
0000 rrr1 01ss sSSS:000:--Z--:-----:13: BCHG Dr,s[!Areg,Immd]
0000 rrr1 10ss sSSS:000:--Z--:-----:13: BCLR Dr,s[!Areg,Immd]
1111 0101 0001 0rrr:402:-----:-----:00: PFLUSHAN Ara
1111 0101 0001 1rrr:402:-----:-----:00: PFLUSHA Ara
% 68040 only
-1111 0101 0100 1rrr:452:-----:-----:00: PTESTR Ara
-1111 0101 0110 1rrr:452:-----:-----:00: PTESTW Ara
+1111 0101 0100 1rrr:452:-----:-----:00: PTESTW Ara
+1111 0101 0110 1rrr:452:-----:-----:00: PTESTR Ara
% destination register number is encoded in the following word
1111 0110 0010 0rrr:400:-----:-----:12: MOVE16 ArP,AxP
% 68060
1111 1000 0000 0000:502:?????:?????:10: LPSTOP #1
-1111 0101 1000 1rrr:502:-----:-----:00: PLPAR Ara
-1111 0101 1100 1rrr:502:-----:-----:00: PLPAW Ara
+1111 0101 1000 1rrr:502:-----:-----:00: PLPAW Ara
+1111 0101 1100 1rrr:502:-----:-----:00: PLPAR Ara