dr->cf_reg = 0xffff;
}
+void record_rom_access(uaecptr ptr, uae_u32 v, int size, bool rw)
+{
+ dma_record_init();
+ if (!dma_record_data)
+ return;
+ struct dma_rec *dr = &dma_record_data[dma_record_cycle];
+ dr->miscaddr = ptr;
+ dr->miscval = v;
+ dr->ciarw = rw;
+ dr->miscsize = size;
+}
+
void record_cia_access(int r, int mask, uae_u16 value, bool rw, int phase)
{
dma_record_init();
_stprintf(l5, _T(" %u "), ph - 1);
}
}
+ } else if (dr->miscsize) {
+ _stprintf(l5, _T("ROM%c%c %08X"), dr->ciarw ? 'W' : 'R', dr->miscsize == 1 ? 'B' : (dr->miscsize == 2 ? 'W' : 'L'), dr->miscaddr);
}
}
if (l6) {
bool ciarw;
int ciaphase;
uae_u16 ciavalue;
+ uaecptr miscaddr;
+ uae_u32 miscval;
+ int miscsize;
bool end;
bool cs, hs, vs;
};
extern void record_dma_clear(void);
extern bool record_dma_check(void);
extern void record_cia_access(int r, int mask, uae_u16 value, bool rw, int phase);
+extern void record_rom_access(uaecptr, uae_u32 value, int size, bool rw);
extern void record_dma_ipl(void);
extern void record_dma_ipl_sample(void);
extern void debug_mark_refreshed(uaecptr);
a1000_handle_kickstart (1);
}
-static void REGPARAM3 kickmem_lput (uaecptr, uae_u32) REGPARAM;
-static void REGPARAM3 kickmem_wput (uaecptr, uae_u32) REGPARAM;
-static void REGPARAM3 kickmem_bput (uaecptr, uae_u32) REGPARAM;
+static void REGPARAM3 kickmem_lput(uaecptr, uae_u32) REGPARAM;
+static void REGPARAM3 kickmem_wput(uaecptr, uae_u32) REGPARAM;
+static void REGPARAM3 kickmem_bput(uaecptr, uae_u32) REGPARAM;
+static uae_u32 REGPARAM3 kickmem_lget(uaecptr) REGPARAM;
+static uae_u32 REGPARAM3 kickmem_wget(uaecptr) REGPARAM;
+static uae_u32 REGPARAM3 kickmem_bget(uaecptr) REGPARAM;
-MEMORY_BGET(kickmem);
-MEMORY_WGET(kickmem);
-MEMORY_LGET(kickmem);
MEMORY_CHECK(kickmem);
MEMORY_XLATE(kickmem);
+static uae_u32 REGPARAM2 kickmem_lget(uaecptr addr)
+{
+ addr &= kickmem_bank.mask;
+ uae_u32 m = do_get_mem_long((uae_u32*)(kickmem_bank.baseaddr + addr));
+#ifdef DEBUGGER
+ if (debug_dma) {
+ record_rom_access(kickmem_bank.start + addr, m, 4, false);
+ }
+#endif
+ return m;
+}
+static uae_u32 REGPARAM2 kickmem_wget(uaecptr addr)
+{
+ addr &= kickmem_bank.mask;
+ uae_u16 m = do_get_mem_word((uae_u16*)(kickmem_bank.baseaddr + addr));
+#ifdef DEBUGGER
+ if (debug_dma) {
+ record_rom_access(kickmem_bank.start + addr, m, 2, false);
+ }
+#endif
+ return m;
+}
+static uae_u32 REGPARAM2 kickmem_bget(uaecptr addr)
+{
+ addr &= kickmem_bank.mask;
+ uae_u8 m = kickmem_bank.baseaddr[addr];
+#ifdef DEBUGGER
+ if (debug_dma) {
+ record_rom_access(kickmem_bank.start + addr, m, 1, false);
+ }
+#endif
+ return m;
+}
+
static void REGPARAM2 kickmem_lput (uaecptr addr, uae_u32 b)
{
uae_u32 *m;
+#ifdef DEBUGGER
+ if (debug_dma) {
+ record_rom_access(kickmem_bank.start + addr, b, 4, true);
+ }
+#endif
if (currprefs.rom_readwrite && rom_write_enabled) {
addr &= kickmem_bank.mask;
m = (uae_u32 *)(kickmem_bank.baseaddr + addr);
static void REGPARAM2 kickmem_wput (uaecptr addr, uae_u32 b)
{
uae_u16 *m;
+#ifdef DEBUGGER
+ if (debug_dma) {
+ record_rom_access(kickmem_bank.start + addr, b, 2, true);
+ }
+#endif
if (currprefs.rom_readwrite && rom_write_enabled) {
addr &= kickmem_bank.mask;
m = (uae_u16 *)(kickmem_bank.baseaddr + addr);
static void REGPARAM2 kickmem_bput (uaecptr addr, uae_u32 b)
{
+#ifdef DEBUGGER
+ if (debug_dma) {
+ record_rom_access(kickmem_bank.start + addr, b, 1, true);
+ }
+#endif
if (currprefs.rom_readwrite && rom_write_enabled) {
addr &= kickmem_bank.mask;
kickmem_bank.baseaddr[addr] = b;
{
if (!(ab->flags & ABFLAG_DIRECTACCESS))
return;
+ if (currprefs.cpu_memory_cycle_exact && currprefs.cpu_model < 68020) {
+ return;
+ }
ab->baseaddr_direct_r = ab->baseaddr;
if (!(ab->flags & ABFLAG_ROM))
ab->baseaddr_direct_w = ab->baseaddr;