uae_int_requested |= 2;
}
-static void dmac_start_dma (void)
+void scsi_dmac_start_dma (void)
{
#if A3000_DEBUG > 0 || A2091_DEBUG > 0
write_log (_T("DMAC DMA started, ADDR=%08X, LEN=%08X words\n"), dmac_acr, dmac_wtc);
#endif
dmac_dma = 1;
}
-static void dmac_stop_dma (void)
+void scsi_dmac_stop_dma (void)
{
dmac_dma = 0;
dmac_istr &= ~ISTR_E_INT;
break;
case 0xe0:
if (dmac_dma <= 0)
- dmac_start_dma ();
+ scsi_dmac_start_dma ();
break;
case 0xe2:
- dmac_stop_dma ();
+ scsi_dmac_stop_dma ();
break;
case 0xe4:
dmac_cint ();
break;
case 0xe0:
if (dmac_dma <= 0)
- dmac_start_dma ();
+ scsi_dmac_start_dma ();
break;
case 0xe2:
- dmac_stop_dma ();
+ scsi_dmac_stop_dma ();
break;
case 0xe4:
dmac_cint ();
break;
case 0x12:
if (dmac_dma <= 0)
- dmac_start_dma ();
+ scsi_dmac_start_dma ();
break;
case 0x16:
if (dmac_dma) {
/* ISTR */
break;
case 0x3e:
- dmac_stop_dma ();
+ scsi_dmac_stop_dma ();
break;
}
}
break;
case 0x12:
if (dmac_dma <= 0)
- dmac_start_dma ();
+ scsi_dmac_start_dma ();
v = 0;
break;
case 0x1a:
break;
case 0x3e:
if (dmac_dma) {
- dmac_stop_dma ();
+ scsi_dmac_stop_dma ();
dmac_istr |= ISTR_FE_FLG;
}
v = 0;
return 0;
}
-static void init_scsi (void)
+void init_scsi (void)
{
if (!scsi_thread_running) {
scsi_thread_running = 1;
int add_scsi_hd (int ch, struct hd_hardfiledata *hfd, struct uaedev_config_info *ci, int scsi_level)
{
+ init_scsi ();
freescsi (scsis[ch]);
scsis[ch] = NULL;
if (!hfd) {
int add_scsi_cd (int ch, int unitnum)
{
+ init_scsi ();
device_func_init (0);
freescsi (scsis[ch]);
scsis[ch] = scsi_alloc_cd (ch, unitnum, false);
int add_scsi_tape (int ch, const TCHAR *tape_directory, bool readonly)
{
+ init_scsi ();
freescsi (scsis[ch]);
scsis[ch] = scsi_alloc_tape (ch, tape_directory, readonly);
return scsis[ch] ? 1 : 0;
int a2091_add_scsi_unit (int ch, struct uaedev_config_info *ci)
{
- init_scsi ();
if (ci->type == UAEDEV_CD)
return add_scsi_cd (ch, ci->device_emu_unit);
else if (ci->type == UAEDEV_TAPE)
{
int i;
if (currprefs.cpu_model > 68020 || currprefs.cachesize || currprefs.m68k_speed != 0) {
- uae_u8 *p = (uae_u8*)extendedkickmemory;
+ uae_u8 *p = extendedkickmem_bank.baseaddr;
for (i = 0; i < 524288 - sizeof (patchdata); i++) {
if (!memcmp (p + i, patchdata, sizeof(patchdata))) {
protect_roms (false);
void REGPARAM2 chipmem_lput_actionreplay1 (uaecptr addr, uae_u32 l)
{
uae_u32 *m;
- addr -= chipmem_start & chipmem_mask;
- addr &= chipmem_mask;
+ addr -= chipmem_start_addr & chipmem_bank.mask;
+ addr &= chipmem_bank.mask;
if (addr == 0x60 && !is_ar_pc_in_rom())
action_replay_chipwrite ();
- m = (uae_u32 *)(chipmemory + addr);
+ m = (uae_u32 *)(chipmem_bank.baseaddr + addr);
do_put_mem_long (m, l);
}
void REGPARAM2 chipmem_wput_actionreplay1 (uaecptr addr, uae_u32 w)
{
uae_u16 *m;
- addr -= chipmem_start & chipmem_mask;
- addr &= chipmem_mask;
+ addr -= chipmem_start_addr & chipmem_bank.mask;
+ addr &= chipmem_bank.mask;
if (addr == 0x60 && !is_ar_pc_in_rom())
action_replay_chipwrite ();
- m = (uae_u16 *)(chipmemory + addr);
+ m = (uae_u16 *)(chipmem_bank.baseaddr + addr);
do_put_mem_word (m, w);
}
void REGPARAM2 chipmem_bput_actionreplay1 (uaecptr addr, uae_u32 b)
{
- addr -= chipmem_start & chipmem_mask;
- addr &= chipmem_mask;
+ addr -= chipmem_start_addr & chipmem_bank.mask;
+ addr &= chipmem_bank.mask;
if (addr >= 0x60 && addr <= 0x63 && !is_ar_pc_in_rom())
action_replay_chipwrite();
- chipmemory[addr] = b;
+ chipmem_bank.baseaddr[addr] = b;
}
void REGPARAM2 chipmem_lput_actionreplay23 (uaecptr addr, uae_u32 l)
{
uae_u32 *m;
- addr -= chipmem_start & chipmem_mask;
- addr &= chipmem_mask;
- m = (uae_u32 *)(chipmemory + addr);
+ addr -= chipmem_start_addr & chipmem_bank.mask;
+ addr &= chipmem_bank.mask;
+ m = (uae_u32 *)(chipmem_bank.baseaddr + addr);
do_put_mem_long (m, l);
if (addr == 8 && action_replay_flag == ACTION_REPLAY_WAITRESET)
action_replay_chipwrite();
{
uae_u16 *m;
- addr -= chipmem_start & chipmem_mask;
- addr &= chipmem_mask;
- m = (uae_u16 *)(chipmemory + addr);
+ addr -= chipmem_start_addr & chipmem_bank.mask;
+ addr &= chipmem_bank.mask;
+ m = (uae_u16 *)(chipmem_bank.baseaddr + addr);
do_put_mem_word (m, w);
if (addr == 8 && action_replay_flag == ACTION_REPLAY_WAITRESET)
action_replay_chipwrite();
hrtmon_flag = ACTION_REPLAY_ACTIVE;
set_special (SPCFLAG_ACTION_REPLAY);
if (hrtmon_zeropage)
- memcpy (hrtmon_zeropage, chipmemory, 1024);
+ memcpy (hrtmon_zeropage, chipmem_bank.baseaddr, 1024);
if (hrtmon_custom)
memcpy (hrtmon_custom, ar_custom, 2 * 256);
for (i = 0; i < 16; i++) {
static void action_replay_patch (void)
{
int off1,off2;
- uae_u8 *kickmem = kickmemory;
+ uae_u8 *kickmem = kickmem_bank.baseaddr;
if (armodel != 3 || !kickmem || !armemory_rom)
return;
}
if (off1 == 524288 - sizeof (ar3patch1) || off2 == ar_rom_file_size - sizeof (ar3patch2))
return;
- armemory_rom[off2 + 0] = (uae_u8)((off1 + kickmem_start + 2) >> 24);
- armemory_rom[off2 + 1] = (uae_u8)((off1 + kickmem_start + 2) >> 16);
- armemory_rom[off2 + 2] = (uae_u8)((off1 + kickmem_start + 2) >> 8);
- armemory_rom[off2 + 3] = (uae_u8)((off1 + kickmem_start + 2) >> 0);
+ armemory_rom[off2 + 0] = (uae_u8)((off1 + kickmem_start_addr + 2) >> 24);
+ armemory_rom[off2 + 1] = (uae_u8)((off1 + kickmem_start_addr + 2) >> 16);
+ armemory_rom[off2 + 2] = (uae_u8)((off1 + kickmem_start_addr + 2) >> 8);
+ armemory_rom[off2 + 3] = (uae_u8)((off1 + kickmem_start_addr + 2) >> 0);
write_log (_T("AR ROM patched for KS2.0+ (%x)\n"), off2);
}
#if 0
static node pos, matchpos, avail, *position, *parent, *prev;
-static int remainder, matchlen;
+static int remainderlh, matchlen;
static unsigned char *level, *childcount;
static unsigned long dicsiz; /* t.okamoto */
static unsigned short max_hash_val;
static int matchlen;
static unsigned int matchpos;
static unsigned int pos;
-static unsigned int remainder;
+static unsigned int remainderlh;
#if 0
/* ------------------------------------------------------------------------ */
n = fread_crc(&text[(unsigned)(txtsiz - dicsiz)],
(unsigned)dicsiz, infile);
- remainder += n;
+ remainderlh += n;
encoded_origsize += n;
pos -= dicsiz;
static void get_next()
{
- remainder--;
+ remainderlh--;
if (++pos >= txtsiz - maxmatch) {
update();
#ifdef DEBUG
encode_set.encode_start();
memset(&text[0], ' ', (long)TXTSIZ);
- remainder = fread_crc(&text[dicsiz], txtsiz-dicsiz, infile);
- encoded_origsize = remainder;
+ remainderlh = fread_crc(&text[dicsiz], txtsiz-dicsiz, infile);
+ encoded_origsize = remainderlh;
matchlen = THRESHOLD - 1;
pos = dicsiz;
- if (matchlen > remainder) matchlen = remainder;
+ if (matchlen > remainderlh) matchlen = remainderlh;
hval = ((((text[dicsiz] << 5) ^ text[dicsiz + 1]) << 5)
^ text[dicsiz + 2]) & (unsigned)(HSHSIZ - 1);
insert();
- while (remainder > 0 && ! unpackable) {
+ while (remainderlh > 0 && ! unpackable) {
lastmatchlen = matchlen; lastmatchoffset = pos - matchpos - 1;
--matchlen;
get_next(); match_insert();
- if (matchlen > remainder) matchlen = remainder;
+ if (matchlen > remainderlh) matchlen = remainderlh;
if (matchlen > lastmatchlen || lastmatchlen < THRESHOLD) {
encode_set.output(text[pos - 1], 0);
#ifdef DEBUG
get_next();
matchlen = THRESHOLD - 1;
match_insert();
- if (matchlen > remainder) matchlen = remainder;
+ if (matchlen > remainderlh) matchlen = remainderlh;
}
}
encode_set.encode_end();
static uae_u32 REGPARAM2 getchipmemsize (TrapContext *context)
{
- m68k_dreg (regs, 1) = allocated_z3chipmem;
- m68k_areg (regs, 1) = z3chipmem_start;
- return allocated_chipmem;
+ m68k_dreg (regs, 1) = z3chipmem_bank.allocated;
+ m68k_areg (regs, 1) = z3chipmem_bank.start;
+ return chipmem_bank.allocated;
}
static uae_u32 REGPARAM2 uae_puts (TrapContext *context)
{
if (!(dmac_cntr & CNTR_PDMD)) { // non-scsi dma
write_comm_pipe_u32 (&requests, 0x0100, 1);
+ } else {
+ scsi_dmac_start_dma ();
+ }
+}
+static void dmac_stop_dma (void)
+{
+ if (!(dmac_cntr & CNTR_PDMD)) { // non-scsi dma
+ ;
+ } else {
+ scsi_dmac_stop_dma ();
}
}
break;
case 0xe2:
case 0xe3:
- dmac_dma = 0;
+ if (dmac_dma) {
+ dmac_dma = 0;
+ dmac_stop_dma ();
+ }
dma_finished = 0;
break;
case 0xe4:
#ifdef ROMHACK2
-extern uae_u8 *extendedkickmemory, *cardmemory;
static void romhack (void)
{
struct zfile *z;
cdtv_battram_reset ();
open_unit ();
gui_flicker_led (LED_CD, 0, -1);
+ if (currprefs.cs_cdtvscsi)
+ init_scsi ();
}
void cdtv_check_banks (void)
static const TCHAR *rtgtype[] = {
_T("ZorroII"), _T("ZorroIII"),
_T("PicassoII"), _T("PicassoII+"),
- _T("Piccolo"), _T("PiccoloSD64_Z2"), _T("PiccoloSD64_Z3"),
+ _T("Piccolo_Z2"), _T("Piccolo_Z3"), _T("PiccoloSD64_Z2"), _T("PiccoloSD64_Z3"),
_T("PiccoloSD64_Z2"), _T("PiccoloSD64_Z3"),
_T("Spectrum28/24_Z2"), _T("Spectrum28/24_Z3"),
_T("PicassoIV_Z2"), _T("PicassoIV_Z3"),
cia_lget, cia_wget, cia_bget,
cia_lput, cia_wput, cia_bput,
default_xlate, default_check, NULL, _T("CIA"),
- cia_lgeti, cia_wgeti, ABFLAG_IO
+ cia_lgeti, cia_wgeti, ABFLAG_IO, 0x3f00
};
// Gayle or Fat Gary does not enable CIA /CS lines if both CIAs are selected
cia_hsync += ((MAXVPOS_PAL * MAXHPOS_PAL * 50 * 256) / (maxhpos * (currprefs.cs_ciaatod == 2 ? 60 : 50)));
}
#endif
- } else if (currprefs.cs_ciaatod == 0 && onvsync) {
+ } else if (currprefs.cs_ciaatod == 0 && vpos == (currprefs.ntscmode ? VSYNC_ENDLINE_NTSC : VSYNC_ENDLINE_PAL)) {
CIA_vsync_posthandler (ciavsyncs);
}
extern int volatile uaenet_int_requested;
extern int volatile uaenet_vsync_requested;
if (uaenet_int_requested || (uaenet_vsync_requested && vpos == 10)) {
- INTREQ (0x8000 | 0x2000);
+ INTREQ (0x8000 | 0x0008);
}
}
custom_lget, custom_wget, custom_bget,
custom_lput, custom_wput, custom_bput,
default_xlate, default_check, NULL, _T("Custom chipset"),
- custom_lgeti, custom_wgeti, ABFLAG_IO
+ custom_lgeti, custom_wgeti, ABFLAG_IO, 0x1ff
};
static uae_u32 REGPARAM2 custom_wgeti (uaecptr addr)
static uae_u32 lastaddr (void)
{
if (currprefs.z3fastmem2_size)
- return z3fastmem2_start + currprefs.z3fastmem2_size;
+ return z3fastmem2_bank.start + currprefs.z3fastmem2_size;
if (currprefs.z3fastmem_size)
- return z3fastmem_start + currprefs.z3fastmem_size;
+ return z3fastmem_bank.start + currprefs.z3fastmem_size;
if (currprefs.z3chipmem_size)
- return z3chipmem_start + currprefs.z3chipmem_size;
+ return z3chipmem_bank.start + currprefs.z3chipmem_size;
if (currprefs.mbresmem_high_size)
- return a3000hmem_start + currprefs.mbresmem_high_size;
+ return a3000hmem_bank.start + currprefs.mbresmem_high_size;
if (currprefs.mbresmem_low_size)
- return a3000lmem_start + currprefs.mbresmem_low_size;
+ return a3000lmem_bank.start + currprefs.mbresmem_low_size;
if (currprefs.bogomem_size)
- return bogomem_start + currprefs.bogomem_size;
+ return bogomem_bank.start + currprefs.bogomem_size;
if (currprefs.fastmem_size)
- return fastmem_start + currprefs.fastmem_size;
+ return fastmem_bank.start + currprefs.fastmem_size;
return currprefs.chipmem_size;
}
prevx = prev;
sizex = size;
size = currprefs.z3fastmem_size;
- prev = z3fastmem_start;
+ prev = z3fastmem_bank.start;
if (addr == prev + size) {
*next = prevx + sizex;
return prevx;
prevx = prev;
sizex = size;
size = currprefs.z3chipmem_size;
- prev = z3chipmem_start;
+ prev = z3chipmem_bank.start;
if (addr == prev + size) {
*next = prevx + sizex;
return prevx;
sizex = size;
prevx = prev;
size = currprefs.mbresmem_high_size;
- prev = a3000hmem_start;
+ prev = a3000hmem_bank.start;
if (addr == prev + size) {
*next = prevx + sizex;
return prevx;
prevx = prev;
sizex = size;
size = currprefs.mbresmem_low_size;
- prev = a3000lmem_start;
+ prev = a3000lmem_bank.start;
if (addr == prev + size) {
*next = prevx + sizex;
return prevx;
sizex = size;
prevx = prev;
size = currprefs.bogomem_size;
- prev = bogomem_start;
+ prev = bogomem_bank.start;
if (addr == prev + size) {
*next = prevx + sizex;
return prevx;
sizex = size;
prevx = prev;
size = currprefs.fastmem_size;
- prev = fastmem_start;
+ prev = fastmem_bank.start;
if (addr == prev + size) {
*next = prevx + sizex;
return prevx;
sr = _T("COP ");
else if (dr->type == DMARECORD_BLITTER)
sr = _T("BLT ");
+ else if (dr->type == DMARECORD_BLITTER_LINE)
+ sr = _T("BLL ");
else if (dr->type == DMARECORD_REFRESH)
sr = _T("RFS ");
else if (dr->type == DMARECORD_AUDIO)
addr = end - 1;
}
if (currprefs.rtgmem_size)
- memset (illghdebug + (p96ram_start >> 16), 3, currprefs.rtgmem_size >> 16);
+ memset (illghdebug + (gfxmem_bank.start >> 16), 3, currprefs.rtgmem_size >> 16);
i = 0;
while (custd[i].name) {
}
}
-static int debug_mem_off (uaecptr addr)
+static int debug_mem_off (uaecptr *addrp)
{
- return munge24 (addr) >> 16;
+ uaecptr addr = *addrp;
+ int offset = munge24 (addr) >> 16;
+ addr &= debug_mem_banks[offset]->mask;
+ *addrp = addr;
+ return offset;
}
struct smc_item {
static uae_u32 REGPARAM2 mmu_lget (uaecptr addr)
{
- int off = debug_mem_off (addr);
+ int off = debug_mem_off (&addr);
uae_u32 v = 0;
if (!mmu_hit (addr, 4, 0, &v))
v = debug_mem_banks[off]->lget (addr);
}
static uae_u32 REGPARAM2 mmu_wget (uaecptr addr)
{
- int off = debug_mem_off (addr);
+ int off = debug_mem_off (&addr);
uae_u32 v = 0;
if (!mmu_hit (addr, 2, 0, &v))
v = debug_mem_banks[off]->wget (addr);
}
static uae_u32 REGPARAM2 mmu_bget (uaecptr addr)
{
- int off = debug_mem_off (addr);
+ int off = debug_mem_off (&addr);
uae_u32 v = 0;
if (!mmu_hit(addr, 1, 0, &v))
v = debug_mem_banks[off]->bget (addr);
}
static void REGPARAM2 mmu_lput (uaecptr addr, uae_u32 v)
{
- int off = debug_mem_off (addr);
+ int off = debug_mem_off (&addr);
if (!mmu_hit (addr, 4, 1, &v))
debug_mem_banks[off]->lput (addr, v);
}
static void REGPARAM2 mmu_wput (uaecptr addr, uae_u32 v)
{
- int off = debug_mem_off (addr);
+ int off = debug_mem_off (&addr);
if (!mmu_hit (addr, 2, 1, &v))
debug_mem_banks[off]->wput (addr, v);
}
static void REGPARAM2 mmu_bput (uaecptr addr, uae_u32 v)
{
- int off = debug_mem_off (addr);
+ int off = debug_mem_off (&addr);
if (!mmu_hit (addr, 1, 1, &v))
debug_mem_banks[off]->bput (addr, v);
}
static uae_u32 REGPARAM2 debug_lget (uaecptr addr)
{
- int off = debug_mem_off (addr);
+ uae_u32 off = debug_mem_off (&addr);
uae_u32 v;
v = debug_mem_banks[off]->lget (addr);
memwatch_func (addr, 1, 4, &v);
}
static uae_u32 REGPARAM2 mmu_lgeti (uaecptr addr)
{
- int off = debug_mem_off (addr);
+ int off = debug_mem_off (&addr);
uae_u32 v = 0;
if (!mmu_hit (addr, 4, 4, &v))
v = debug_mem_banks[off]->lgeti (addr);
}
static uae_u32 REGPARAM2 mmu_wgeti (uaecptr addr)
{
- int off = debug_mem_off (addr);
+ int off = debug_mem_off (&addr);
uae_u32 v = 0;
if (!mmu_hit (addr, 2, 4, &v))
v = debug_mem_banks[off]->wgeti (addr);
static uae_u32 REGPARAM2 debug_wget (uaecptr addr)
{
- int off = debug_mem_off (addr);
+ int off = debug_mem_off (&addr);
uae_u32 v;
v = debug_mem_banks[off]->wget (addr);
memwatch_func (addr, 1, 2, &v);
}
static uae_u32 REGPARAM2 debug_bget (uaecptr addr)
{
- int off = debug_mem_off (addr);
+ int off = debug_mem_off (&addr);
uae_u32 v;
v = debug_mem_banks[off]->bget (addr);
memwatch_func (addr, 1, 1, &v);
}
static uae_u32 REGPARAM2 debug_lgeti (uaecptr addr)
{
- int off = debug_mem_off (addr);
+ int off = debug_mem_off (&addr);
uae_u32 v;
v = debug_mem_banks[off]->lgeti (addr);
memwatch_func (addr, 4, 4, &v);
}
static uae_u32 REGPARAM2 debug_wgeti (uaecptr addr)
{
- int off = debug_mem_off (addr);
+ int off = debug_mem_off (&addr);
uae_u32 v;
v = debug_mem_banks[off]->wgeti (addr);
memwatch_func (addr, 4, 2, &v);
}
static void REGPARAM2 debug_lput (uaecptr addr, uae_u32 v)
{
- int off = debug_mem_off (addr);
+ int off = debug_mem_off (&addr);
if (memwatch_func (addr, 2, 4, &v))
debug_mem_banks[off]->lput (addr, v);
}
static void REGPARAM2 debug_wput (uaecptr addr, uae_u32 v)
{
- int off = debug_mem_off (addr);
+ int off = debug_mem_off (&addr);
if (memwatch_func (addr, 2, 2, &v))
debug_mem_banks[off]->wput (addr, v);
}
static void REGPARAM2 debug_bput (uaecptr addr, uae_u32 v)
{
- int off = debug_mem_off (addr);
+ int off = debug_mem_off (&addr);
if (memwatch_func (addr, 2, 1, &v))
debug_mem_banks[off]->bput (addr, v);
}
if (!memwatch_enabled)
return v;
if (!currprefs.z3chipmem_size)
- addr &= chipmem_mask;
- memwatch_func (addr & chipmem_mask, 2, 2, &v);
+ addr &= chipmem_bank.mask;
+ memwatch_func (addr & chipmem_bank.mask, 2, 2, &v);
return v;
}
uae_u16 debug_wgetpeekdma (uaecptr addr, uae_u32 v)
if (!memwatch_enabled)
return v;
if (!currprefs.z3chipmem_size)
- addr &= chipmem_mask;
+ addr &= chipmem_bank.mask;
memwatch_func (addr, 1, 2, &vv);
return vv;
}
struct membank_store
{
addrbank *addr;
- addrbank store;
+ addrbank newbank;
+ int banknr;
};
static struct membank_store *membank_stores;
+static int membank_total;
+#define MEMWATCH_STORE_SLOTS 32
+
+static void memwatch_reset (void)
+{
+ for (int i = 0; i < membank_total; i++) {
+ addrbank *ab = debug_mem_banks[i];
+ if (!ab)
+ continue;
+ map_banks_quick (ab, i, 1, 1);
+ }
+ for (int i = 0; membank_stores[i].addr; i++) {
+ struct membank_store *ms = &membank_stores[i];
+ xfree (ms->newbank.name);
+ memset (ms, 0, sizeof (struct membank_store));
+ ms->addr = NULL;
+ }
+ memset (debug_mem_banks, 0, membank_total * sizeof (addrbank*));
+}
+
+static void memwatch_remap (uaecptr addr)
+{
+ int mode = 0;
+ int i;
+ int banknr;
+ struct membank_store *ms;
+ addrbank *bank;
+ addrbank *newbank = NULL;
+
+ addr &= ~65535;
+ banknr = addr >> 16;
+ if (debug_mem_banks[banknr])
+ return;
+ bank = mem_banks[banknr];
+ for (i = 0 ; i < MEMWATCH_STORE_SLOTS; i++) {
+ ms = &membank_stores[i];
+ if (ms->addr == NULL)
+ break;
+ if (ms->addr == bank) {
+ newbank = &ms->newbank;
+ break;
+ }
+ }
+ if (i >= MEMWATCH_STORE_SLOTS)
+ return;
+ if (!newbank) {
+ TCHAR tmp[200];
+ _stprintf (tmp, _T("%s [D]"), bank->name);
+ ms->addr = bank;
+ newbank = &ms->newbank;
+ memcpy (newbank, bank, sizeof addrbank);
+ newbank->bget = mode ? mmu_bget : debug_bget;
+ newbank->wget = mode ? mmu_wget : debug_wget;
+ newbank->lget = mode ? mmu_lget : debug_lget;
+ newbank->bput = mode ? mmu_bput : debug_bput;
+ newbank->wput = mode ? mmu_wput : debug_wput;
+ newbank->lput = mode ? mmu_lput : debug_lput;
+ newbank->check = debug_check;
+ newbank->xlateaddr = debug_xlate;
+ newbank->wgeti = mode ? mmu_wgeti : debug_wgeti;
+ newbank->lgeti = mode ? mmu_lgeti : debug_lgeti;
+ newbank->name = my_strdup (tmp);
+ if (!newbank->mask)
+ newbank->mask = -1;
+ }
+ debug_mem_banks[banknr] = bank;
+ map_banks_quick (newbank, banknr, 1, 1);
+ // map aliases
+ for (i = 0; i < membank_total; i++) {
+ uaecptr addr2 = i << 16;
+ addrbank *ab = &get_mem_bank(addr2);
+ if (ab != ms->addr)
+ continue;
+ if ((addr2 & ab->mask) == (addr & bank->mask)) {
+ debug_mem_banks[i] = ms->addr;
+ map_banks_quick (newbank, i, 1, 1);
+ }
+ }
+}
+
+static void memwatch_setup (void)
+{
+ memwatch_reset ();
+ for (int i = 0; i < MEMWATCH_TOTAL; i++) {
+ struct memwatch_node *m = &mwnodes[i];
+ uae_u32 size = 0;
+ if (!m->size)
+ continue;
+ while (size < m->size) {
+ memwatch_remap (m->addr + size);
+ size += 65536;
+ }
+ }
+}
static int deinitialize_memwatch (void)
{
- int i, oldmode;
+ int oldmode;
if (!memwatch_enabled && !mmu_enabled)
return -1;
- for (i = 0; membank_stores[i].addr; i++) {
- memcpy (membank_stores[i].addr, &membank_stores[i].store, sizeof (addrbank));
- }
+ memwatch_reset ();
oldmode = mmu_enabled ? 1 : 0;
xfree (debug_mem_banks);
debug_mem_banks = NULL;
static void initialize_memwatch (int mode)
{
+ membank_total = currprefs.address_space_24 ? 256 : 65536;
+ deinitialize_memwatch ();
+ debug_mem_banks = xcalloc (addrbank*, membank_total);
+ debug_mem_area = xcalloc (addrbank, membank_total);
+ membank_stores = xcalloc (struct membank_store, MEMWATCH_STORE_SLOTS);
+#if 0
int i, j, as;
addrbank *a1, *a2, *oa;
-
- deinitialize_memwatch ();
- as = currprefs.address_space_24 ? 256 : 65536;
- debug_mem_banks = xmalloc (addrbank*, as);
- debug_mem_area = xmalloc (addrbank, as);
- membank_stores = xcalloc (struct membank_store, 32);
oa = NULL;
for (i = 0; i < as; i++) {
a1 = debug_mem_banks[i] = debug_mem_area + i;
a2->wgeti = mode ? mmu_wgeti : debug_wgeti;
a2->lgeti = mode ? mmu_lgeti : debug_lgeti;
}
+#endif
if (mode)
mmu_enabled = 1;
else
ignore_ws (c);
if (!more_params (c)) {
console_out_f (_T("Memwatch %d removed\n"), num);
+ memwatch_setup ();
return;
}
mwn->addr = readhex (c);
}
if (mwn->frozen && mwn->rwi == 0)
mwn->rwi = 3;
+ memwatch_setup ();
memwatch_dump (num);
}
{
uae_u32 *m;
- addr -= chipmem_start & chipmem_mask;
- addr &= chipmem_mask;
- m = (uae_u32 *)(chipmemory + addr);
+ addr -= chipmem_start_addr & chipmem_bank.mask;
+ addr &= chipmem_bank.mask;
+ m = (uae_u32 *)(chipmem_bank.baseaddr + addr);
if (ISILLEGAL_LONG (addr))
{
{
uae_u16 *m;
- addr -= chipmem_start & chipmem_mask;
- addr &= chipmem_mask;
- m = (uae_u16 *)(chipmemory + addr);
+ addr -= chipmem_start_addr & chipmem_bank.mask;
+ addr &= chipmem_bank.mask;
+ m = (uae_u16 *)(chipmem_bank.baseaddr + addr);
if (ISILLEGAL_WORD (addr))
{
uae_u32 REGPARAM2 chipmem_bget2 (uaecptr addr)
{
- addr -= chipmem_start & chipmem_mask;
- addr &= chipmem_mask;
+ addr -= chipmem_start_addr & chipmem_bank.mask;
+ addr &= chipmem_bank.mask;
if (ISILLEGAL_BYTE (addr))
{
set_special (SPCFLAG_TRAP);
}
- return chipmemory[addr];
+ return chipmem_bank.baseaddr[addr];
}
void REGPARAM2 chipmem_lput2 (uaecptr addr, uae_u32 l)
{
uae_u32 *m;
- addr -= chipmem_start & chipmem_mask;
- addr &= chipmem_mask;
- m = (uae_u32 *)(chipmemory + addr);
+ addr -= chipmem_start_addr & chipmem_bank.mask;
+ addr &= chipmem_bank.mask;
+ m = (uae_u32 *)(chipmem_bank.baseaddr + addr);
if (ISILLEGAL_LONG (addr))
{
{
uae_u16 *m;
- addr -= chipmem_start & chipmem_mask;
- addr &= chipmem_mask;
- m = (uae_u16 *)(chipmemory + addr);
+ addr -= chipmem_start_addr & chipmem_bank.mask;
+ addr &= chipmem_bank.mask;
+ m = (uae_u16 *)(chipmem_bank.baseaddr + addr);
if (ISILLEGAL_WORD (addr))
{
void REGPARAM2 chipmem_bput2 (uaecptr addr, uae_u32 b)
{
- addr -= chipmem_start & chipmem_mask;
- addr &= chipmem_mask;
+ addr -= chipmem_start_addr & chipmem_bank.mask;
+ addr &= chipmem_bank.mask;
if (ISILLEGAL_BYTE (addr))
{
}
if (ISEXEC (addr))
return;
- chipmemory[addr] = b;
+ chipmem_bank.baseaddr[addr] = b;
}
int REGPARAM2 chipmem_check2 (uaecptr addr, uae_u32 size)
{
- addr -= chipmem_start & chipmem_mask;
- addr &= chipmem_mask;
- return (addr + size) <= allocated_chipmem;
+ addr -= chipmem_start_addr & chipmem_bank.mask;
+ addr &= chipmem_bank.mask;
+ return (addr + size) <= chipmem_bank.allocated;
}
uae_u8 * REGPARAM2 chipmem_xlate2 (uaecptr addr)
{
- addr -= chipmem_start & chipmem_mask;
- addr &= chipmem_mask;
- return chipmemory + addr;
+ addr -= chipmem_start_addr & chipmem_bank.mask;
+ addr &= chipmem_bank.mask;
+ return chipmem_bank.baseaddr + addr;
}
uae_u32 REGPARAM2 dummy_lget2 (uaecptr addr)
p2 = 0;
while (!p2 && z3num < 2) {
if (z3num == 0 && currprefs.z3fastmem_size)
- p2 = z3fastmem_start >> 16;
+ p2 = z3fastmem_bank.start >> 16;
else if (z3num == 1 && currprefs.z3fastmem2_size)
- p2 = z3fastmem2_start >> 16;
+ p2 = z3fastmem2_bank.start >> 16;
if (!p2)
z3num++;
}
z3num++;
} else {
// Z3 P96 RAM
- if (p96ram_start & 0xff000000)
- p2 = p96ram_start >> 16;
+ if (gfxmem_bank.start & 0xff000000)
+ p2 = gfxmem_bank.start >> 16;
}
put_word (regs.regs[11] + 0x20, p2);
put_word (regs.regs[11] + 0x28, p2);
* Fast Memory
*/
-static uae_u32 fastmem_mask;
-static uae_u32 REGPARAM3 fastmem_lget (uaecptr) REGPARAM;
-static uae_u32 REGPARAM3 fastmem_wget (uaecptr) REGPARAM;
-static uae_u32 REGPARAM3 fastmem_bget (uaecptr) REGPARAM;
-static void REGPARAM3 fastmem_lput (uaecptr, uae_u32) REGPARAM;
-static void REGPARAM3 fastmem_wput (uaecptr, uae_u32) REGPARAM;
-static void REGPARAM3 fastmem_bput (uaecptr, uae_u32) REGPARAM;
-static int REGPARAM3 fastmem_check (uaecptr addr, uae_u32 size) REGPARAM;
-static uae_u8 *REGPARAM3 fastmem_xlate (uaecptr addr) REGPARAM;
-
-uaecptr fastmem_start; /* Determined by the OS */
-static uae_u8 *fastmemory;
-
-static uae_u32 REGPARAM2 fastmem_lget (uaecptr addr)
-{
- uae_u8 *m;
- addr -= fastmem_start & fastmem_mask;
- addr &= fastmem_mask;
- m = fastmemory + addr;
- return do_get_mem_long ((uae_u32 *)m);
-}
-
-static uae_u32 REGPARAM2 fastmem_wget (uaecptr addr)
-{
- uae_u8 *m;
- addr -= fastmem_start & fastmem_mask;
- addr &= fastmem_mask;
- m = fastmemory + addr;
- return do_get_mem_word ((uae_u16 *)m);
-}
-
-static uae_u32 REGPARAM2 fastmem_bget (uaecptr addr)
-{
- addr -= fastmem_start & fastmem_mask;
- addr &= fastmem_mask;
- return fastmemory[addr];
-}
-
-static void REGPARAM2 fastmem_lput (uaecptr addr, uae_u32 l)
-{
- uae_u8 *m;
- addr -= fastmem_start & fastmem_mask;
- addr &= fastmem_mask;
- m = fastmemory + addr;
- do_put_mem_long ((uae_u32 *)m, l);
-}
-
-static void REGPARAM2 fastmem_wput (uaecptr addr, uae_u32 w)
-{
- uae_u8 *m;
- addr -= fastmem_start & fastmem_mask;
- addr &= fastmem_mask;
- m = fastmemory + addr;
- do_put_mem_word ((uae_u16 *)m, w);
-}
-
-static void REGPARAM2 fastmem_bput (uaecptr addr, uae_u32 b)
-{
- addr -= fastmem_start & fastmem_mask;
- addr &= fastmem_mask;
- fastmemory[addr] = b;
-}
-
-static int REGPARAM2 fastmem_check (uaecptr addr, uae_u32 size)
-{
- addr -= fastmem_start & fastmem_mask;
- addr &= fastmem_mask;
- return (addr + size) <= allocated_fastmem;
-}
-
-static uae_u8 *REGPARAM2 fastmem_xlate (uaecptr addr)
-{
- addr -= fastmem_start & fastmem_mask;
- addr &= fastmem_mask;
- return fastmemory + addr;
-}
+MEMORY_FUNCTIONS(fastmem);
addrbank fastmem_bank = {
fastmem_lget, fastmem_wget, fastmem_bget,
* Z3fastmem Memory
*/
-static uae_u32 z3fastmem_mask, z3fastmem2_mask, z3chipmem_mask;
-uaecptr z3fastmem_start, z3fastmem2_start, z3chipmem_start;
-static uae_u8 *z3fastmem, *z3fastmem2, *z3chipmem;
-
-static uae_u32 REGPARAM2 z3fastmem_lget (uaecptr addr)
-{
- uae_u8 *m;
- addr -= z3fastmem_start & z3fastmem_mask;
- addr &= z3fastmem_mask;
- m = z3fastmem + addr;
- return do_get_mem_long ((uae_u32 *)m);
-}
-static uae_u32 REGPARAM2 z3fastmem_wget (uaecptr addr)
-{
- uae_u8 *m;
- addr -= z3fastmem_start & z3fastmem_mask;
- addr &= z3fastmem_mask;
- m = z3fastmem + addr;
- return do_get_mem_word ((uae_u16 *)m);
-}
-
-static uae_u32 REGPARAM2 z3fastmem_bget (uaecptr addr)
-{
- addr -= z3fastmem_start & z3fastmem_mask;
- addr &= z3fastmem_mask;
- return z3fastmem[addr];
-}
-static void REGPARAM2 z3fastmem_lput (uaecptr addr, uae_u32 l)
-{
- uae_u8 *m;
- addr -= z3fastmem_start & z3fastmem_mask;
- addr &= z3fastmem_mask;
- m = z3fastmem + addr;
- do_put_mem_long ((uae_u32 *)m, l);
-}
-static void REGPARAM2 z3fastmem_wput (uaecptr addr, uae_u32 w)
-{
- uae_u8 *m;
- addr -= z3fastmem_start & z3fastmem_mask;
- addr &= z3fastmem_mask;
- m = z3fastmem + addr;
- do_put_mem_word ((uae_u16 *)m, w);
-}
-static void REGPARAM2 z3fastmem_bput (uaecptr addr, uae_u32 b)
-{
- addr -= z3fastmem_start & z3fastmem_mask;
- addr &= z3fastmem_mask;
- z3fastmem[addr] = b;
-}
-static int REGPARAM2 z3fastmem_check (uaecptr addr, uae_u32 size)
-{
- addr -= z3fastmem_start & z3fastmem_mask;
- addr &= z3fastmem_mask;
- return (addr + size) <= allocated_z3fastmem;
-}
-static uae_u8 *REGPARAM2 z3fastmem_xlate (uaecptr addr)
-{
- addr -= z3fastmem_start & z3fastmem_mask;
- addr &= z3fastmem_mask;
- return z3fastmem + addr;
-}
-
-static uae_u32 REGPARAM2 z3fastmem2_lget (uaecptr addr)
-{
- uae_u8 *m;
- addr -= z3fastmem2_start & z3fastmem2_mask;
- addr &= z3fastmem2_mask;
- m = z3fastmem2 + addr;
- return do_get_mem_long ((uae_u32 *)m);
-}
-static uae_u32 REGPARAM2 z3fastmem2_wget (uaecptr addr)
-{
- uae_u8 *m;
- addr -= z3fastmem2_start & z3fastmem2_mask;
- addr &= z3fastmem2_mask;
- m = z3fastmem2 + addr;
- return do_get_mem_word ((uae_u16 *)m);
-}
-static uae_u32 REGPARAM2 z3fastmem2_bget (uaecptr addr)
-{
- addr -= z3fastmem2_start & z3fastmem2_mask;
- addr &= z3fastmem2_mask;
- return z3fastmem2[addr];
-}
-static void REGPARAM2 z3fastmem2_lput (uaecptr addr, uae_u32 l)
-{
- uae_u8 *m;
- addr -= z3fastmem2_start & z3fastmem2_mask;
- addr &= z3fastmem2_mask;
- m = z3fastmem2 + addr;
- do_put_mem_long ((uae_u32 *)m, l);
-}
-static void REGPARAM2 z3fastmem2_wput (uaecptr addr, uae_u32 w)
-{
- uae_u8 *m;
- addr -= z3fastmem2_start & z3fastmem2_mask;
- addr &= z3fastmem2_mask;
- m = z3fastmem2 + addr;
- do_put_mem_word ((uae_u16 *)m, w);
-}
-static void REGPARAM2 z3fastmem2_bput (uaecptr addr, uae_u32 b)
-{
- addr -= z3fastmem2_start & z3fastmem2_mask;
- addr &= z3fastmem2_mask;
- z3fastmem2[addr] = b;
-}
-static int REGPARAM2 z3fastmem2_check (uaecptr addr, uae_u32 size)
-{
- addr -= z3fastmem2_start & z3fastmem2_mask;
- addr &= z3fastmem2_mask;
- return (addr + size) <= allocated_z3fastmem2;
-}
-static uae_u8 *REGPARAM2 z3fastmem2_xlate (uaecptr addr)
-{
- addr -= z3fastmem2_start & z3fastmem2_mask;
- addr &= z3fastmem2_mask;
- return z3fastmem2 + addr;
-}
-
-static uae_u32 REGPARAM2 z3chipmem_lget (uaecptr addr)
-{
- uae_u8 *m;
- addr -= z3chipmem_start & z3chipmem_mask;
- addr &= z3chipmem_mask;
- m = z3chipmem + addr;
- return do_get_mem_long ((uae_u32 *)m);
-}
-static uae_u32 REGPARAM2 z3chipmem_wget (uaecptr addr)
-{
- uae_u8 *m;
- addr -= z3chipmem_start & z3chipmem_mask;
- addr &= z3chipmem_mask;
- m = z3chipmem + addr;
- return do_get_mem_word ((uae_u16 *)m);
-}
-static uae_u32 REGPARAM2 z3chipmem_bget (uaecptr addr)
-{
- addr -= z3chipmem_start & z3chipmem_mask;
- addr &= z3chipmem_mask;
- return z3chipmem[addr];
-}
-static void REGPARAM2 z3chipmem_lput (uaecptr addr, uae_u32 l)
-{
- uae_u8 *m;
- addr -= z3chipmem_start & z3chipmem_mask;
- addr &= z3chipmem_mask;
- m = z3chipmem + addr;
- do_put_mem_long ((uae_u32 *)m, l);
-}
-static void REGPARAM2 z3chipmem_wput (uaecptr addr, uae_u32 w)
-{
- uae_u8 *m;
- addr -= z3chipmem_start & z3chipmem_mask;
- addr &= z3chipmem_mask;
- m = z3chipmem + addr;
- do_put_mem_word ((uae_u16 *)m, w);
-}
-static void REGPARAM2 z3chipmem_bput (uaecptr addr, uae_u32 b)
-{
- addr -= z3chipmem_start & z3chipmem_mask;
- addr &= z3chipmem_mask;
- z3chipmem[addr] = b;
-}
-static int REGPARAM2 z3chipmem_check (uaecptr addr, uae_u32 size)
-{
- addr -= z3chipmem_start & z3chipmem_mask;
- addr &= z3chipmem_mask;
- return (addr + size) <= allocated_z3chipmem;
-}
-static uae_u8 *REGPARAM2 z3chipmem_xlate (uaecptr addr)
-{
- addr -= z3chipmem_start & z3chipmem_mask;
- addr &= z3chipmem_mask;
- return z3chipmem + addr;
-}
-
+MEMORY_FUNCTIONS(z3fastmem);
+MEMORY_FUNCTIONS(z3fastmem2);
+MEMORY_FUNCTIONS(z3chipmem);
addrbank z3fastmem_bank = {
z3fastmem_lget, z3fastmem_wget, z3fastmem_bget,
};
/* Z3-based UAEGFX-card */
-uae_u32 gfxmem_mask; /* for memory.c */
-uae_u8 *gfxmemory;
-uae_u32 gfxmem_start;
/* ********************************************************** */
static void expamem_map_fastcard (void)
{
- fastmem_start = ((expamem_hi | (expamem_lo >> 4)) << 16);
- if (fastmem_start) {
- map_banks (&fastmem_bank, fastmem_start >> 16, allocated_fastmem >> 16, 0);
- write_log (_T("Fastcard: mapped @$%lx: %dMB fast memory\n"), fastmem_start, allocated_fastmem >> 20);
+ fastmem_bank.start = ((expamem_hi | (expamem_lo >> 4)) << 16);
+ if (fastmem_bank.start) {
+ map_banks (&fastmem_bank, fastmem_bank.start >> 16, fastmem_bank.allocated >> 16, 0);
+ write_log (_T("Fastcard: mapped @$%lx: %dMB fast memory\n"), fastmem_bank.start, fastmem_bank.allocated >> 20);
}
}
uae_u8 pid = (currprefs.cs_a2091 || currprefs.uae_hide) ? commodore_a2091_ram : (currprefs.maprom ? 1 : 81);
expamem_init_clear ();
- if (allocated_fastmem == 0x100000)
+ if (fastmem_bank.allocated == 0x100000)
expamem_write (0x00, Z2_MEM_1MB + add_memory + zorroII);
- else if (allocated_fastmem == 0x200000)
+ else if (fastmem_bank.allocated == 0x200000)
expamem_write (0x00, Z2_MEM_2MB + add_memory + zorroII);
- else if (allocated_fastmem == 0x400000)
+ else if (fastmem_bank.allocated == 0x400000)
expamem_write (0x00, Z2_MEM_4MB + add_memory + zorroII);
- else if (allocated_fastmem == 0x800000)
+ else if (fastmem_bank.allocated == 0x800000)
expamem_write (0x00, Z2_MEM_8MB + add_memory + zorroII);
expamem_write (0x08, care_addr);
static void expamem_map_z3fastmem (void)
{
- expamem_map_z3fastmem_2 (&z3fastmem_bank, &z3fastmem_start, currprefs.z3fastmem_size, allocated_z3fastmem, 0);
+ expamem_map_z3fastmem_2 (&z3fastmem_bank, &z3fastmem_bank.start, currprefs.z3fastmem_size, z3fastmem_bank.allocated, 0);
}
static void expamem_map_z3fastmem2 (void)
{
- expamem_map_z3fastmem_2 (&z3fastmem2_bank, &z3fastmem2_start, currprefs.z3fastmem2_size, allocated_z3fastmem2, 0);
+ expamem_map_z3fastmem_2 (&z3fastmem2_bank, &z3fastmem2_bank.start, currprefs.z3fastmem2_size, z3fastmem2_bank.allocated, 0);
}
static void expamem_init_z3fastmem_2 (addrbank *bank, uae_u32 start, uae_u32 size, uae_u32 allocated)
}
static void expamem_init_z3fastmem (void)
{
- expamem_init_z3fastmem_2 (&z3fastmem_bank, z3fastmem_start, currprefs.z3fastmem_size, allocated_z3fastmem);
+ expamem_init_z3fastmem_2 (&z3fastmem_bank, z3fastmem_bank.start, currprefs.z3fastmem_size, z3fastmem_bank.allocated);
}
static void expamem_init_z3fastmem2 (void)
{
- expamem_init_z3fastmem_2 (&z3fastmem2_bank, z3fastmem2_start, currprefs.z3fastmem2_size, allocated_z3fastmem2);
+ expamem_init_z3fastmem_2 (&z3fastmem2_bank, z3fastmem2_bank.start, currprefs.z3fastmem2_size, z3fastmem2_bank.allocated);
}
#ifdef PICASSO96
* Fake Graphics Card (ZORRO III) - BDK
*/
-uaecptr p96ram_start;
-
static void expamem_map_gfxcard (void)
{
- gfxmem_start = (expamem_hi | (expamem_lo >> 4)) << 16;
- if (gfxmem_start) {
- map_banks (&gfxmem_bank, gfxmem_start >> 16, allocated_gfxmem >> 16, allocated_gfxmem);
- write_log (_T("%sUAEGFX-card: mapped @$%lx, %d MB RTG RAM\n"), currprefs.rtgmem_type ? _T("Z3") : _T("Z2"), gfxmem_start, allocated_gfxmem / 0x100000);
+ gfxmem_bank.start = (expamem_hi | (expamem_lo >> 4)) << 16;
+ if (gfxmem_bank.start) {
+ map_banks (&gfxmem_bank, gfxmem_bank.start >> 16, gfxmem_bank.allocated >> 16, gfxmem_bank.allocated);
+ write_log (_T("%sUAEGFX-card: mapped @$%lx, %d MB RTG RAM\n"), currprefs.rtgmem_type ? _T("Z3") : _T("Z2"), gfxmem_bank.baseaddr, gfxmem_bank.allocated / 0x100000);
}
}
static void expamem_init_gfxcard (bool z3)
{
- int code = (allocated_gfxmem == 0x100000 ? Z2_MEM_1MB
- : allocated_gfxmem == 0x200000 ? Z2_MEM_2MB
- : allocated_gfxmem == 0x400000 ? Z2_MEM_4MB
- : allocated_gfxmem == 0x800000 ? Z2_MEM_8MB
- : allocated_gfxmem == 0x1000000 ? Z3_MEM_16MB
- : allocated_gfxmem == 0x2000000 ? Z3_MEM_32MB
- : allocated_gfxmem == 0x4000000 ? Z3_MEM_64MB
- : allocated_gfxmem == 0x8000000 ? Z3_MEM_128MB
- : allocated_gfxmem == 0x10000000 ? Z3_MEM_256MB
- : allocated_gfxmem == 0x20000000 ? Z3_MEM_512MB
+ int code = (gfxmem_bank.allocated == 0x100000 ? Z2_MEM_1MB
+ : gfxmem_bank.allocated == 0x200000 ? Z2_MEM_2MB
+ : gfxmem_bank.allocated == 0x400000 ? Z2_MEM_4MB
+ : gfxmem_bank.allocated == 0x800000 ? Z2_MEM_8MB
+ : gfxmem_bank.allocated == 0x1000000 ? Z3_MEM_16MB
+ : gfxmem_bank.allocated == 0x2000000 ? Z3_MEM_32MB
+ : gfxmem_bank.allocated == 0x4000000 ? Z3_MEM_64MB
+ : gfxmem_bank.allocated == 0x8000000 ? Z3_MEM_128MB
+ : gfxmem_bank.allocated == 0x10000000 ? Z3_MEM_256MB
+ : gfxmem_bank.allocated == 0x20000000 ? Z3_MEM_512MB
: Z3_MEM_1GB);
- int subsize = (allocated_gfxmem == 0x100000 ? Z3_SS_MEM_1MB
- : allocated_gfxmem == 0x200000 ? Z3_SS_MEM_2MB
- : allocated_gfxmem == 0x400000 ? Z3_SS_MEM_4MB
- : allocated_gfxmem == 0x800000 ? Z3_SS_MEM_8MB
+ int subsize = (gfxmem_bank.allocated == 0x100000 ? Z3_SS_MEM_1MB
+ : gfxmem_bank.allocated == 0x200000 ? Z3_SS_MEM_2MB
+ : gfxmem_bank.allocated == 0x400000 ? Z3_SS_MEM_4MB
+ : gfxmem_bank.allocated == 0x800000 ? Z3_SS_MEM_8MB
: Z3_SS_MEM_SAME);
- if (allocated_gfxmem < 0x1000000 && z3)
+ if (gfxmem_bank.allocated < 0x1000000 && z3)
code = Z3_MEM_16MB; /* Z3 physical board size is always at least 16M */
expamem_init_clear ();
expamem_write (0x00, (z3 ? zorroIII : zorroII) | code);
- expamem_write (0x08, care_addr | (z3 ? (force_z3 | (allocated_gfxmem > 0x800000 ? ext_size: subsize)) : 0));
+ expamem_write (0x08, care_addr | (z3 ? (force_z3 | (gfxmem_bank.allocated > 0x800000 ? ext_size: subsize)) : 0));
expamem_write (0x04, 96);
expamem_write (0x10, uae_id >> 8);
void free_fastmemory (void)
{
- if (fastmemory)
- mapped_free (fastmemory);
- fastmemory = 0;
+ if (fastmem_bank.baseaddr)
+ mapped_free (fastmem_bank.baseaddr);
+ fastmem_bank.baseaddr = 0;
}
-static bool mapped_malloc_dynamic (uae_u32 *currpsize, uae_u32 *changedpsize, uae_u8 **memory, uae_u32 *allocated, uae_u32 *mask, int max, const TCHAR *name)
+static bool mapped_malloc_dynamic (uae_u32 *currpsize, uae_u32 *changedpsize, addrbank *bank, int max, const TCHAR *name)
{
int alloc = *currpsize;
- *allocated = 0;
- *memory = NULL;
- *mask = 0;
+ bank->allocated = 0;
+ bank->baseaddr = NULL;
+ bank->mask = 0;
if (!alloc)
return false;
while (alloc >= max * 1024 * 1024) {
uae_u8 *mem = mapped_malloc (alloc, name);
if (mem) {
- *memory = mem;
+ bank->baseaddr = mem;
*currpsize = alloc;
*changedpsize = alloc;
- *mask = alloc - 1;
- *allocated = alloc;
+ bank->mask = alloc - 1;
+ bank->allocated = alloc;
return true;
}
write_log (_T("Out of memory for %s, %d bytes.\n"), name, alloc);
currprefs.rtgmem_type = changed_prefs.rtgmem_type;
currprefs.z3chipmem_size = changed_prefs.z3chipmem_size;
- z3chipmem_start = currprefs.z3fastmem_start;
- z3fastmem_start = currprefs.z3fastmem_start;
+ z3chipmem_bank.start = currprefs.z3fastmem_start;
+ z3fastmem_bank.start = currprefs.z3fastmem_start;
if (currprefs.z3chipmem_size)
- z3fastmem_start += currprefs.z3chipmem_size + 16 * 1024 * 1024;
- z3fastmem2_start = z3fastmem_start + currprefs.z3fastmem_size;
+ z3fastmem_bank.start += currprefs.z3chipmem_size + 16 * 1024 * 1024;
+ z3fastmem2_bank.start = z3fastmem_bank.start + currprefs.z3fastmem_size;
- if (allocated_fastmem != currprefs.fastmem_size) {
+ if (fastmem_bank.allocated != currprefs.fastmem_size) {
free_fastmemory ();
- allocated_fastmem = currprefs.fastmem_size;
- fastmem_mask = allocated_fastmem - 1;
+ fastmem_bank.allocated = currprefs.fastmem_size;
+ fastmem_bank.mask = fastmem_bank.allocated - 1;
- if (allocated_fastmem) {
- fastmemory = mapped_malloc (allocated_fastmem, _T("fast"));
- if (fastmemory == 0) {
+ if (fastmem_bank.allocated) {
+ fastmem_bank.baseaddr = mapped_malloc (fastmem_bank.allocated, _T("fast"));
+ if (fastmem_bank.baseaddr == 0) {
write_log (_T("Out of memory for fastmem card.\n"));
- allocated_fastmem = 0;
+ fastmem_bank.allocated = 0;
}
}
memory_hardreset (1);
}
- if (allocated_z3fastmem != currprefs.z3fastmem_size) {
- if (z3fastmem)
- mapped_free (z3fastmem);
- mapped_malloc_dynamic (&currprefs.z3fastmem_size, &changed_prefs.z3fastmem_size, &z3fastmem, &allocated_z3fastmem, &z3fastmem_mask, 1, _T("z3"));
+ if (z3fastmem_bank.allocated != currprefs.z3fastmem_size) {
+ if (z3fastmem_bank.baseaddr)
+ mapped_free (z3fastmem_bank.baseaddr);
+ mapped_malloc_dynamic (&currprefs.z3fastmem_size, &changed_prefs.z3fastmem_size, &z3fastmem_bank, 1, _T("z3"));
memory_hardreset (1);
}
- if (allocated_z3fastmem2 != currprefs.z3fastmem2_size) {
- if (z3fastmem2)
- mapped_free (z3fastmem2);
- z3fastmem2 = 0;
+ if (z3fastmem2_bank.allocated != currprefs.z3fastmem2_size) {
+ if (z3fastmem2_bank.baseaddr)
+ mapped_free (z3fastmem2_bank.baseaddr);
+ z3fastmem2_bank.baseaddr = 0;
- allocated_z3fastmem2 = currprefs.z3fastmem2_size;
- z3fastmem2_mask = allocated_z3fastmem2 - 1;
+ z3fastmem2_bank.allocated = currprefs.z3fastmem2_size;
+ z3fastmem2_bank.mask = z3fastmem2_bank.allocated - 1;
- if (allocated_z3fastmem2) {
- z3fastmem2 = mapped_malloc (allocated_z3fastmem2, _T("z3_2"));
- if (z3fastmem2 == 0) {
+ if (z3fastmem2_bank.allocated) {
+ z3fastmem2_bank.baseaddr = mapped_malloc (z3fastmem2_bank.allocated, _T("z3_2"));
+ if (z3fastmem2_bank.baseaddr == 0) {
write_log (_T("Out of memory for 32 bit fast memory #2.\n"));
- allocated_z3fastmem2 = 0;
+ z3fastmem2_bank.allocated = 0;
}
}
memory_hardreset (1);
}
- if (allocated_z3chipmem != currprefs.z3chipmem_size) {
- if (z3chipmem)
- mapped_free (z3chipmem);
- mapped_malloc_dynamic (&currprefs.z3chipmem_size, &changed_prefs.z3chipmem_size, &z3chipmem, &allocated_z3chipmem, &z3chipmem_mask, 16, _T("z3_chip"));
+ if (z3chipmem_bank.allocated != currprefs.z3chipmem_size) {
+ if (z3chipmem_bank.baseaddr)
+ mapped_free (z3chipmem_bank.baseaddr);
+ mapped_malloc_dynamic (&currprefs.z3chipmem_size, &changed_prefs.z3chipmem_size, &z3chipmem_bank, 16, _T("z3_chip"));
memory_hardreset (1);
}
#ifdef PICASSO96
- if (allocated_gfxmem != currprefs.rtgmem_size) {
- if (gfxmemory)
- mapped_free (gfxmemory);
- mapped_malloc_dynamic (&currprefs.rtgmem_size, &changed_prefs.rtgmem_size, &gfxmemory, &allocated_gfxmem, &gfxmem_mask, 1, currprefs.rtgmem_type ? _T("z3_gfx") : _T("z2_gfx"));
+ if (gfxmem_bank.allocated != currprefs.rtgmem_size) {
+ if (gfxmem_bank.baseaddr)
+ mapped_free (gfxmem_bank.baseaddr);
+ mapped_malloc_dynamic (&currprefs.rtgmem_size, &changed_prefs.rtgmem_size, &gfxmem_bank, 1, currprefs.rtgmem_type ? _T("z3_gfx") : _T("z2_gfx"));
memory_hardreset (1);
}
#endif
- z3fastmem_bank.baseaddr = z3fastmem;
- z3fastmem2_bank.baseaddr = z3fastmem2;
- z3chipmem_bank.baseaddr = z3chipmem;
- fastmem_bank.baseaddr = fastmemory;
-#ifdef PICASSO96
- gfxmem_bank.baseaddr = gfxmemory;
-#endif
-
#ifdef SAVESTATE
if (savestate_state == STATE_RESTORE) {
- if (allocated_fastmem > 0) {
- restore_ram (fast_filepos, fastmemory);
- map_banks (&fastmem_bank, fastmem_start >> 16, currprefs.fastmem_size >> 16,
- allocated_fastmem);
+ if (fastmem_bank.allocated > 0) {
+ restore_ram (fast_filepos, fastmem_bank.baseaddr);
+ map_banks (&fastmem_bank, fastmem_bank.start >> 16, currprefs.fastmem_size >> 16,
+ fastmem_bank.allocated);
}
- if (allocated_z3fastmem > 0) {
- restore_ram (z3_filepos, z3fastmem);
- map_banks (&z3fastmem_bank, z3fastmem_start >> 16, currprefs.z3fastmem_size >> 16,
- allocated_z3fastmem);
+ if (z3fastmem_bank.allocated > 0) {
+ restore_ram (z3_filepos, z3fastmem_bank.baseaddr);
+ map_banks (&z3fastmem_bank, z3fastmem_bank.start >> 16, currprefs.z3fastmem_size >> 16,
+ z3fastmem_bank.allocated);
}
- if (allocated_z3fastmem2 > 0) {
- restore_ram (z3_filepos2, z3fastmem2);
- map_banks (&z3fastmem2_bank, z3fastmem2_start >> 16, currprefs.z3fastmem2_size >> 16,
- allocated_z3fastmem2);
+ if (z3fastmem2_bank.allocated > 0) {
+ restore_ram (z3_filepos2, z3fastmem2_bank.baseaddr);
+ map_banks (&z3fastmem2_bank, z3fastmem2_bank.start >> 16, currprefs.z3fastmem2_size >> 16,
+ z3fastmem2_bank.allocated);
}
- if (allocated_z3chipmem > 0) {
- restore_ram (z3_fileposchip, z3chipmem);
- map_banks (&z3chipmem_bank, z3chipmem_start >> 16, currprefs.z3chipmem_size >> 16,
- allocated_z3fastmem2);
+ if (z3chipmem_bank.allocated > 0) {
+ restore_ram (z3_fileposchip, z3chipmem_bank.baseaddr);
+ map_banks (&z3chipmem_bank, z3chipmem_bank.start >> 16, currprefs.z3chipmem_size >> 16,
+ z3chipmem_bank.allocated);
}
#ifdef PICASSO96
- if (allocated_gfxmem > 0 && gfxmem_start > 0) {
- restore_ram (p96_filepos, gfxmemory);
- map_banks (&gfxmem_bank, gfxmem_start >> 16, currprefs.rtgmem_size >> 16,
- allocated_gfxmem);
+ if (gfxmem_bank.allocated > 0 && gfxmem_bank.start > 0) {
+ restore_ram (p96_filepos, gfxmem_bank.baseaddr);
+ map_banks (&gfxmem_bank, gfxmem_bank.start >> 16, currprefs.rtgmem_size >> 16,
+ gfxmem_bank.allocated);
}
#endif
}
void p96memstart (void)
{
/* make sure there is always empty space between Z3 and P96 RAM */
- p96ram_start = currprefs.z3fastmem_start + ((currprefs.z3fastmem_size + currprefs.z3fastmem2_size + currprefs.z3chipmem_size + 0xffffff) & ~0xffffff);
- if (p96ram_start == currprefs.z3fastmem_start + currprefs.z3fastmem_size + currprefs.z3fastmem2_size + currprefs.z3chipmem_size &&
+ p96ram_start = currprefs.z3fastmem_bank.start + ((currprefs.z3fastmem_size + currprefs.z3fastmem2_size + currprefs.z3chipmem_size + 0xffffff) & ~0xffffff);
+ if (p96ram_start == currprefs.z3fastmem_bank.start + currprefs.z3fastmem_size + currprefs.z3fastmem2_size + currprefs.z3chipmem_size &&
(currprefs.z3fastmem_size + currprefs.z3fastmem2_size + currprefs.z3chipmem_size < 512 * 1024 * 1024 || currprefs.rtgmem_size < 128 * 1024 * 1024))
p96ram_start += 0x1000000;
}
}
if (need_uae_boot_rom () == 0)
do_mount = 0;
- if (fastmemory != NULL && currprefs.chipmem_size <= 2 * 1024 * 1024) {
+ if (fastmem_bank.baseaddr != NULL && currprefs.chipmem_size <= 2 * 1024 * 1024) {
if (currprefs.fastmem_autoconfig) {
fastmem_bank.name = _T("Fast memory");
card_name[cardno] = _T("Z2Fast");
card_map[cardno++] = expamem_map_fastcard;
} else {
fastmem_bank.name = _T("Fast memory (non-autoconfig)");
- map_banks (&fastmem_bank, 0x00200000 >> 16, allocated_fastmem >> 16, 0);
+ map_banks (&fastmem_bank, 0x00200000 >> 16, fastmem_bank.allocated >> 16, 0);
}
}
}
#endif
#ifdef PICASSO96
- if (currprefs.rtgmem_type == GFXBOARD_UAE_Z2 && gfxmemory != NULL) {
+ if (currprefs.rtgmem_type == GFXBOARD_UAE_Z2 && gfxmem_bank.baseaddr != NULL) {
card_name[cardno] = _T("Z2RTG");
card_init[cardno] = expamem_init_gfxcard_z2;
card_map[cardno++] = expamem_map_gfxcard;
#endif
/* Z3 boards last */
- if (z3fastmem != NULL) {
+ if (z3fastmem_bank.baseaddr != NULL) {
z3num = 0;
card_name[cardno] = _T("Z3Fast");
card_init[cardno] = expamem_init_z3fastmem;
card_map[cardno++] = expamem_map_z3fastmem;
- map_banks (&z3fastmem_bank, z3fastmem_start >> 16, currprefs.z3fastmem_size >> 16, allocated_z3fastmem);
- if (z3fastmem2 != NULL) {
+ map_banks (&z3fastmem_bank, z3fastmem_bank.start >> 16, currprefs.z3fastmem_size >> 16, z3fastmem_bank.allocated);
+ if (z3fastmem2_bank.baseaddr != NULL) {
card_name[cardno] = _T("Z3Fast2");
card_init[cardno] = expamem_init_z3fastmem2;
card_map[cardno++] = expamem_map_z3fastmem2;
- map_banks (&z3fastmem2_bank, z3fastmem2_start >> 16, currprefs.z3fastmem2_size >> 16, allocated_z3fastmem2);
+ map_banks (&z3fastmem2_bank, z3fastmem2_bank.start >> 16, currprefs.z3fastmem2_size >> 16, z3fastmem2_bank.allocated);
}
}
- if (z3chipmem != NULL)
- map_banks (&z3chipmem_bank, z3chipmem_start >> 16, currprefs.z3chipmem_size >> 16, allocated_z3chipmem);
+ if (z3chipmem_bank.baseaddr != NULL)
+ map_banks (&z3chipmem_bank, z3chipmem_bank.start >> 16, currprefs.z3chipmem_size >> 16, z3chipmem_bank.allocated);
#ifdef NCR
if (currprefs.cs_a4091) {
card_name[cardno] = _T("A4091");
}
#endif
#ifdef PICASSO96
- if (currprefs.rtgmem_type == GFXBOARD_UAE_Z3 && gfxmemory != NULL) {
+ if (currprefs.rtgmem_type == GFXBOARD_UAE_Z3 && gfxmem_bank.baseaddr != NULL) {
card_name[cardno] = _T("Z3RTG");
card_init[cardno] = expamem_init_gfxcard_z3;
card_map[cardno++] = expamem_map_gfxcard;
{
if (savestate_state != STATE_RESTORE) {
- allocated_fastmem = 0;
- fastmem_mask = fastmem_start = 0;
- fastmemory = 0;
+ fastmem_bank.allocated = 0;
+ fastmem_bank.mask = fastmem_bank.start = 0;
+ fastmem_bank.baseaddr = NULL;
#ifdef PICASSO96
- allocated_gfxmem = 0;
- gfxmem_mask = gfxmem_start = 0;
- gfxmemory = 0;
+ gfxmem_bank.allocated = 0;
+ gfxmem_bank.mask = gfxmem_bank.start = 0;
+ gfxmem_bank.baseaddr = NULL;
#endif
#ifdef CATWEASEL
catweasel_mask = catweasel_start = 0;
#endif
- allocated_z3fastmem = 0;
- z3fastmem_mask = z3fastmem_start = 0;
- z3fastmem = 0;
- allocated_z3fastmem2 = 0;
- z3fastmem2_mask = z3fastmem2_start = 0;
- z3fastmem2 = 0;
- allocated_z3chipmem = 0;
- z3chipmem_mask = z3chipmem_start = 0;
- z3chipmem = 0;
+ z3fastmem_bank.allocated = 0;
+ z3fastmem_bank.mask = z3fastmem_bank.start = 0;
+ z3fastmem_bank.baseaddr = NULL;
+ z3fastmem2_bank.allocated = 0;
+ z3fastmem2_bank.mask = z3fastmem2_bank.start = 0;
+ z3fastmem2_bank.baseaddr = NULL;
+ z3chipmem_bank.allocated = 0;
+ z3chipmem_bank.mask = z3chipmem_bank.start = 0;
+ z3chipmem_bank.baseaddr = NULL;
}
#ifdef FILESYS
void expansion_cleanup (void)
{
- if (fastmemory)
- mapped_free (fastmemory);
- fastmemory = 0;
-
- if (z3fastmem)
- mapped_free (z3fastmem);
- z3fastmem = 0;
- if (z3fastmem2)
- mapped_free (z3fastmem2);
- z3fastmem2 = 0;
- if (z3chipmem)
- mapped_free (z3chipmem);
- z3chipmem = 0;
+ mapped_free (fastmem_bank.baseaddr);
+ fastmem_bank.baseaddr = NULL;
+ mapped_free (z3fastmem_bank.baseaddr);
+ z3fastmem_bank.baseaddr = NULL;
+ mapped_free (z3fastmem2_bank.baseaddr);
+ z3fastmem2_bank.baseaddr = NULL;
+ mapped_free (z3chipmem_bank.baseaddr);
+ z3chipmem_bank.baseaddr = NULL;
#ifdef PICASSO96
- if (gfxmemory)
- mapped_free (gfxmemory);
- gfxmemory = 0;
+ mapped_free (gfxmem_bank.baseaddr);
+ gfxmem_bank.baseaddr = NULL;
#endif
#ifdef FILESYS
- if (filesysory)
- mapped_free (filesysory);
- filesysory = 0;
+ mapped_free (filesysory);
+ filesysory = NULL;
#endif
#ifdef CATWEASEL
#endif
}
+static void clear_bank (addrbank *ab)
+{
+ if (!ab->baseaddr || !ab->allocated)
+ return;
+ memset (ab->baseaddr, 0, ab->allocated > 0x800000 ? 0x800000 : ab->allocated);
+}
+
void expansion_clear (void)
{
- if (fastmemory)
- memset (fastmemory, 0, allocated_fastmem);
- if (z3fastmem)
- memset (z3fastmem, 0, allocated_z3fastmem > 0x800000 ? 0x800000 : allocated_z3fastmem);
- if (z3fastmem2)
- memset (z3fastmem2, 0, allocated_z3fastmem2 > 0x800000 ? 0x800000 : allocated_z3fastmem2);
- if (z3chipmem)
- memset (z3chipmem, 0, allocated_z3chipmem > 0x800000 ? 0x800000 : allocated_z3chipmem);
- if (gfxmemory)
- memset (gfxmemory, 0, allocated_gfxmem);
+ clear_bank (&fastmem_bank);
+ clear_bank (&z3fastmem_bank);
+ clear_bank (&z3fastmem2_bank);
+ clear_bank (&z3chipmem_bank);
+ clear_bank (&gfxmem_bank);
}
#ifdef SAVESTATE
uae_u8 *save_fram (int *len)
{
- *len = allocated_fastmem;
- return fastmemory;
+ *len = fastmem_bank.allocated;
+ return fastmem_bank.baseaddr;
}
uae_u8 *save_zram (int *len, int num)
{
if (num < 0) {
- *len = allocated_z3chipmem;
- return z3chipmem;
+ *len = z3chipmem_bank.allocated;
+ return z3chipmem_bank.baseaddr;
}
- *len = num ? allocated_z3fastmem2 : allocated_z3fastmem;
- return num ? z3fastmem2 : z3fastmem;
+ *len = num ? z3fastmem2_bank.allocated : z3fastmem_bank.allocated;
+ return num ? z3fastmem2_bank.baseaddr : z3fastmem_bank.baseaddr;
}
uae_u8 *save_pram (int *len)
{
- *len = allocated_gfxmem;
- return gfxmemory;
+ *len = gfxmem_bank.allocated;
+ return gfxmem_bank.baseaddr;
}
void restore_fram (int len, size_t filepos)
uae_u8 *dst = t, *dstbak = t;
if (dstptr)
dst = dstbak = dstptr;
- save_u32 (fastmem_start);
- save_u32 (z3fastmem_start);
- save_u32 (gfxmem_start);
+ save_u32 (fastmem_bank.start);
+ save_u32 (z3fastmem_bank.start);
+ save_u32 (gfxmem_bank.start);
save_u32 (rtarea_base);
*len = 4 + 4 + 4 + 4;
return dstbak;
uae_u8 *restore_expansion (uae_u8 *src)
{
- fastmem_start = restore_u32 ();
- z3fastmem_start = restore_u32 ();
- gfxmem_start = restore_u32 ();
+ fastmem_bank.start = restore_u32 ();
+ z3fastmem_bank.start = restore_u32 ();
+ gfxmem_bank.start = restore_u32 ();
rtarea_base = restore_u32 ();
if (rtarea_base != 0 && rtarea_base != RTAREA_DEFAULT && rtarea_base != RTAREA_BACKUP)
rtarea_base = 0;
s = au ((char*)pp + 37);
pp += 128;
dostype = rl (pp + 64);
- size = ((uae_u64)rl (pp + 4)) * 4 * rl (pp + 12) * rl (pp + 20) * (rl (pp + 40) - rl (pp + 36) + 1);
+ spb = rl (pp + 16);
blocksize = rl (pp + 4) * 4;
surfaces = rl (pp + 12);
- spb = rl (pp + 16);
spt = rl (pp + 20);
reserved = rl (pp + 24);
lowcyl = rl (pp + 36);
highcyl = rl (pp + 40);
+ size = ((uae_u64)blocksize) * surfaces * spt * (highcyl - lowcyl + 1);
write_log (_T("Partition '%s' Dostype=%08X (%s) Flags: %08X\n"), s, dostype, dostypes (dostype), flags);
write_log (_T("BlockSize: %d, Surfaces: %d, SectorsPerBlock %d\n"),
#include "newcpu.h"
#include "picasso96.h"
#include "statusline.h"
+#include "rommgr.h"
+#include "zfile.h"
#include "gfxboard.h"
#include "qemuvga/qemuuaeglue.h"
#include "qemuvga/vga.h"
+#define GFXBOARD_AUTOCONFIG_SIZE 131072
+
#define BOARD_REGISTERS_SIZE 0x00010000
#define BOARD_MANUFACTURER_PICASSO 2167
#define PICASSOIV_REG 0x00600000
#define PICASSOIV_IO 0x00200000
#define PICASSOIV_VRAM 0x01000000
-
+#define PICASSOIV_ROM_OFFSET 0x0200
+#define PICASSOIV_FLASH_OFFSET 0x8000
+#define PICASSOIV_FLASH_BANK 0x8000
+#define PICASSOIV_MAX_FLASH (GFXBOARD_AUTOCONFIG_SIZE - 32768)
#define BOARD_MANUFACTURER_PICCOLO 2195
#define BOARD_MODEL_MEMORY_PICCOLO 5
#define BOARD_MODEL_MEMORY_SPECTRUM 1
#define BOARD_MODEL_REGISTERS_SPECTRUM 2
+extern addrbank gfxboard_bank_special;
+
struct gfxboard
{
TCHAR *name;
int banksize;
int chiptype;
bool z3;
- bool irq;
+ int irq;
bool swap;
};
-#define PICASSOIV 10
+#define PICASSOIV 11
static struct gfxboard boards[] =
{
{
_T("Picasso II"),
BOARD_MANUFACTURER_PICASSO, BOARD_MODEL_MEMORY_PICASSOII, BOARD_MODEL_REGISTERS_PICASSOII,
- 0x00020000, 0x00100000, 0x00200000, 0x00200000, CIRRUS_ID_CLGD5426, false, false, false
+ 0x00020000, 0x00100000, 0x00200000, 0x00200000, CIRRUS_ID_CLGD5426, false, 0, false
},
{
_T("Picasso II+"),
BOARD_MANUFACTURER_PICASSO, BOARD_MODEL_MEMORY_PICASSOII, BOARD_MODEL_REGISTERS_PICASSOII,
- 0x00100000, 0x00100000, 0x00200000, 0x00200000, CIRRUS_ID_CLGD5428, false, true, false
+ 0x00100000, 0x00100000, 0x00200000, 0x00200000, CIRRUS_ID_CLGD5428, false, 2, false
+ },
+ {
+ _T("Piccolo Zorro II"),
+ BOARD_MANUFACTURER_PICCOLO, BOARD_MODEL_MEMORY_PICCOLO, BOARD_MODEL_REGISTERS_PICCOLO,
+ 0x00000000, 0x00100000, 0x00200000, 0x00200000, CIRRUS_ID_CLGD5426, false, 6, true
},
{
- _T("Piccolo"),
+ _T("Piccolo Zorro III"),
BOARD_MANUFACTURER_PICCOLO, BOARD_MODEL_MEMORY_PICCOLO, BOARD_MODEL_REGISTERS_PICCOLO,
- 0x00000000, 0x00100000, 0x00200000, 0x00200000, CIRRUS_ID_CLGD5426, false, true, true
+ 0x00000000, 0x00100000, 0x00200000, 0x00200000, CIRRUS_ID_CLGD5426, true, 6, true
},
{
_T("Piccolo SD64 Zorro II"),
BOARD_MANUFACTURER_PICCOLO, BOARD_MODEL_MEMORY_PICCOLO64, BOARD_MODEL_REGISTERS_PICCOLO64,
- 0x00000000, 0x00200000, 0x00400000, 0x00200000, CIRRUS_ID_CLGD5434, false, true, true
+ 0x00000000, 0x00200000, 0x00400000, 0x00400000, CIRRUS_ID_CLGD5434, false, 6, true
},
{
_T("Piccolo SD64 Zorro III"),
BOARD_MANUFACTURER_PICCOLO, BOARD_MODEL_MEMORY_PICCOLO64, BOARD_MODEL_REGISTERS_PICCOLO64,
- 0x00000000, 0x00200000, 0x00400000, 0x01000000, CIRRUS_ID_CLGD5434, true, true, true
+ 0x00000000, 0x00200000, 0x00400000, 0x04000000, CIRRUS_ID_CLGD5434, true, 6, true
},
{
_T("Spectrum 28/24 Zorro II"),
BOARD_MANUFACTURER_SPECTRUM, BOARD_MODEL_MEMORY_SPECTRUM, BOARD_MODEL_REGISTERS_SPECTRUM,
- 0x00000000, 0x00100000, 0x00200000, 0x00200000, CIRRUS_ID_CLGD5428, false, true, true
+ 0x00000000, 0x00100000, 0x00200000, 0x00200000, CIRRUS_ID_CLGD5428, false, 6, true
},
{
_T("Spectrum 28/24 Zorro III"),
BOARD_MANUFACTURER_SPECTRUM, BOARD_MODEL_MEMORY_SPECTRUM, BOARD_MODEL_REGISTERS_SPECTRUM,
- 0x00000000, 0x00100000, 0x00200000, 0x01000000, CIRRUS_ID_CLGD5428, true, true, true
+ 0x00000000, 0x00100000, 0x00200000, 0x01000000, CIRRUS_ID_CLGD5428, true, 6, true
},
{
_T("Picasso IV Zorro II"),
BOARD_MANUFACTURER_PICASSO, BOARD_MODEL_MEMORY_PICASSOIV, BOARD_MODEL_REGISTERS_PICASSOIV,
- 0x00000000, 0x00400000, 0x00400000, 0x00400000, CIRRUS_ID_CLGD5446, false, true, true
+ 0x00000000, 0x00400000, 0x00400000, 0x00400000, CIRRUS_ID_CLGD5446, false, 6, true
},
{
// REG:00600000 IO:00200000 VRAM:01000000
_T("Picasso IV Zorro III"),
BOARD_MANUFACTURER_PICASSO, BOARD_MODEL_MEMORY_PICASSOIV, 0,
- 0x00000000, 0x00400000, 0x00400000, 0x04000000, CIRRUS_ID_CLGD5446, true, true, true
+ 0x00000000, 0x00400000, 0x00400000, 0x04000000, CIRRUS_ID_CLGD5446, true, 6, true
}
};
static struct gfxboard *board;
static uae_u32 memory_mask;
-static uae_u8 automemory[256];
+static uae_u8 *automemory;
+static int picassoiv_bank;
static CirrusVGAState vga;
static uae_u8 *vram;
static uae_u32 gfxboardmem_start;
static bool modechanged;
static uae_u8 *gfxboard_surface, *vram_address, *fakesurface_surface;
static bool gfxboard_vblank;
-static bool blit_cpu_to_vram;
+static bool gfxboard_intena;
+static bool vram_enabled, vram_offset_enabled;
+static hwaddr vram_offset[2];
-static const MemoryRegionOps *vgaio, *vgablitram;
-static const MemoryRegion *vgaioregion, *vgavramregion;
+static uae_u32 vgaioregionptr, vgavramregionptr, vgabank0regionptr, vgabank1regionptr;
+
+static const MemoryRegionOps *vgaio, *vgaram, *vgalowram;
+static MemoryRegion vgaioregion, vgavramregion;
static void init_board (void)
{
fakesurface_surface = xmalloc (uae_u8, 4 * 10000);
if (currprefs.rtgmem_type == PICASSOIV)
vramsize = 16 * 1024 * 1024;
+ vram_offset[0] = vram_offset[1] = 0;
+ vram_enabled = true;
+ vram_offset_enabled = false;
vram = mapped_malloc (vramsize, board->z3 ? _T("z3_gfx") : _T("z2_gfx"));
vga.vga.vram_size_mb = currprefs.rtgmem_size >> 20;
+ vgaioregion.opaque = &vgaioregionptr;
+ vgavramregion.opaque = &vgavramregionptr;
+ vga.vga.vram.opaque = &vgavramregionptr;
vga_common_init(&vga.vga);
cirrus_init_common(&vga, board->chiptype, 0, NULL, NULL);
picasso_allocatewritewatch (currprefs.rtgmem_size);
}
-static void gfxboard_setmode (void)
+static bool gfxboard_setmode (void)
{
int bpp, width, height;
bpp = vga.vga.get_bpp (&vga.vga);
vga.vga.get_resolution (&vga.vga, &width, &height);
-
+ if (bpp == 0)
+ bpp = 8;
+ if (width <= 16 || height <= 16)
+ return false;
picasso96_state.Width = width;
picasso96_state.Height = height;
picasso96_state.BytesPerPixel = bpp / 8;
write_log (_T("GFXBOARD %dx%dx%d\n"), width, height, bpp);
gfx_set_picasso_modeinfo (width, height, bpp, RGBFB_NONE);
fullrefresh = 2;
+ return true;
}
static bool gfxboard_checkchanged (void)
int bpp, width, height;
bpp = vga.vga.get_bpp (&vga.vga);
vga.vga.get_resolution (&vga.vga, &width, &height);
-
+ if (bpp == 0)
+ bpp = 8;
+ if (width <= 16 || height <= 16)
+ return false;
if (picasso96_state.Width != width ||
picasso96_state.Height != height ||
picasso96_state.BytesPerPixel != bpp / 8)
if (!configured_mem || !configured_regs)
return;
- if ((modechanged || gfxboard_checkchanged ()) && monswitch) {
- gfxboard_setmode ();
+ if (monswitch && (modechanged || gfxboard_checkchanged ())) {
+ if (!gfxboard_setmode ())
+ return;
init_hz_p96 ();
modechanged = false;
picasso_requested_on = true;
gfxboard_surface = NULL;
// Vertical Sync End Register, 0x10 = Clear Vertical Interrupt.
- if (board->irq && (vga.vga.cr[0x11] & 0x10)) {
+ if (board->irq && gfxboard_intena && (vga.vga.cr[0x11] & 0x10)) {
gfxboard_vblank = true;
- INTREQ (0x8000 | 0x0008);
+ if (board->irq == 2)
+ INTREQ (0x8000 | 0x0008);
+ else
+ INTREQ (0x8000 | 0x2000);
}
if (fullrefresh > 0)
picasso_invalidate (x, y, w, h);
}
+void memory_region_init_alias(MemoryRegion *mr,
+ const char *name,
+ MemoryRegion *orig,
+ hwaddr offset,
+ uint64_t size)
+{
+ if (!stricmp(name, "vga.bank0")) {
+ mr->opaque = &vgabank0regionptr;
+ } else if (!stricmp(name, "vga.bank1")) {
+ mr->opaque = &vgabank1regionptr;
+ }
+}
+static void remap_vram (hwaddr offset0, hwaddr offset1, bool enabled)
+{
+#ifdef JIT
+ if (currprefs.cachesize && (!currprefs.comptrustbyte || !currprefs.comptrustword || !currprefs.comptrustlong))
+ flush_icache (0, 3);
+#endif
+ vram_offset[0] = offset0;
+ vram_offset[1] = offset1;
+#if 0
+ if (vram_enabled != enabled)
+ write_log (_T("VRAM state=%d\n"), enabled);
+#endif
+ vram_enabled = enabled && (vga.vga.sr[0x07] & 0x01);
+#if 0
+ vram_enabled = false;
+#endif
+ // offset==0 and offset1==0x8000: linear vram mapping
+ vram_offset_enabled = offset0 != 0 || offset1 != 0x8000;
+#if 0
+ if (vram_offset_enabled)
+ write_log (_T("VRAM offset %08x and %08x\n"), offset0, offset1);
+#endif
+}
+
+void memory_region_set_alias_offset(MemoryRegion *mr,
+ hwaddr offset)
+{
+ if (mr->opaque == &vgabank0regionptr) {
+ if (offset != vram_offset[0]) {
+ //write_log (_T("vgavramregion0 %08x\n"), offset);
+ remap_vram (offset, vram_offset[1], vram_enabled);
+ }
+ } else if (mr->opaque == &vgabank1regionptr) {
+ if (offset != vram_offset[1]) {
+ //write_log (_T("vgavramregion1 %08x\n"), offset);
+ remap_vram (vram_offset[0], offset, vram_enabled);
+ }
+ } else if (mr->opaque == &vgaioregionptr) {
+ write_log (_T("vgaioregion %d\n"), offset);
+ } else {
+ write_log (_T("unknown region %d\n"), offset);
+ }
+
+}
+void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
+{
+ if (mr->opaque == &vgabank0regionptr || mr->opaque == &vgabank1regionptr) {
+ if (enabled != vram_enabled) {
+ //write_log (_T("enable vgavramregion %d\n"), enabled);
+ remap_vram (vram_offset[0], vram_offset[1], enabled);
+ }
+ } else if (mr->opaque == &vgaioregionptr) {
+ write_log (_T("enable vgaioregion %d\n"), enabled);
+ } else {
+ write_log (_T("enable unknown region %d\n"), enabled);
+ }
+}
void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
hwaddr size, unsigned client)
{
bool memory_region_get_dirty(MemoryRegion *mr, hwaddr addr,
hwaddr size, unsigned client)
{
- if (mr != vgavramregion)
+ if (mr->opaque != &vgavramregionptr)
return false;
if (fullrefresh)
return true;
- return picasso_is_vram_dirty (addr + p96ram_start, size);
+ return picasso_is_vram_dirty (addr + gfxmem_bank.start, size);
}
static QEMUResetHandler *reset_func;
if (!(vga.vga.cr[0x11] & 0x10))
gfxboard_vblank = false;
}
- if (vga.cirrus_srcptr != vga.cirrus_srcptr_end && !blit_cpu_to_vram) {
- blit_cpu_to_vram = true;
-#ifdef JIT
- if (currprefs.cachesize && (!currprefs.comptrustbyte || !currprefs.comptrustword || !currprefs.comptrustlong))
- flush_icache (0, 3);
-#endif
+ if (!(vga.vga.sr[0x07] & 0x01) && vram_enabled) {
+ remap_vram (vram_offset[0], vram_offset[1], false);
}
}
return v;
}
-static void checkblitend (void)
-{
- if (vga.cirrus_srcptr == vga.cirrus_srcptr_end) {
- blit_cpu_to_vram = false;
- }
-}
-
void *memory_region_get_ram_ptr(MemoryRegion *mr)
{
- if (mr == vgavramregion)
+ if (mr->opaque == &vgavramregionptr)
return vram;
return NULL;
}
uint64_t size)
{
if (!stricmp (name, "vga.vram")) {
- vgavramregion = mr;
+ vgavramregion.opaque = mr->opaque;
}
}
{
if (!stricmp (name, "cirrus-io")) {
vgaio = ops;
- vgaioregion = mr;
+ mr->opaque = vgaioregion.opaque;
+ } else if (!stricmp (name, "cirrus-linear-io")) {
+ vgaram = ops;
} else if (!stricmp (name, "cirrus-low-memory")) {
- vgablitram = ops;
+ vgalowram = ops;
}
}
return board->swap;
}
-static uae_u32 REGPARAM2 gfxboard_lget_mem (uaecptr addr)
+
+static uaecptr fixaddr (uaecptr addr, int mask)
{
-#if 0
+ if (vram_offset_enabled && vram_enabled) {
#ifdef JIT
- special_mem |= S_READ;
+ special_mem |= mask;
#endif
- return vgavram->read (&vga, addr, 4);
-#else
+ if (addr & 0x8000) {
+ addr += vram_offset[1] & ~0x8000;
+ } else {
+ addr += vram_offset[0];
+ }
+ }
+ addr &= memory_mask;
+ return addr;
+}
+
+static const MemoryRegionOps *getvgabank (uaecptr *paddr)
+{
+ uaecptr addr = *paddr;
+ addr &= memory_mask;
+ *paddr = addr;
+// if (!(vga.vga.sr[0x07] & 0x01))
+ if (addr < 0x10000)
+ return vgalowram;
+ return vgaram;
+}
+
+static uae_u32 REGPARAM2 gfxboard_lget_mem (uaecptr addr)
+{
uae_u8 *m;
addr -= gfxboardmem_start & memory_mask;
- addr &= memory_mask;
- m = vram + addr;
- return do_get_mem_long ((uae_u32 *)m);
+ if (!vram_enabled) {
+ const MemoryRegionOps *bank = getvgabank (&addr);
+ uae_u32 v;
+#ifdef JIT
+ special_mem |= S_READ;
#endif
+ addr &= memory_mask;
+ v = bank->read (&vga, addr + 0, 1) << 24;
+ v |= bank->read (&vga, addr + 1, 1) << 16;
+ v |= bank->read (&vga, addr + 2, 1) << 8;
+ v |= bank->read (&vga, addr + 3, 1) << 0;
+ return v;
+ } else {
+ addr = fixaddr (addr, S_READ);
+ m = vram + addr;
+ return do_get_mem_long ((uae_u32 *)m);
+ }
}
static uae_u32 REGPARAM2 gfxboard_wget_mem (uaecptr addr)
{
-#if 0
-#ifdef JIT
- special_mem |= S_READ;
-#endif
- return vgavram->read (&vga, addr, 2);
-#else
uae_u8 *m;
addr -= gfxboardmem_start & memory_mask;
- addr &= memory_mask;
- m = vram + addr;
- return do_get_mem_word ((uae_u16 *)m);
+ if (!vram_enabled) {
+ const MemoryRegionOps *bank = getvgabank (&addr);
+ uae_u32 v;
+#ifdef JIT
+ special_mem |= S_READ;;
#endif
+ v = bank->read (&vga, addr + 0, 1) << 8;
+ v |= bank->read (&vga, addr + 1, 1) << 0;
+ return v;
+ } else {
+ addr = fixaddr (addr, S_READ);
+ m = vram + addr;
+ return do_get_mem_word ((uae_u16 *)m);
+ }
}
static uae_u32 REGPARAM2 gfxboard_bget_mem (uaecptr addr)
{
-#if 0
-#ifdef JIT
- special_mem |= S_READ;
-#endif
- return vgavram->read (&vga, addr, 1);
-#else
addr -= gfxboardmem_start & memory_mask;
- addr &= memory_mask;
- return vram[addr];
+ if (!vram_enabled) {
+ const MemoryRegionOps *bank = getvgabank (&addr);
+ uae_u32 v;
+#ifdef JIT
+ special_mem |= S_READ;;
#endif
+ v = bank->read (&vga, addr + 0, 1);
+ return v;
+ } else {
+ addr = fixaddr (addr, S_READ);
+ return vram[addr];
+ }
}
+
+#define MEMDEBUG 0
+#define MEMDEBUGMASK 0xffffff
+#define MEMDEBUGTEST 0x1fc000
+
static void REGPARAM2 gfxboard_lput_mem (uaecptr addr, uae_u32 l)
{
- if (blit_cpu_to_vram) {
+ uae_u8 *m;
+ addr -= gfxboardmem_start & memory_mask;
+#if MEMDEBUG
+ if ((addr & MEMDEBUGMASK) >= MEMDEBUGTEST && l)
+ write_log (_T("%08X L %08X\n"), addr, l);
+#endif
+ if (!vram_enabled) {
+ const MemoryRegionOps *bank = getvgabank (&addr);
#ifdef JIT
special_mem |= S_WRITE;
#endif
- vgablitram->write (&vga, 0, l >> 24, 1);
- vgablitram->write (&vga, 0, l >> 16, 1);
- vgablitram->write (&vga, 0, l >> 8, 1);
- vgablitram->write (&vga, 0, l >> 0, 1);
- checkblitend ();
+ bank->write (&vga, addr + 0, l >> 24, 1);
+ bank->write (&vga, addr + 1, l >> 16, 1);
+ bank->write (&vga, addr + 2, l >> 8, 1);
+ bank->write (&vga, addr + 3, l >> 0, 1);
} else {
- uae_u8 *m;
- addr -= gfxboardmem_start & memory_mask;
- addr &= memory_mask;
+ addr = fixaddr (addr, S_WRITE);
m = vram + addr;
do_put_mem_long ((uae_u32 *) m, l);
}
}
static void REGPARAM2 gfxboard_wput_mem (uaecptr addr, uae_u32 w)
{
- if (blit_cpu_to_vram) {
+ uae_u8 *m;
+ addr -= gfxboardmem_start & memory_mask;
+#if MEMDEBUG
+ if ((addr & MEMDEBUGMASK) >= MEMDEBUGTEST && w)
+ write_log (_T("%08X W %04X\n"), addr, w & 0xffff);
+#endif
+ if (!vram_enabled) {
+ const MemoryRegionOps *bank = getvgabank (&addr);
#ifdef JIT
special_mem |= S_WRITE;
#endif
- vgablitram->write (&vga, 0, w >> 8, 1);
- vgablitram->write (&vga, 0, w >> 0, 1);
- checkblitend ();
+ bank->write (&vga, addr + 0, w >> 8, 1);
+ bank->write (&vga, addr + 1, w >> 0, 1);
} else {
- uae_u8 *m;
- addr -= gfxboardmem_start & memory_mask;
- addr &= memory_mask;
+ addr = fixaddr (addr, S_WRITE);
m = vram + addr;
do_put_mem_word ((uae_u16 *)m, w);
}
}
static void REGPARAM2 gfxboard_bput_mem (uaecptr addr, uae_u32 b)
{
- if (blit_cpu_to_vram) {
+ addr -= gfxboardmem_start & memory_mask;
+#if MEMDEBUG
+ if ((addr & MEMDEBUGMASK) >= MEMDEBUGTEST && b)
+ write_log (_T("%08X B %02X\n"), addr, b & 0xff);
+#endif
+ if (!vram_enabled) {
+ const MemoryRegionOps *bank = getvgabank (&addr);
#ifdef JIT
special_mem |= S_WRITE;
#endif
- vgablitram->write (&vga, 0, b, 1);
- checkblitend ();
+ bank->write (&vga, addr, b, 1);
} else {
- addr -= gfxboardmem_start & memory_mask;
- addr &= memory_mask;
+ addr = fixaddr (addr, S_WRITE);
vram[addr] = b;
}
}
special_mem |= S_READ;
#endif
addr &= 65535;
- if (addr < 0x40)
+ if (addr < GFXBOARD_AUTOCONFIG_SIZE)
v = automemory[addr];
return v;
}
b &= 0xffff;
addr &= 65535;
if (addr == 0x44) {
- put_word (regs.regs[11] + 0x20, p96ram_start >> 16);
- put_word (regs.regs[11] + 0x28, p96ram_start >> 16);
+ put_word (regs.regs[11] + 0x20, gfxmem_bank.start >> 16);
+ put_word (regs.regs[11] + 0x28, gfxmem_bank.start >> 16);
gfxboard_bank_memory.bget = gfxboard_bget_mem;
gfxboard_bank_memory.bput = gfxboard_bput_mem;
gfxboard_bank_memory.wput = gfxboard_wput_mem;
if (currprefs.rtgmem_type == PICASSOIV) {
- map_banks (&gfxboard_bank_memory, (p96ram_start + PICASSOIV_VRAM) >> 16, (board->banksize - PICASSOIV_VRAM) >> 16, currprefs.rtgmem_size);
- map_banks (&gfxboard_bank_registers, (p96ram_start + PICASSOIV_IO) >> 16, BOARD_REGISTERS_SIZE >> 16, BOARD_REGISTERS_SIZE);
+ map_banks (&gfxboard_bank_memory, (gfxmem_bank.start + PICASSOIV_VRAM) >> 16, (board->banksize - PICASSOIV_VRAM) >> 16, currprefs.rtgmem_size);
+ map_banks (&gfxboard_bank_registers, (gfxmem_bank.start + PICASSOIV_REG) >> 16, BOARD_REGISTERS_SIZE >> 16, BOARD_REGISTERS_SIZE);
+ map_banks (&gfxboard_bank_special, gfxmem_bank.start >> 16, (PICASSOIV_FLASH_BANK * 4) >> 16, PICASSOIV_FLASH_BANK * 4);
+ picassoiv_bank = 0;
+ init_board ();
} else {
- map_banks (&gfxboard_bank_memory, p96ram_start >> 16, board->banksize >> 16, currprefs.rtgmem_size);
+ map_banks (&gfxboard_bank_memory, gfxmem_bank.start >> 16, board->banksize >> 16, currprefs.rtgmem_size);
}
- write_log (_T("%s autoconfigured at 0x%04X0000\n"), gfxboard_bank_memory.name, p96ram_start >> 16);
- configured_mem = p96ram_start >> 16;
- gfxboardmem_start = p96ram_start;
+ write_log (_T("%s autoconfigured at 0x%04X0000\n"), gfxboard_bank_memory.name, gfxmem_bank.start >> 16);
+ configured_mem = gfxmem_bank.start >> 16;
+ gfxboardmem_start = gfxmem_bank.start;
expamem_next ();
return;
}
}
}
-static uaecptr mungeaddr (uaecptr addr)
+static uaecptr mungeaddr (uaecptr addr, bool write)
{
addr &= 65535;
- if (addr >= 0x2000)
+ if (addr >= 0x2000) {
+ if (addr == 0x46e8) {
+ // wakeup register
+ return 0;
+ }
+ write_log (_T("GFXBOARD: %d unknown IO address %x\n"), write, addr);
return 0;
- if (addr >= 0x1000)
+ }
+ if (addr >= 0x1000) {
+ if (board->manufacturer == BOARD_MANUFACTURER_PICASSO) {
+ if (addr == 0x1001) {
+ gfxboard_intena = true;
+ return 0;
+ }
+ if (addr == 0x1000) {
+ gfxboard_intena = false;
+ return 0;
+ }
+ }
+ if ((addr & 0xfff) < 0x3b0) {
+ write_log (_T("GFXBOARD: %d unknown IO address %x\n"), write, addr);
+ return 0;
+ }
addr++;
+ }
addr &= 0x0fff;
- if (addr < 0x3b0)
+ if (addr == 0x102) {
+ // POS102
return 0;
+ }
+ if (addr < 0x3b0) {
+ write_log (_T("GFXBOARD: %d unknown IO address %x\n"), write, addr);
+ return 0;
+ }
addr -= 0x3b0;
return addr;
}
#ifdef JIT
special_mem |= S_READ;
#endif
- addr = mungeaddr (addr);
+ addr = mungeaddr (addr, false);
if (addr)
v = vgaio->read (&vga, addr, 4);
return v;
#ifdef JIT
special_mem |= S_READ;
#endif
- addr = mungeaddr (addr);
+ addr = mungeaddr (addr, false);
if (addr) {
uae_u8 v1, v2;
v1 = vgaio->read (&vga, addr + 0, 1);
addr &= 65535;
if (addr >= 0x8000)
return 0;
- addr = mungeaddr (addr);
+ addr = mungeaddr (addr, false);
if (addr) {
v = vgaio->read (&vga, addr, 1);
v = bget_regtest (addr, v);
special_mem |= S_WRITE;
#endif
//write_log (_T("GFX LONG PUT IO %04X = %04X\n"), addr & 65535, l);
- addr = mungeaddr (addr);
+ addr = mungeaddr (addr, true);
if (addr)
vgaio->write (&vga, addr, l, 4);
}
special_mem |= S_WRITE;
#endif
//write_log (_T("GFX WORD PUT IO %04X = %04X\n"), addr & 65535, w & 0xffff);
- addr = mungeaddr (addr);
+ addr = mungeaddr (addr, true);
if (addr) {
vgaio->write (&vga, addr + 0, (w >> 8) & 0xff, 1);
bput_regtest (addr + 0, (w >> 8) & 0xff);
case BOARD_MANUFACTURER_PICCOLO:
case BOARD_MANUFACTURER_SPECTRUM:
monswitch = (b & 0x20) != 0;
+ gfxboard_intena = (b & 0x40) != 0;
break;
}
return;
}
- addr = mungeaddr (addr);
+ addr = mungeaddr (addr, true);
if (addr) {
vgaio->write (&vga, addr, b & 0xff, 1);
bput_regtest (addr, b);
special_mem |= S_READ;
#endif
addr &= 65535;
- if (addr < 0x40)
+ if (addr < GFXBOARD_AUTOCONFIG_SIZE)
v = automemory[addr];
return v;
}
fakesurface_surface = NULL;
configured_mem = 0;
configured_regs = 0;
- gfxboard_bank_registers.bget = gfxboard_bget_regs_autoconfig;
- gfxboard_bank_registers.bput = gfxboard_bput_regs_autoconfig;
- gfxboard_bank_memory.bget = gfxboard_bget_mem_autoconfig;
- gfxboard_bank_memory.bput = gfxboard_bput_mem_autoconfig;
+ monswitch = false;
+ oldswitch = false;
+ modechanged = false;
+ gfxboard_vblank = false;
+ gfxboard_intena = false;
if (board) {
if (board->z3)
gfxboard_bank_memory.wput = gfxboard_wput_mem_autoconfig;
addrbank gfxboard_bank_memory = {
gfxboard_lget_mem, gfxboard_wget_mem, gfxboard_bget_mem,
- gfxboard_lput_mem, gfxboard_wput_mem, gfxboard_bput_mem_autoconfig,
+ gfxboard_lput_mem, gfxboard_wput_mem, gfxboard_bput_mem,
gfxboard_xlate, gfxboard_check, NULL, NULL,
gfxboard_lget_mem, gfxboard_wget_mem, ABFLAG_RAM
};
addrbank gfxboard_bank_registers = {
gfxboard_lget_regs, gfxboard_wget_regs, gfxboard_bget_regs,
- gfxboard_lput_regs, gfxboard_wput_regs, gfxboard_bput_regs_autoconfig,
+ gfxboard_lput_regs, gfxboard_wput_regs, gfxboard_bput_regs,
default_xlate, default_check, NULL, NULL,
dummy_lgeti, dummy_wgeti, ABFLAG_IO | ABFLAG_SAFE
};
+
+
+static uae_u32 REGPARAM2 gfxboards_lget_regs (uaecptr addr)
+{
+ uae_u32 v = 0xffffffff;
+#ifdef JIT
+ special_mem |= S_READ;
+#endif
+ return v;
+}
+static uae_u32 REGPARAM2 gfxboards_wget_regs (uaecptr addr)
+{
+ uae_u16 v = 0xffff;
+#ifdef JIT
+ special_mem |= S_READ;
+#endif
+ return v;
+}
+static uae_u32 REGPARAM2 gfxboards_bget_regs (uaecptr addr)
+{
+ uae_u8 v = 0xff;
+#ifdef JIT
+ special_mem |= S_READ;
+#endif
+ addr &= 0x1ffff;
+ if (picassoiv_bank) {
+ write_log (_T("PicassoIV bget %08x\n"), addr);
+ return 0;
+ } else {
+ if (addr < PICASSOIV_FLASH_OFFSET) {
+ v = automemory[addr];
+ return v;
+ }
+ addr -= PICASSOIV_FLASH_OFFSET;
+ addr /= 2;
+ v = automemory[addr + PICASSOIV_FLASH_OFFSET];
+ return v;
+ }
+}
+static void REGPARAM2 gfxboards_lput_regs (uaecptr addr, uae_u32 l)
+{
+#ifdef JIT
+ special_mem |= S_WRITE;
+#endif
+}
+static void REGPARAM2 gfxboards_wput_regs (uaecptr addr, uae_u32 w)
+{
+#ifdef JIT
+ special_mem |= S_WRITE;
+#endif
+}
+static void REGPARAM2 gfxboards_bput_regs (uaecptr addr, uae_u32 b)
+{
+#ifdef JIT
+ special_mem |= S_WRITE;
+#endif
+ write_log (_T("PicassoIV bput %08x %02X\n"), addr, b & 0xff);
+ if ((addr & 65535) == 0)
+ picassoiv_bank = b;
+}
+addrbank gfxboard_bank_special = {
+ gfxboards_lget_regs, gfxboards_wget_regs, gfxboards_bget_regs,
+ gfxboards_lput_regs, gfxboards_wput_regs, gfxboards_bput_regs,
+ default_xlate, default_check, NULL, _T("Picasso IV Flash"),
+ dummy_lgeti, dummy_wgeti, ABFLAG_IO | ABFLAG_SAFE
+};
bool gfxboard_is_z3 (int type)
{
if (type == GFXBOARD_UAE_Z2)
return board->z3;
}
+bool gfxboard_need_byteswap (int type)
+{
+ if (type < 2)
+ return false;
+ board = &boards[type - 2];
+ return board->swap;
+}
+
int gfxboard_get_vram_min (int type)
{
if (type < 2)
return -1;
board = &boards[type - 2];
- return board->vrammax; //board->vrammin;
+ return board->vrammax;
+ //return board->vrammin;
}
int gfxboard_get_vram_max (int type)
return board->model_registers != 0;
}
+static void gfxboard_init (void)
+{
+ if (!automemory)
+ automemory = xmalloc (uae_u8, GFXBOARD_AUTOCONFIG_SIZE);
+ memset (automemory, 0xff, GFXBOARD_AUTOCONFIG_SIZE);
+}
+
void gfxboard_init_memory (void)
{
int vram = currprefs.rtgmem_size;
- uae_u8 flags;
- memset (automemory, 0xff, sizeof automemory);
+ uae_u8 z2_flags, z3_flags, type;
+
+ gfxboard_init ();
+
+ memset (automemory, 0xff, GFXBOARD_AUTOCONFIG_SIZE);
- flags = 0x05;
+ z2_flags = 0x05;
+ z3_flags = 0x06;
vram /= 0x00100000;
while (vram > 1) {
- flags++;
+ z2_flags++;
+ z3_flags++;
vram >>= 1;
}
if (board->z3) {
- ew (0x00, 0x00 | 0x08 | 0x80); // 16M Z3
- ew (0x08, flags | 0x10);
+ type = 0x00 | 0x08 | 0x80; // 16M Z3
+ ew (0x08, z3_flags | 0x10 | 0x20);
} else {
- ew (0x00, flags | 0x08 | 0xc0);
+ type = z2_flags | 0x08 | 0xc0;
}
ew (0x04, board->model_memory);
ew (0x10, board->manufacturer >> 8);
ew (0x20, ser >> 8); /* ser.no. Byte 2 */
ew (0x24, ser >> 0); /* ser.no. Byte 3 */
+ if (currprefs.rtgmem_type == PICASSOIV) {
+ struct zfile *rom;
+ rom = read_rom_name (_T("roms/picasso_iv_boot.rom"));
+ if (rom) {
+ uae_u8 b;
+ int size = 0;
+ int offset = PICASSOIV_ROM_OFFSET;
+ /* rom vector */
+ type |= 0x10;
+ ew (0x28, PICASSOIV_ROM_OFFSET >> 8);
+ ew (0x2c, PICASSOIV_ROM_OFFSET);
+ while (zfile_fread (&b, 1, 1, rom)) {
+ automemory[offset] = b;
+ automemory[offset + 2] = b << 4;
+ offset += 4;
+ size++;
+ }
+ zfile_fclose (rom);
+ write_log (_T("PICASSOIV: %d byte boot rom loaded\n"), size);
+ } else {
+ write_log (_T("PICASSOIV: boot rom not found\n"));
+ }
+ rom = read_rom_name (_T("roms/picasso_iv_flash_7.4.rom"));
+ if (rom) {
+ int size;
+ size = zfile_fread (&automemory[PICASSOIV_FLASH_OFFSET], 1, PICASSOIV_MAX_FLASH, rom);
+ zfile_fclose (rom);
+ write_log (_T("PICASSOIV: %d byte flash rom loaded\n"), size);
+ } else {
+ write_log (_T("PICASSOIV: flash rom not found\n"));
+ }
+ }
+
+ ew (0x00, type);
+
gfxboard_bank_memory.name = board->name;
gfxboard_bank_registers.name = board->name;
+
+ gfxboard_bank_memory.bget = gfxboard_bget_mem_autoconfig;
+ gfxboard_bank_memory.bput = gfxboard_bput_mem_autoconfig;
+
map_banks (&gfxboard_bank_memory, 0xe80000 >> 16, 0x10000 >> 16, 0x10000);
}
{
if (!board->model_registers)
return;
- memset (automemory, 0xff, sizeof automemory);
+ memset (automemory, 0xff, GFXBOARD_AUTOCONFIG_SIZE);
ew (0x00, 0xc0 | 0x01); // 64k Z2
ew (0x04, board->model_registers);
ew (0x10, board->manufacturer >> 8);
ew (0x20, ser >> 8); /* ser.no. Byte 2 */
ew (0x24, ser >> 0); /* ser.no. Byte 3 */
+ gfxboard_bank_registers.bget = gfxboard_bget_regs_autoconfig;
+ gfxboard_bank_registers.bput = gfxboard_bput_regs_autoconfig;
+
map_banks (&gfxboard_bank_registers, 0xe80000 >> 16, 0x10000 >> 16, 0x10000);
}
extern addrbank dmaca2091_bank;
+extern void init_scsi (void);
+extern void scsi_dmac_start_dma (void);
+extern void scsi_dmac_stop_dma (void);
+
extern void a2091_init (void);
extern void a2091_free (void);
extern void a2091_reset (void);
extern void AKIKO_hsync_handler (void);
extern void akiko_mute (int);
-extern uae_u8 *extendedkickmemory;
-
extern void rethink_akiko (void);
extern void align (int);
-extern volatile int uae_int_requested;
+extern volatile int uae_int_requested, uaenet_int_requested;
extern void set_uae_int_flag (void);
#define RTS 0x4e75
#define VBLANK_SPRITE_NTSC 20
#define VBLANK_HZ_PAL 50
#define VBLANK_HZ_NTSC 60
+#define VSYNC_ENDLINE_PAL 5
+#define VSYNC_ENDLINE_NTSC 6
#define EQU_ENDLINE_PAL 8
#define EQU_ENDLINE_NTSC 10
};
#define HFD_FLAGS_REALDRIVE 1
+#define HFD_FLAGS_REALDRIVEPARTITION 2
struct hd_hardfiledata {
struct hardfiledata hfd;
extern addrbank gfxboard_bank_memory;
-extern addrbank gfxboard_bank_memory_blit;
extern addrbank gfxboard_bank_registers;
extern void gfxboard_init_memory (void);
extern bool gfxboard_is_registers (int);
extern int gfxboard_get_vram_min (int);
extern int gfxboard_get_vram_max (int);
+extern bool gfxboard_need_byteswap (int type);
extern double gfxboard_get_vsync (void);
extern void gfxboard_refresh (void);
typedef int (REGPARAM3 *check_func)(uaecptr, uae_u32) REGPARAM;
extern uae_u8 *address_space, *good_address_map;
-extern uae_u8 *chipmemory;
-
-extern uae_u32 allocated_chipmem;
-extern uae_u32 allocated_fastmem;
-extern uae_u32 allocated_bogomem;
-extern uae_u32 allocated_gfxmem;
-extern uae_u32 allocated_z3fastmem, allocated_z3fastmem2, allocated_z3chipmem;
extern uae_u32 max_z3fastmem;
-extern uae_u32 allocated_a3000mem;
-extern uae_u32 allocated_cardmem;
extern uae_u32 wait_cpu_cycle_read (uaecptr addr, int mode);
extern void wait_cpu_cycle_write (uaecptr addr, int mode, uae_u32 v);
#undef DIRECT_MEMFUNCS_SUCCESSFUL
#include "machdep/maccess.h"
-#define chipmem_start 0x00000000
-#define bogomem_start 0x00C00000
-#define cardmem_start 0x00E00000
-#define kickmem_start 0x00F80000
-extern uaecptr z3fastmem_start, z3fastmem2_start, z3chipmem_start;
-extern uaecptr p96ram_start;
-extern uaecptr fastmem_start;
-extern uaecptr a3000lmem_start, a3000hmem_start;
+#define chipmem_start_addr 0x00000000
+#define bogomem_start_addr 0x00C00000
+#define cardmem_start_addr 0x00E00000
+#define kickmem_start_addr 0x00F80000
extern bool ersatzkickfile;
extern bool cloanto_rom, kickstart_rom;
/* for instruction opcode/operand fetches */
mem_get_func lgeti, wgeti;
int flags;
+ uae_u32 mask;
+ uae_u32 start;
+ uae_u32 allocated;
} addrbank;
#define CE_MEMBANK_FAST 0
#define CE_MEMBANK_FAST16BIT 3
extern uae_u8 ce_banktype[65536], ce_cachable[65536];
+#define MEMORY_LGET(name) \
+static uae_u32 REGPARAM3 name ## _lget (uaecptr) REGPARAM; \
+static uae_u32 REGPARAM2 name ## _lget (uaecptr addr) \
+{ \
+ uae_u8 *m; \
+ addr -= name ## _bank.start & name ## _bank.mask; \
+ addr &= name ## _bank.mask; \
+ m = name ## _bank.baseaddr + addr; \
+ return do_get_mem_long ((uae_u32 *)m); \
+}
+#define MEMORY_WGET(name) \
+static uae_u32 REGPARAM3 name ## _wget (uaecptr) REGPARAM; \
+static uae_u32 REGPARAM2 name ## _wget (uaecptr addr) \
+{ \
+ uae_u8 *m; \
+ addr -= name ## _bank.start & name ## _bank.mask; \
+ addr &= name ## _bank.mask; \
+ m = name ## _bank.baseaddr + addr; \
+ return do_get_mem_word ((uae_u16 *)m); \
+}
+#define MEMORY_BGET(name) \
+static uae_u32 REGPARAM3 name ## _bget (uaecptr) REGPARAM; \
+static uae_u32 REGPARAM2 name ## _bget (uaecptr addr) \
+{ \
+ addr -= name ## _bank.start & name ## _bank.mask; \
+ addr &= name ## _bank.mask; \
+ return name ## _bank.baseaddr[addr]; \
+}
+#define MEMORY_LPUT(name) \
+static void REGPARAM3 name ## _lput (uaecptr, uae_u32) REGPARAM; \
+static void REGPARAM2 name ## _lput (uaecptr addr, uae_u32 l) \
+{ \
+ uae_u8 *m; \
+ addr -= name ## _bank.start & name ## _bank.mask; \
+ addr &= name ## _bank.mask; \
+ m = name ## _bank.baseaddr + addr; \
+ do_put_mem_long ((uae_u32 *)m, l); \
+}
+#define MEMORY_WPUT(name) \
+static void REGPARAM3 name ## _wput (uaecptr, uae_u32) REGPARAM; \
+static void REGPARAM2 name ## _wput (uaecptr addr, uae_u32 w) \
+{ \
+ uae_u8 *m; \
+ addr -= name ## _bank.start & name ## _bank.mask; \
+ addr &= name ## _bank.mask; \
+ m = name ## _bank.baseaddr + addr; \
+ do_put_mem_word ((uae_u16 *)m, w); \
+}
+#define MEMORY_BPUT(name) \
+static void REGPARAM3 name ## _bput (uaecptr, uae_u32) REGPARAM; \
+static void REGPARAM2 name ## _bput (uaecptr addr, uae_u32 b) \
+{ \
+ addr -= name ## _bank.start & name ## _bank.mask; \
+ addr &= name ## _bank.mask; \
+ name ## _bank.baseaddr[addr] = b; \
+}
+#define MEMORY_CHECK(name) \
+static int REGPARAM3 name ## _check (uaecptr addr, uae_u32 size) REGPARAM; \
+static int REGPARAM2 name ## _check (uaecptr addr, uae_u32 size) \
+{ \
+ addr -= name ## _bank.start & name ## _bank.mask; \
+ addr &= name ## _bank.mask; \
+ return (addr + size) <= name ## _bank.allocated; \
+}
+#define MEMORY_XLATE(name) \
+static uae_u8 *REGPARAM3 name ## _xlate (uaecptr addr) REGPARAM; \
+static uae_u8 *REGPARAM2 name ## _xlate (uaecptr addr) \
+{ \
+ addr -= name ## _bank.start & name ## _bank.mask; \
+ addr &= name ## _bank.mask; \
+ return name ## _bank.baseaddr + addr; \
+}
+
+#define MEMORY_FUNCTIONS(name) \
+MEMORY_LGET(name); \
+MEMORY_WGET(name); \
+MEMORY_BGET(name); \
+MEMORY_LPUT(name); \
+MEMORY_WPUT(name); \
+MEMORY_BPUT(name); \
+MEMORY_CHECK(name); \
+MEMORY_XLATE(name);
+
extern uae_u8 *filesysory;
extern uae_u8 *rtarea;
extern addrbank mbres_bank;
extern addrbank akiko_bank;
extern addrbank cardmem_bank;
+extern addrbank bogomem_bank;
+extern addrbank z3fastmem_bank;
+extern addrbank z3fastmem2_bank;
+extern addrbank z3chipmem_bank;
+extern addrbank a3000lmem_bank;
+extern addrbank a3000hmem_bank;
+extern addrbank extendedkickmem_bank;
+extern addrbank extendedkickmem2_bank;
+extern addrbank custmem1_bank;
+extern addrbank custmem2_bank;
extern void rtarea_init (void);
extern void rtarea_init_mem (void);
extern void expamem_reset (void);
extern void expamem_next (void);
-extern uae_u32 gfxmem_start;
-extern uae_u8 *gfxmemory;
-extern uae_u32 gfxmem_mask;
extern uae_u16 last_custom_value1;
/* Default memory access functions */
extern void memory_init (void);
extern void memory_cleanup (void);
extern void map_banks (addrbank *bank, int first, int count, int realsize);
+extern void map_banks_quick (addrbank *bank, int first, int count, int realsize);
extern void map_banks_cond (addrbank *bank, int first, int count, int realsize);
extern void map_overlay (int chip);
extern void memory_hardreset (int);
extern uae_u32 REGPARAM3 chipmem_agnus_wget (uaecptr) REGPARAM;
extern void REGPARAM3 chipmem_agnus_wput (uaecptr, uae_u32) REGPARAM;
-extern uae_u32 chipmem_mask, kickmem_mask;
-extern uae_u8 *kickmemory;
extern addrbank dummy_bank;
/* 68020+ Chip RAM DMA contention emulation */
*target++=0x90;
}
-extern uae_u8* kickmemory;
STATIC_INLINE int isinrom(uae_u32 addr)
{
- return (addr>=(uae_u32)kickmemory &&
- addr<(uae_u32)kickmemory+8*65536);
+ return (addr>=(uae_u32)kickmem_bank.baseaddr &&
+ addr<(uae_u32)kickmem_bank.baseaddr+8*65536);
}
static void flush_all(void)
canbang = 0;
}
-uae_u32 allocated_chipmem;
-uae_u32 allocated_fastmem;
-uae_u32 allocated_bogomem;
-uae_u32 allocated_gfxmem;
-uae_u32 allocated_z3fastmem, allocated_z3fastmem2, allocated_z3chipmem;
-uae_u32 allocated_a3000lmem;
-uae_u32 allocated_a3000hmem;
-uae_u32 allocated_cardmem;
uae_u8 ce_banktype[65536];
uae_u8 ce_cachable[65536];
return 1;
}
-uae_u32 chipmem_mask, chipmem_full_mask, chipmem_full_size;
-uae_u32 kickmem_mask, extendedkickmem_mask, extendedkickmem2_mask, bogomem_mask;
-uae_u32 a3000lmem_mask, a3000hmem_mask, cardmem_mask;
-
static int illegal_count;
/* A dummy bank that only contains zeros */
/* Chip memory */
-uae_u8 *chipmemory;
+static uae_u32 chipmem_full_mask;
+static uae_u32 chipmem_full_size;
static int REGPARAM3 chipmem_check (uaecptr addr, uae_u32 size) REGPARAM;
static uae_u8 *REGPARAM3 chipmem_xlate (uaecptr addr) REGPARAM;
#ifdef JIT
special_mem |= S_READ;
#endif
- addr &= chipmem_mask;
- m = (uae_u32 *)(chipmemory + addr);
+ addr &= chipmem_bank.mask;
+ m = (uae_u32 *)(chipmem_bank.baseaddr + addr);
ce2_timeout ();
return do_get_mem_long (m);
}
#ifdef JIT
special_mem |= S_READ;
#endif
- addr &= chipmem_mask;
- m = (uae_u16 *)(chipmemory + addr);
+ addr &= chipmem_bank.mask;
+ m = (uae_u16 *)(chipmem_bank.baseaddr + addr);
ce2_timeout ();
v = do_get_mem_word (m);
return v;
#ifdef JIT
special_mem |= S_READ;
#endif
- addr &= chipmem_mask;
+ addr &= chipmem_bank.mask;
ce2_timeout ();
- return chipmemory[addr];
+ return chipmem_bank.baseaddr[addr];
}
static void REGPARAM2 chipmem_lput_ce2 (uaecptr addr, uae_u32 l)
#ifdef JIT
special_mem |= S_WRITE;
#endif
- addr &= chipmem_mask;
- m = (uae_u32 *)(chipmemory + addr);
+ addr &= chipmem_bank.mask;
+ m = (uae_u32 *)(chipmem_bank.baseaddr + addr);
ce2_timeout ();
do_put_mem_long (m, l);
}
#ifdef JIT
special_mem |= S_WRITE;
#endif
- addr &= chipmem_mask;
- m = (uae_u16 *)(chipmemory + addr);
+ addr &= chipmem_bank.mask;
+ m = (uae_u16 *)(chipmem_bank.baseaddr + addr);
ce2_timeout ();
do_put_mem_word (m, w);
}
#ifdef JIT
special_mem |= S_WRITE;
#endif
- addr &= chipmem_mask;
+ addr &= chipmem_bank.mask;
ce2_timeout ();
- chipmemory[addr] = b;
+ chipmem_bank.baseaddr[addr] = b;
}
#endif
{
uae_u32 *m;
- addr &= chipmem_mask;
- m = (uae_u32 *)(chipmemory + addr);
+ addr &= chipmem_bank.mask;
+ m = (uae_u32 *)(chipmem_bank.baseaddr + addr);
return do_get_mem_long (m);
}
{
uae_u16 *m, v;
- addr &= chipmem_mask;
- m = (uae_u16 *)(chipmemory + addr);
+ addr &= chipmem_bank.mask;
+ m = (uae_u16 *)(chipmem_bank.baseaddr + addr);
v = do_get_mem_word (m);
return v;
}
static uae_u32 REGPARAM2 chipmem_bget (uaecptr addr)
{
uae_u8 v;
- addr &= chipmem_mask;
- v = chipmemory[addr];
+ addr &= chipmem_bank.mask;
+ v = chipmem_bank.baseaddr[addr];
return v;
}
{
uae_u32 *m;
- addr &= chipmem_mask;
- m = (uae_u32 *)(chipmemory + addr);
+ addr &= chipmem_bank.mask;
+ m = (uae_u32 *)(chipmem_bank.baseaddr + addr);
do_put_mem_long (m, l);
}
{
uae_u16 *m;
- addr &= chipmem_mask;
- m = (uae_u16 *)(chipmemory + addr);
+ addr &= chipmem_bank.mask;
+ m = (uae_u16 *)(chipmem_bank.baseaddr + addr);
do_put_mem_word (m, w);
}
void REGPARAM2 chipmem_bput (uaecptr addr, uae_u32 b)
{
- addr &= chipmem_mask;
- chipmemory[addr] = b;
+ addr &= chipmem_bank.mask;
+ chipmem_bank.baseaddr[addr] = b;
}
/* cpu chipmem access inside agnus addressable ram but no ram available */
uae_u32 *m;
addr &= chipmem_full_mask;
- m = (uae_u32 *)(chipmemory + addr);
+ m = (uae_u32 *)(chipmem_bank.baseaddr + addr);
return do_get_mem_long (m);
}
uae_u16 *m;
addr &= chipmem_full_mask;
- m = (uae_u16 *)(chipmemory + addr);
+ m = (uae_u16 *)(chipmem_bank.baseaddr + addr);
return do_get_mem_word (m);
}
static uae_u32 REGPARAM2 chipmem_agnus_bget (uaecptr addr)
{
addr &= chipmem_full_mask;
- return chipmemory[addr];
+ return chipmem_bank.baseaddr[addr];
}
static void REGPARAM2 chipmem_agnus_lput (uaecptr addr, uae_u32 l)
addr &= chipmem_full_mask;
if (addr >= chipmem_full_size)
return;
- m = (uae_u32 *)(chipmemory + addr);
+ m = (uae_u32 *)(chipmem_bank.baseaddr + addr);
do_put_mem_long (m, l);
}
addr &= chipmem_full_mask;
if (addr >= chipmem_full_size)
return;
- m = (uae_u16 *)(chipmemory + addr);
+ m = (uae_u16 *)(chipmem_bank.baseaddr + addr);
do_put_mem_word (m, w);
}
addr &= chipmem_full_mask;
if (addr >= chipmem_full_size)
return;
- chipmemory[addr] = b;
+ chipmem_bank.baseaddr[addr] = b;
}
static int REGPARAM2 chipmem_check (uaecptr addr, uae_u32 size)
{
- addr &= chipmem_mask;
+ addr &= chipmem_bank.mask;
return (addr + size) <= chipmem_full_size;
}
static uae_u8 *REGPARAM2 chipmem_xlate (uaecptr addr)
{
- addr &= chipmem_mask;
- return chipmemory + addr;
+ addr &= chipmem_bank.mask;
+ return chipmem_bank.baseaddr + addr;
}
STATIC_INLINE void REGPARAM2 chipmem_lput_bigmem (uaecptr addr, uae_u32 v)
/* Slow memory */
-static uae_u8 *bogomemory;
-static int bogomemory_allocated;
-
-static uae_u32 REGPARAM3 bogomem_lget (uaecptr) REGPARAM;
-static uae_u32 REGPARAM3 bogomem_wget (uaecptr) REGPARAM;
-static uae_u32 REGPARAM3 bogomem_bget (uaecptr) REGPARAM;
-static void REGPARAM3 bogomem_lput (uaecptr, uae_u32) REGPARAM;
-static void REGPARAM3 bogomem_wput (uaecptr, uae_u32) REGPARAM;
-static void REGPARAM3 bogomem_bput (uaecptr, uae_u32) REGPARAM;
-static int REGPARAM3 bogomem_check (uaecptr addr, uae_u32 size) REGPARAM;
-static uae_u8 *REGPARAM3 bogomem_xlate (uaecptr addr) REGPARAM;
-
-static uae_u32 REGPARAM2 bogomem_lget (uaecptr addr)
-{
- uae_u32 *m;
- addr &= bogomem_mask;
- m = (uae_u32 *)(bogomemory + addr);
- return do_get_mem_long (m);
-}
-
-static uae_u32 REGPARAM2 bogomem_wget (uaecptr addr)
-{
- uae_u16 *m;
- addr &= bogomem_mask;
- m = (uae_u16 *)(bogomemory + addr);
- return do_get_mem_word (m);
-}
-
-static uae_u32 REGPARAM2 bogomem_bget (uaecptr addr)
-{
- addr &= bogomem_mask;
- return bogomemory[addr];
-}
-
-static void REGPARAM2 bogomem_lput (uaecptr addr, uae_u32 l)
-{
- uae_u32 *m;
- addr &= bogomem_mask;
- m = (uae_u32 *)(bogomemory + addr);
- do_put_mem_long (m, l);
-}
-
-static void REGPARAM2 bogomem_wput (uaecptr addr, uae_u32 w)
-{
- uae_u16 *m;
- addr &= bogomem_mask;
- m = (uae_u16 *)(bogomemory + addr);
- do_put_mem_word (m, w);
-}
-
-static void REGPARAM2 bogomem_bput (uaecptr addr, uae_u32 b)
-{
- addr &= bogomem_mask;
- bogomemory[addr] = b;
-}
-
-static int REGPARAM2 bogomem_check (uaecptr addr, uae_u32 size)
-{
- addr &= bogomem_mask;
- return (addr + size) <= allocated_bogomem;
-}
-
-static uae_u8 *REGPARAM2 bogomem_xlate (uaecptr addr)
-{
- addr &= bogomem_mask;
- return bogomemory + addr;
-}
+MEMORY_FUNCTIONS(bogomem);
/* CDTV expension memory card memory */
-uae_u8 *cardmemory;
-
-static uae_u32 REGPARAM3 cardmem_lget (uaecptr) REGPARAM;
-static uae_u32 REGPARAM3 cardmem_wget (uaecptr) REGPARAM;
-static uae_u32 REGPARAM3 cardmem_bget (uaecptr) REGPARAM;
-static void REGPARAM3 cardmem_lput (uaecptr, uae_u32) REGPARAM;
-static void REGPARAM3 cardmem_wput (uaecptr, uae_u32) REGPARAM;
-static void REGPARAM3 cardmem_bput (uaecptr, uae_u32) REGPARAM;
-static int REGPARAM3 cardmem_check (uaecptr addr, uae_u32 size) REGPARAM;
-static uae_u8 *REGPARAM3 cardmem_xlate (uaecptr addr) REGPARAM;
-
-static uae_u32 REGPARAM2 cardmem_lget (uaecptr addr)
-{
- uae_u32 *m;
- addr &= cardmem_mask;
- m = (uae_u32 *)(cardmemory + addr);
- return do_get_mem_long (m);
-}
-
-static uae_u32 REGPARAM2 cardmem_wget (uaecptr addr)
-{
- uae_u16 *m;
- addr &= cardmem_mask;
- m = (uae_u16 *)(cardmemory + addr);
- return do_get_mem_word (m);
-}
-
-static uae_u32 REGPARAM2 cardmem_bget (uaecptr addr)
-{
- addr &= cardmem_mask;
- return cardmemory[addr];
-}
-
-static void REGPARAM2 cardmem_lput (uaecptr addr, uae_u32 l)
-{
- uae_u32 *m;
- addr &= cardmem_mask;
- m = (uae_u32 *)(cardmemory + addr);
- do_put_mem_long (m, l);
-}
-
-static void REGPARAM2 cardmem_wput (uaecptr addr, uae_u32 w)
-{
- uae_u16 *m;
- addr &= cardmem_mask;
- m = (uae_u16 *)(cardmemory + addr);
- do_put_mem_word (m, w);
-}
-
-static void REGPARAM2 cardmem_bput (uaecptr addr, uae_u32 b)
-{
- addr &= cardmem_mask;
- cardmemory[addr] = b;
-}
-
-static int REGPARAM2 cardmem_check (uaecptr addr, uae_u32 size)
-{
- addr &= cardmem_mask;
- return (addr + size) <= allocated_cardmem;
-}
-
-static uae_u8 *REGPARAM2 cardmem_xlate (uaecptr addr)
-{
- addr &= cardmem_mask;
- return cardmemory + addr;
-}
+MEMORY_FUNCTIONS(cardmem);
/* A3000 motherboard fast memory */
-static uae_u8 *a3000lmemory, *a3000hmemory;
-uae_u32 a3000lmem_start, a3000hmem_start;
-
-static uae_u32 REGPARAM3 a3000lmem_lget (uaecptr) REGPARAM;
-static uae_u32 REGPARAM3 a3000lmem_wget (uaecptr) REGPARAM;
-static uae_u32 REGPARAM3 a3000lmem_bget (uaecptr) REGPARAM;
-static void REGPARAM3 a3000lmem_lput (uaecptr, uae_u32) REGPARAM;
-static void REGPARAM3 a3000lmem_wput (uaecptr, uae_u32) REGPARAM;
-static void REGPARAM3 a3000lmem_bput (uaecptr, uae_u32) REGPARAM;
-static int REGPARAM3 a3000lmem_check (uaecptr addr, uae_u32 size) REGPARAM;
-static uae_u8 *REGPARAM3 a3000lmem_xlate (uaecptr addr) REGPARAM;
-
-static uae_u32 REGPARAM2 a3000lmem_lget (uaecptr addr)
-{
- uae_u32 *m;
- addr &= a3000lmem_mask;
- m = (uae_u32 *)(a3000lmemory + addr);
- return do_get_mem_long (m);
-}
-
-static uae_u32 REGPARAM2 a3000lmem_wget (uaecptr addr)
-{
- uae_u16 *m;
- addr &= a3000lmem_mask;
- m = (uae_u16 *)(a3000lmemory + addr);
- return do_get_mem_word (m);
-}
-
-static uae_u32 REGPARAM2 a3000lmem_bget (uaecptr addr)
-{
- addr &= a3000lmem_mask;
- return a3000lmemory[addr];
-}
-
-static void REGPARAM2 a3000lmem_lput (uaecptr addr, uae_u32 l)
-{
- uae_u32 *m;
- addr &= a3000lmem_mask;
- m = (uae_u32 *)(a3000lmemory + addr);
- do_put_mem_long (m, l);
-}
-
-static void REGPARAM2 a3000lmem_wput (uaecptr addr, uae_u32 w)
-{
- uae_u16 *m;
- addr &= a3000lmem_mask;
- m = (uae_u16 *)(a3000lmemory + addr);
- do_put_mem_word (m, w);
-}
-
-static void REGPARAM2 a3000lmem_bput (uaecptr addr, uae_u32 b)
-{
- addr &= a3000lmem_mask;
- a3000lmemory[addr] = b;
-}
-
-static int REGPARAM2 a3000lmem_check (uaecptr addr, uae_u32 size)
-{
- addr &= a3000lmem_mask;
- return (addr + size) <= allocated_a3000lmem;
-}
-
-static uae_u8 *REGPARAM2 a3000lmem_xlate (uaecptr addr)
-{
- addr &= a3000lmem_mask;
- return a3000lmemory + addr;
-}
-
-static uae_u32 REGPARAM3 a3000hmem_lget (uaecptr) REGPARAM;
-static uae_u32 REGPARAM3 a3000hmem_wget (uaecptr) REGPARAM;
-static uae_u32 REGPARAM3 a3000hmem_bget (uaecptr) REGPARAM;
-static void REGPARAM3 a3000hmem_lput (uaecptr, uae_u32) REGPARAM;
-static void REGPARAM3 a3000hmem_wput (uaecptr, uae_u32) REGPARAM;
-static void REGPARAM3 a3000hmem_bput (uaecptr, uae_u32) REGPARAM;
-static int REGPARAM3 a3000hmem_check (uaecptr addr, uae_u32 size) REGPARAM;
-static uae_u8 *REGPARAM3 a3000hmem_xlate (uaecptr addr) REGPARAM;
-
-static uae_u32 REGPARAM2 a3000hmem_lget (uaecptr addr)
-{
- uae_u32 *m;
- addr &= a3000hmem_mask;
- m = (uae_u32 *)(a3000hmemory + addr);
- return do_get_mem_long (m);
-}
-
-static uae_u32 REGPARAM2 a3000hmem_wget (uaecptr addr)
-{
- uae_u16 *m;
- addr &= a3000hmem_mask;
- m = (uae_u16 *)(a3000hmemory + addr);
- return do_get_mem_word (m);
-}
-
-static uae_u32 REGPARAM2 a3000hmem_bget (uaecptr addr)
-{
- addr &= a3000hmem_mask;
- return a3000hmemory[addr];
-}
-
-static void REGPARAM2 a3000hmem_lput (uaecptr addr, uae_u32 l)
-{
- uae_u32 *m;
- addr &= a3000hmem_mask;
- m = (uae_u32 *)(a3000hmemory + addr);
- do_put_mem_long (m, l);
-}
-
-static void REGPARAM2 a3000hmem_wput (uaecptr addr, uae_u32 w)
-{
- uae_u16 *m;
- addr &= a3000hmem_mask;
- m = (uae_u16 *)(a3000hmemory + addr);
- do_put_mem_word (m, w);
-}
-static void REGPARAM2 a3000hmem_bput (uaecptr addr, uae_u32 b)
-{
- addr &= a3000hmem_mask;
- a3000hmemory[addr] = b;
-}
-
-static int REGPARAM2 a3000hmem_check (uaecptr addr, uae_u32 size)
-{
- addr &= a3000hmem_mask;
- return (addr + size) <= allocated_a3000hmem;
-}
-
-static uae_u8 *REGPARAM2 a3000hmem_xlate (uaecptr addr)
-{
- addr &= a3000hmem_mask;
- return a3000hmemory + addr;
-}
+MEMORY_FUNCTIONS(a3000lmem);
+MEMORY_FUNCTIONS(a3000hmem);
/* Kick memory */
-uae_u8 *kickmemory;
uae_u16 kickstart_version;
-static int kickmem_size;
/*
* A1000 kickstart RAM handling
protect_roms (false);
if (mode == 0) {
a1000_kickstart_mode = 0;
- memcpy (kickmemory, kickmemory + 262144, 262144);
- kickstart_version = (kickmemory[262144 + 12] << 8) | kickmemory[262144 + 13];
+ memcpy (kickmem_bank.baseaddr, kickmem_bank.baseaddr + 262144, 262144);
+ kickstart_version = (kickmem_bank.baseaddr[262144 + 12] << 8) | kickmem_bank.baseaddr[262144 + 13];
} else {
a1000_kickstart_mode = 1;
- memcpy (kickmemory, a1000_bootrom, 262144);
+ memcpy (kickmem_bank.baseaddr, a1000_bootrom, 262144);
kickstart_version = 0;
}
if (kickstart_version == 0xffff)
a1000_handle_kickstart (1);
}
-static uae_u32 REGPARAM3 kickmem_lget (uaecptr) REGPARAM;
-static uae_u32 REGPARAM3 kickmem_wget (uaecptr) REGPARAM;
-static uae_u32 REGPARAM3 kickmem_bget (uaecptr) REGPARAM;
static void REGPARAM3 kickmem_lput (uaecptr, uae_u32) REGPARAM;
static void REGPARAM3 kickmem_wput (uaecptr, uae_u32) REGPARAM;
static void REGPARAM3 kickmem_bput (uaecptr, uae_u32) REGPARAM;
-static int REGPARAM3 kickmem_check (uaecptr addr, uae_u32 size) REGPARAM;
-static uae_u8 *REGPARAM3 kickmem_xlate (uaecptr addr) REGPARAM;
-
-static uae_u32 REGPARAM2 kickmem_lget (uaecptr addr)
-{
- uae_u32 *m;
- addr &= kickmem_mask;
- m = (uae_u32 *)(kickmemory + addr);
- return do_get_mem_long (m);
-}
-static uae_u32 REGPARAM2 kickmem_wget (uaecptr addr)
-{
- uae_u16 *m;
- addr &= kickmem_mask;
- m = (uae_u16 *)(kickmemory + addr);
- return do_get_mem_word (m);
-}
-
-static uae_u32 REGPARAM2 kickmem_bget (uaecptr addr)
-{
- addr &= kickmem_mask;
- return kickmemory[addr];
-}
+MEMORY_BGET(kickmem);
+MEMORY_WGET(kickmem);
+MEMORY_LGET(kickmem);
+MEMORY_CHECK(kickmem);
+MEMORY_XLATE(kickmem);
static void REGPARAM2 kickmem_lput (uaecptr addr, uae_u32 b)
{
special_mem |= S_WRITE;
#endif
if (currprefs.rom_readwrite && rom_write_enabled) {
- addr &= kickmem_mask;
- m = (uae_u32 *)(kickmemory + addr);
+ addr &= kickmem_bank.mask;
+ m = (uae_u32 *)(kickmem_bank.baseaddr + addr);
do_put_mem_long (m, b);
if (addr == 524288-4) {
rom_write_enabled = false;
}
} else if (a1000_kickstart_mode) {
if (addr >= 0xfc0000) {
- addr &= kickmem_mask;
- m = (uae_u32 *)(kickmemory + addr);
+ addr &= kickmem_bank.mask;
+ m = (uae_u32 *)(kickmem_bank.baseaddr + addr);
do_put_mem_long (m, b);
return;
} else
special_mem |= S_WRITE;
#endif
if (currprefs.rom_readwrite && rom_write_enabled) {
- addr &= kickmem_mask;
- m = (uae_u16 *)(kickmemory + addr);
+ addr &= kickmem_bank.mask;
+ m = (uae_u16 *)(kickmem_bank.baseaddr + addr);
do_put_mem_word (m, b);
} else if (a1000_kickstart_mode) {
if (addr >= 0xfc0000) {
- addr &= kickmem_mask;
- m = (uae_u16 *)(kickmemory + addr);
+ addr &= kickmem_bank.mask;
+ m = (uae_u16 *)(kickmem_bank.baseaddr + addr);
do_put_mem_word (m, b);
return;
} else
special_mem |= S_WRITE;
#endif
if (currprefs.rom_readwrite && rom_write_enabled) {
- addr &= kickmem_mask;
- kickmemory[addr] = b;
+ addr &= kickmem_bank.mask;
+ kickmem_bank.baseaddr[addr] = b;
} else if (a1000_kickstart_mode) {
if (addr >= 0xfc0000) {
- addr &= kickmem_mask;
- kickmemory[addr] = b;
+ addr &= kickmem_bank.mask;
+ kickmem_bank.baseaddr[addr] = b;
return;
} else
a1000_handle_kickstart (0);
#ifdef JIT
special_mem |= S_WRITE;
#endif
- addr &= kickmem_mask;
- m = (uae_u32 *)(kickmemory + addr);
+ addr &= kickmem_bank.mask;
+ m = (uae_u32 *)(kickmem_bank.baseaddr + addr);
do_put_mem_long (m, l);
}
#ifdef JIT
special_mem |= S_WRITE;
#endif
- addr &= kickmem_mask;
- m = (uae_u16 *)(kickmemory + addr);
+ addr &= kickmem_bank.mask;
+ m = (uae_u16 *)(kickmem_bank.baseaddr + addr);
do_put_mem_word (m, w);
}
#ifdef JIT
special_mem |= S_WRITE;
#endif
- addr &= kickmem_mask;
- kickmemory[addr] = b;
-}
-
-static int REGPARAM2 kickmem_check (uaecptr addr, uae_u32 size)
-{
- addr &= kickmem_mask;
- return (addr + size) <= kickmem_size;
-}
-
-static uae_u8 *REGPARAM2 kickmem_xlate (uaecptr addr)
-{
- addr &= kickmem_mask;
- return kickmemory + addr;
+ addr &= kickmem_bank.mask;
+ kickmem_bank.baseaddr[addr] = b;
}
/* CD32/CDTV extended kick memory */
-uae_u8 *extendedkickmemory, *extendedkickmemory2;
-static int extendedkickmem_size, extendedkickmem2_size;
-static uae_u32 extendedkickmem_start, extendedkickmem2_start;
static int extendedkickmem_type;
#define EXTENDED_ROM_CD32 1
#define EXTENDED_ROM_KS 3
#define EXTENDED_ROM_ARCADIA 4
-static uae_u32 REGPARAM3 extendedkickmem_lget (uaecptr) REGPARAM;
-static uae_u32 REGPARAM3 extendedkickmem_wget (uaecptr) REGPARAM;
-static uae_u32 REGPARAM3 extendedkickmem_bget (uaecptr) REGPARAM;
static void REGPARAM3 extendedkickmem_lput (uaecptr, uae_u32) REGPARAM;
static void REGPARAM3 extendedkickmem_wput (uaecptr, uae_u32) REGPARAM;
static void REGPARAM3 extendedkickmem_bput (uaecptr, uae_u32) REGPARAM;
-static int REGPARAM3 extendedkickmem_check (uaecptr addr, uae_u32 size) REGPARAM;
-static uae_u8 *REGPARAM3 extendedkickmem_xlate (uaecptr addr) REGPARAM;
-static uae_u32 REGPARAM2 extendedkickmem_lget (uaecptr addr)
-{
- uae_u32 *m;
- addr -= extendedkickmem_start & extendedkickmem_mask;
- addr &= extendedkickmem_mask;
- m = (uae_u32 *)(extendedkickmemory + addr);
- return do_get_mem_long (m);
-}
-static uae_u32 REGPARAM2 extendedkickmem_wget (uaecptr addr)
-{
- uae_u16 *m;
- addr -= extendedkickmem_start & extendedkickmem_mask;
- addr &= extendedkickmem_mask;
- m = (uae_u16 *)(extendedkickmemory + addr);
- return do_get_mem_word (m);
-}
-static uae_u32 REGPARAM2 extendedkickmem_bget (uaecptr addr)
-{
- addr -= extendedkickmem_start & extendedkickmem_mask;
- addr &= extendedkickmem_mask;
- return extendedkickmemory[addr];
-}
+
+MEMORY_BGET(extendedkickmem);
+MEMORY_WGET(extendedkickmem);
+MEMORY_LGET(extendedkickmem);
+MEMORY_CHECK(extendedkickmem);
+MEMORY_XLATE(extendedkickmem);
+
static void REGPARAM2 extendedkickmem_lput (uaecptr addr, uae_u32 b)
{
#ifdef JIT
if (currprefs.illegal_mem)
write_log (_T("Illegal extendedkickmem lput at %08x\n"), addr);
}
-static int REGPARAM2 extendedkickmem_check (uaecptr addr, uae_u32 size)
-{
- addr -= extendedkickmem_start & extendedkickmem_mask;
- addr &= extendedkickmem_mask;
- return (addr + size) <= extendedkickmem_size;
-}
-static uae_u8 *REGPARAM2 extendedkickmem_xlate (uaecptr addr)
-{
- addr -= extendedkickmem_start & extendedkickmem_mask;
- addr &= extendedkickmem_mask;
- return extendedkickmemory + addr;
-}
-static uae_u32 REGPARAM3 extendedkickmem2_lget (uaecptr) REGPARAM;
-static uae_u32 REGPARAM3 extendedkickmem2_wget (uaecptr) REGPARAM;
-static uae_u32 REGPARAM3 extendedkickmem2_bget (uaecptr) REGPARAM;
+
static void REGPARAM3 extendedkickmem2_lput (uaecptr, uae_u32) REGPARAM;
static void REGPARAM3 extendedkickmem2_wput (uaecptr, uae_u32) REGPARAM;
static void REGPARAM3 extendedkickmem2_bput (uaecptr, uae_u32) REGPARAM;
-static int REGPARAM3 extendedkickmem2_check (uaecptr addr, uae_u32 size) REGPARAM;
-static uae_u8 *REGPARAM3 extendedkickmem2_xlate (uaecptr addr) REGPARAM;
-static uae_u32 REGPARAM2 extendedkickmem2_lget (uaecptr addr)
-{
- uae_u32 *m;
- addr -= extendedkickmem2_start & extendedkickmem2_mask;
- addr &= extendedkickmem2_mask;
- m = (uae_u32 *)(extendedkickmemory2 + addr);
- return do_get_mem_long (m);
-}
-static uae_u32 REGPARAM2 extendedkickmem2_wget (uaecptr addr)
-{
- uae_u16 *m;
- addr -= extendedkickmem2_start & extendedkickmem2_mask;
- addr &= extendedkickmem2_mask;
- m = (uae_u16 *)(extendedkickmemory2 + addr);
- return do_get_mem_word (m);
-}
-static uae_u32 REGPARAM2 extendedkickmem2_bget (uaecptr addr)
-{
- addr -= extendedkickmem2_start & extendedkickmem2_mask;
- addr &= extendedkickmem2_mask;
- return extendedkickmemory2[addr];
-}
+
+MEMORY_BGET(extendedkickmem2);
+MEMORY_WGET(extendedkickmem2);
+MEMORY_LGET(extendedkickmem2);
+MEMORY_CHECK(extendedkickmem2);
+MEMORY_XLATE(extendedkickmem2);
+
static void REGPARAM2 extendedkickmem2_lput (uaecptr addr, uae_u32 b)
{
#ifdef JIT
if (currprefs.illegal_mem)
write_log (_T("Illegal extendedkickmem2 lput at %08x\n"), addr);
}
-static int REGPARAM2 extendedkickmem2_check (uaecptr addr, uae_u32 size)
-{
- addr -= extendedkickmem2_start & extendedkickmem2_mask;
- addr &= extendedkickmem2_mask;
- return (addr + size) <= extendedkickmem2_size;
-}
-static uae_u8 *REGPARAM2 extendedkickmem2_xlate (uaecptr addr)
-{
- addr -= extendedkickmem2_start & extendedkickmem2_mask;
- addr &= extendedkickmem2_mask;
- return extendedkickmemory2 + addr;
-}
-
/* Default memory access functions */
extendedkickmem2_lget, extendedkickmem2_wget, ABFLAG_ROM
};
-
-static uae_u32 allocated_custmem1, allocated_custmem2;
-static uae_u32 custmem1_mask, custmem2_mask;
-static uae_u8 *custmem1, *custmem2;
-
-static uae_u32 REGPARAM3 custmem1_lget (uaecptr) REGPARAM;
-static uae_u32 REGPARAM3 custmem1_wget (uaecptr) REGPARAM;
-static uae_u32 REGPARAM3 custmem1_bget (uaecptr) REGPARAM;
-static void REGPARAM3 custmem1_lput (uaecptr, uae_u32) REGPARAM;
-static void REGPARAM3 custmem1_wput (uaecptr, uae_u32) REGPARAM;
-static void REGPARAM3 custmem1_bput (uaecptr, uae_u32) REGPARAM;
-static int REGPARAM3 custmem1_check (uaecptr addr, uae_u32 size) REGPARAM;
-static uae_u8 *REGPARAM3 custmem1_xlate (uaecptr addr) REGPARAM;
-
-static uae_u32 REGPARAM2 custmem1_lget (uaecptr addr)
-{
- uae_u8 *m;
- addr -= currprefs.custom_memory_addrs[0] & custmem1_mask;
- addr &= custmem1_mask;
- m = custmem1 + addr;
- return do_get_mem_long ((uae_u32 *)m);
-}
-static uae_u32 REGPARAM2 custmem1_wget (uaecptr addr)
-{
- uae_u8 *m;
- addr -= currprefs.custom_memory_addrs[0] & custmem1_mask;
- addr &= custmem1_mask;
- m = custmem1 + addr;
- return do_get_mem_word ((uae_u16 *)m);
-}
-static uae_u32 REGPARAM2 custmem1_bget (uaecptr addr)
-{
- addr -= currprefs.custom_memory_addrs[0] & custmem1_mask;
- addr &= custmem1_mask;
- return custmem1[addr];
-}
-static void REGPARAM2 custmem1_lput (uaecptr addr, uae_u32 l)
-{
- uae_u8 *m;
- addr -= currprefs.custom_memory_addrs[0] & custmem1_mask;
- addr &= custmem1_mask;
- m = custmem1 + addr;
- do_put_mem_long ((uae_u32 *)m, l);
-}
-static void REGPARAM2 custmem1_wput (uaecptr addr, uae_u32 w)
-{
- uae_u8 *m;
- addr -= currprefs.custom_memory_addrs[0] & custmem1_mask;
- addr &= custmem1_mask;
- m = custmem1 + addr;
- do_put_mem_word ((uae_u16 *)m, w);
-}
-static void REGPARAM2 custmem1_bput (uaecptr addr, uae_u32 b)
-{
- addr -= currprefs.custom_memory_addrs[0] & custmem1_mask;
- addr &= custmem1_mask;
- custmem1[addr] = b;
-}
-static int REGPARAM2 custmem1_check (uaecptr addr, uae_u32 size)
-{
- addr -= currprefs.custom_memory_addrs[0] & custmem1_mask;
- addr &= custmem1_mask;
- return (addr + size) <= currprefs.custom_memory_sizes[0];
-}
-static uae_u8 *REGPARAM2 custmem1_xlate (uaecptr addr)
-{
- addr -= currprefs.custom_memory_addrs[0] & custmem1_mask;
- addr &= custmem1_mask;
- return custmem1 + addr;
-}
-
-static uae_u32 REGPARAM3 custmem2_lget (uaecptr) REGPARAM;
-static uae_u32 REGPARAM3 custmem2_wget (uaecptr) REGPARAM;
-static uae_u32 REGPARAM3 custmem2_bget (uaecptr) REGPARAM;
-static void REGPARAM3 custmem2_lput (uaecptr, uae_u32) REGPARAM;
-static void REGPARAM3 custmem2_wput (uaecptr, uae_u32) REGPARAM;
-static void REGPARAM3 custmem2_bput (uaecptr, uae_u32) REGPARAM;
-static int REGPARAM3 custmem2_check (uaecptr addr, uae_u32 size) REGPARAM;
-static uae_u8 *REGPARAM3 custmem2_xlate (uaecptr addr) REGPARAM;
-
-static uae_u32 REGPARAM2 custmem2_lget (uaecptr addr)
-{
- uae_u8 *m;
- addr -= currprefs.custom_memory_addrs[1] & custmem2_mask;
- addr &= custmem2_mask;
- m = custmem2 + addr;
- return do_get_mem_long ((uae_u32 *)m);
-}
-static uae_u32 REGPARAM2 custmem2_wget (uaecptr addr)
-{
- uae_u8 *m;
- addr -= currprefs.custom_memory_addrs[1] & custmem2_mask;
- addr &= custmem2_mask;
- m = custmem2 + addr;
- return do_get_mem_word ((uae_u16 *)m);
-}
-static uae_u32 REGPARAM2 custmem2_bget (uaecptr addr)
-{
- addr -= currprefs.custom_memory_addrs[1] & custmem2_mask;
- addr &= custmem2_mask;
- return custmem2[addr];
-}
-static void REGPARAM2 custmem2_lput (uaecptr addr, uae_u32 l)
-{
- uae_u8 *m;
- addr -= currprefs.custom_memory_addrs[1] & custmem2_mask;
- addr &= custmem2_mask;
- m = custmem2 + addr;
- do_put_mem_long ((uae_u32 *)m, l);
-}
-static void REGPARAM2 custmem2_wput (uaecptr addr, uae_u32 w)
-{
- uae_u8 *m;
- addr -= currprefs.custom_memory_addrs[1] & custmem2_mask;
- addr &= custmem2_mask;
- m = custmem2 + addr;
- do_put_mem_word ((uae_u16 *)m, w);
-}
-static void REGPARAM2 custmem2_bput (uaecptr addr, uae_u32 b)
-{
- addr -= currprefs.custom_memory_addrs[1] & custmem2_mask;
- addr &= custmem2_mask;
- custmem2[addr] = b;
-}
-static int REGPARAM2 custmem2_check (uaecptr addr, uae_u32 size)
-{
- addr -= currprefs.custom_memory_addrs[1] & custmem2_mask;
- addr &= custmem2_mask;
- return (addr + size) <= currprefs.custom_memory_sizes[1];
-}
-static uae_u8 *REGPARAM2 custmem2_xlate (uaecptr addr)
-{
- addr -= currprefs.custom_memory_addrs[1] & custmem2_mask;
- addr &= custmem2_mask;
- return custmem2 + addr;
-}
+MEMORY_FUNCTIONS(custmem1);
+MEMORY_FUNCTIONS(custmem2);
addrbank custmem1_bank = {
custmem1_lget, custmem1_wget, custmem1_bget,
protect_roms (false);
if (map) {
- uae_u8 *fkickmemory = a3000lmemory + allocated_a3000lmem - fkickmem_size;
+ uae_u8 *fkickmemory = a3000lmem_bank.baseaddr + a3000lmem_bank.allocated - fkickmem_size;
if (fkickmemory[2] == 0x4e && fkickmemory[3] == 0xf9 && fkickmemory[4] == 0x00) {
if (!kickstore)
kickstore = xmalloc (uae_u8, fkickmem_size);
- memcpy (kickstore, kickmemory, fkickmem_size);
+ memcpy (kickstore, kickmem_bank.baseaddr, fkickmem_size);
if (fkickmemory[5] == 0xfc) {
- memcpy (kickmemory, fkickmemory, fkickmem_size / 2);
- memcpy (kickmemory + fkickmem_size / 2, fkickmemory, fkickmem_size / 2);
- extendedkickmem_size = 65536;
- extendedkickmem_mask = extendedkickmem_size - 1;
- extendedkickmemory = mapped_malloc (extendedkickmem_size, _T("rom_f0"));
- extendedkickmem_bank.baseaddr = extendedkickmemory;
- memcpy (extendedkickmemory, fkickmemory + fkickmem_size / 2, 65536);
+ memcpy (kickmem_bank.baseaddr, fkickmemory, fkickmem_size / 2);
+ memcpy (kickmem_bank.baseaddr + fkickmem_size / 2, fkickmemory, fkickmem_size / 2);
+ extendedkickmem_bank.allocated = 65536;
+ extendedkickmem_bank.mask = extendedkickmem_bank.allocated - 1;
+ extendedkickmem_bank.baseaddr = mapped_malloc (extendedkickmem_bank.allocated, _T("rom_f0"));
+ memcpy (extendedkickmem_bank.baseaddr, fkickmemory + fkickmem_size / 2, 65536);
map_banks (&extendedkickmem_bank, 0xf0, 1, 1);
a3000_f0 = 1;
} else {
- memcpy (kickmemory, fkickmemory, fkickmem_size);
+ memcpy (kickmem_bank.baseaddr, fkickmemory, fkickmem_size);
}
}
} else {
if (a3000_f0) {
map_banks (&dummy_bank, 0xf0, 1, 1);
- mapped_free (extendedkickmemory);
- extendedkickmemory = NULL;
+ mapped_free (extendedkickmem_bank.baseaddr);
+ extendedkickmem_bank.baseaddr = NULL;
a3000_f0 = 0;
}
if (kickstore)
- memcpy (kickmemory, kickstore, fkickmem_size);
+ memcpy (kickmem_bank.baseaddr, kickstore, fkickmem_size);
xfree (kickstore);
kickstore = NULL;
}
int off = 0;
a1000_bootrom = xcalloc (uae_u8, 262144);
while (off + i < 262144) {
- memcpy (a1000_bootrom + off, kickmemory, i);
+ memcpy (a1000_bootrom + off, kickmem_bank.baseaddr, i);
off += i;
}
- memset (kickmemory, 0, kickmem_size);
+ memset (kickmem_bank.baseaddr, 0, kickmem_bank.allocated);
a1000_handle_kickstart (1);
dochecksum = 0;
i = 524288;
}
zfile_fseek (f, 0, SEEK_END);
size = zfile_ftell (f);
- extendedkickmem_size = 524288;
+ extendedkickmem_bank.allocated = 524288;
off = 0;
if (type == 0) {
if (currprefs.cs_cd32cd) {
zfile_fseek (f, off, SEEK_SET);
switch (extendedkickmem_type) {
case EXTENDED_ROM_CDTV:
- extendedkickmemory = mapped_malloc (extendedkickmem_size, _T("rom_f0"));
- extendedkickmem_bank.baseaddr = extendedkickmemory;
- extendedkickmem_start = 0xf00000;
+ extendedkickmem_bank.baseaddr = mapped_malloc (extendedkickmem_bank.allocated, _T("rom_f0"));
+ extendedkickmem_bank.start = 0xf00000;
break;
case EXTENDED_ROM_CD32:
- extendedkickmemory = mapped_malloc (extendedkickmem_size, _T("rom_e0"));
- extendedkickmem_bank.baseaddr = extendedkickmemory;
- extendedkickmem_start = 0xe00000;
+ extendedkickmem_bank.baseaddr = mapped_malloc (extendedkickmem_bank.allocated, _T("rom_e0"));
+ extendedkickmem_bank.start = 0xe00000;
break;
}
- if (extendedkickmemory) {
- read_kickstart (f, extendedkickmemory, extendedkickmem_size, 0, 1);
- extendedkickmem_mask = extendedkickmem_size - 1;
+ if (extendedkickmem_bank.baseaddr) {
+ read_kickstart (f, extendedkickmem_bank.baseaddr, extendedkickmem_bank.allocated, 0, 1);
+ extendedkickmem_bank.mask = extendedkickmem_bank.allocated - 1;
ret = true;
}
}
static void patch_kick (void)
{
int patched = 0;
- if (kickmem_size >= 524288 && currprefs.kickshifter)
- patched += patch_shapeshifter (kickmemory);
- patched += patch_residents (kickmemory, kickmem_size);
- if (extendedkickmemory) {
- patched += patch_residents (extendedkickmemory, extendedkickmem_size);
+ if (kickmem_bank.allocated >= 524288 && currprefs.kickshifter)
+ patched += patch_shapeshifter (kickmem_bank.baseaddr);
+ patched += patch_residents (kickmem_bank.baseaddr, kickmem_bank.allocated);
+ if (extendedkickmem_bank.baseaddr) {
+ patched += patch_residents (extendedkickmem_bank.baseaddr, extendedkickmem_bank.allocated);
if (patched)
- kickstart_fix_checksum (extendedkickmemory, extendedkickmem_size);
+ kickstart_fix_checksum (extendedkickmem_bank.baseaddr, extendedkickmem_bank.allocated);
}
if (patched)
- kickstart_fix_checksum (kickmemory, kickmem_size);
+ kickstart_fix_checksum (kickmem_bank.baseaddr, kickmem_bank.allocated);
}
extern unsigned char arosrom[];
f = zfile_gunzip (f);
if (!f)
return false;
- kickmem_mask = 0x80000 - 1;
- kickmem_size = 0x80000;
- extendedkickmem_size = 0x80000;
+ kickmem_bank.mask = 0x80000 - 1;
+ kickmem_bank.allocated = 0x80000;
+ extendedkickmem_bank.allocated = 0x80000;
extendedkickmem_type = EXTENDED_ROM_KS;
- extendedkickmemory = mapped_malloc (extendedkickmem_size, _T("rom_e0"));
- extendedkickmem_bank.baseaddr = extendedkickmemory;
- read_kickstart (f, extendedkickmemory, extendedkickmem_size, 0, 1);
- extendedkickmem_mask = extendedkickmem_size - 1;
- read_kickstart (f, kickmemory, 0x80000, 1, 0);
+ extendedkickmem_bank.baseaddr = mapped_malloc (extendedkickmem_bank.allocated, _T("rom_e0"));
+ read_kickstart (f, extendedkickmem_bank.baseaddr, extendedkickmem_bank.allocated, 0, 1);
+ extendedkickmem_bank.mask = extendedkickmem_bank.allocated - 1;
+ read_kickstart (f, extendedkickmem_bank.baseaddr, 0x80000, 1, 0);
zfile_fclose (f);
seriallog = -1;
return true;
extpos = 0;
zfile_fseek (f, kspos, SEEK_SET);
}
- size = read_kickstart (f, kickmemory, maxsize, 1, 0);
+ size = read_kickstart (f, kickmem_bank.baseaddr, maxsize, 1, 0);
if (size == 0)
goto err;
- kickmem_mask = size - 1;
- kickmem_size = size;
+ kickmem_bank.mask = size - 1;
+ kickmem_bank.allocated = size;
if (filesize >= 524288 * 2 && !extendedkickmem_type) {
- extendedkickmem_size = 0x80000;
+ extendedkickmem_bank.allocated = 0x80000;
if (currprefs.cs_cdtvcd || currprefs.cs_cdtvram) {
extendedkickmem_type = EXTENDED_ROM_CDTV;
- extendedkickmem_size *= 2;
- extendedkickmemory = mapped_malloc (extendedkickmem_size, _T("rom_f0"));
- extendedkickmem_start = 0xf00000;
+ extendedkickmem_bank.allocated *= 2;
+ extendedkickmem_bank.baseaddr = mapped_malloc (extendedkickmem_bank.allocated, _T("rom_f0"));
+ extendedkickmem_bank.start = 0xf00000;
} else {
extendedkickmem_type = EXTENDED_ROM_KS;
- extendedkickmemory = mapped_malloc (extendedkickmem_size, _T("rom_e0"));
- extendedkickmem_start = 0xe00000;
+ extendedkickmem_bank.baseaddr = mapped_malloc (extendedkickmem_bank.allocated, _T("rom_e0"));
+ extendedkickmem_bank.start = 0xe00000;
}
- extendedkickmem_bank.baseaddr = extendedkickmemory;
zfile_fseek (f, extpos, SEEK_SET);
- read_kickstart (f, extendedkickmemory, extendedkickmem_size, 0, 1);
- extendedkickmem_mask = extendedkickmem_size - 1;
+ read_kickstart (f, extendedkickmem_bank.baseaddr, extendedkickmem_bank.allocated, 0, 1);
+ extendedkickmem_bank.mask = extendedkickmem_bank.allocated - 1;
}
if (filesize > 524288 * 2) {
- extendedkickmem2_size = 524288 * 2;
- extendedkickmemory2 = mapped_malloc (extendedkickmem2_size, _T("rom_a8"));
- extendedkickmem2_bank.baseaddr = extendedkickmemory2;
+ extendedkickmem2_bank.allocated = 524288 * 2;
+ extendedkickmem2_bank.baseaddr = mapped_malloc (extendedkickmem2_bank.allocated, _T("rom_a8"));
zfile_fseek (f, extpos + 524288, SEEK_SET);
- read_kickstart (f, extendedkickmemory2, 524288, 0, 1);
+ read_kickstart (f, extendedkickmem2_bank.baseaddr, 524288, 0, 1);
zfile_fseek (f, extpos + 524288 * 2, SEEK_SET);
- read_kickstart (f, extendedkickmemory2 + 524288, 524288, 0, 1);
- extendedkickmem2_mask = extendedkickmem2_size - 1;
- extendedkickmem2_start = 0xa80000;
+ read_kickstart (f, extendedkickmem2_bank.baseaddr + 524288, 524288, 0, 1);
+ extendedkickmem2_bank.mask = extendedkickmem2_bank.allocated - 1;
+ extendedkickmem2_bank.start = 0xa80000;
}
}
chk_sum:
#endif
- kickstart_version = (kickmemory[12] << 8) | kickmemory[13];
+ kickstart_version = (kickmem_bank.baseaddr[12] << 8) | kickmem_bank.baseaddr[13];
if (kickstart_version == 0xffff)
kickstart_version = 0;
zfile_fclose (f);
/* emulate 0.5M+0.5M with 1M Agnus chip ram aliasing */
if (currprefs.chipmem_size == 0x80000 && currprefs.bogomem_size >= 0x80000 &&
(currprefs.chipset_mask & CSMASK_ECS_AGNUS) && !(currprefs.chipset_mask & CSMASK_AGA) && currprefs.cpu_model < 68020) {
- if ((allocated_chipmem != currprefs.chipmem_size || allocated_bogomem != currprefs.bogomem_size)) {
+ if ((chipmem_bank.allocated != currprefs.chipmem_size || bogomem_bank.allocated != currprefs.bogomem_size)) {
int memsize1, memsize2;
- if (chipmemory)
- mapped_free (chipmemory);
- chipmemory = 0;
- if (bogomemory_allocated)
- mapped_free (bogomemory);
- bogomemory = 0;
- bogomemory_allocated = 0;
- memsize1 = allocated_chipmem = currprefs.chipmem_size;
- memsize2 = allocated_bogomem = currprefs.bogomem_size;
- chipmem_mask = allocated_chipmem - 1;
- chipmem_full_mask = allocated_chipmem * 2 - 1;
+ mapped_free (chipmem_bank.baseaddr);
+ chipmem_bank.baseaddr = 0;
+ mapped_free (bogomem_bank.baseaddr);
+ bogomem_bank.baseaddr = NULL;
+ bogomem_bank.allocated = 0;
+ memsize1 = chipmem_bank.allocated = currprefs.chipmem_size;
+ memsize2 = bogomem_bank.allocated = currprefs.bogomem_size;
+ chipmem_bank.mask = chipmem_bank.allocated - 1;
+ chipmem_bank.start = chipmem_start_addr;
+ chipmem_full_mask = bogomem_bank.allocated * 2 - 1;
chipmem_full_size = 0x80000 * 2;
- chipmemory = mapped_malloc (memsize1 + memsize2, _T("chip"));
- bogomemory = chipmemory + memsize1;
- bogomem_mask = allocated_bogomem - 1;
- if (chipmemory == 0) {
+ chipmem_bank.baseaddr = mapped_malloc (memsize1 + memsize2, _T("chip"));
+ bogomem_bank.baseaddr = chipmem_bank.baseaddr + memsize1;
+ bogomem_bank.mask = bogomem_bank.allocated - 1;
+ bogomem_bank.start = bogomem_start_addr;
+ if (chipmem_bank.baseaddr == 0) {
write_log (_T("Fatal error: out of memory for chipmem.\n"));
- allocated_chipmem = 0;
+ chipmem_bank.allocated = 0;
} else {
need_hardreset = true;
}
bogomem_aliasing = true;
}
- if (allocated_chipmem != currprefs.chipmem_size) {
+ if (chipmem_bank.allocated != currprefs.chipmem_size) {
int memsize;
- if (chipmemory)
- mapped_free (chipmemory);
- chipmemory = 0;
+ mapped_free (chipmem_bank.baseaddr);
+ chipmem_bank.baseaddr = 0;
if (currprefs.chipmem_size > 2 * 1024 * 1024)
free_fastmemory ();
- memsize = allocated_chipmem = chipmem_full_size = currprefs.chipmem_size;
- chipmem_full_mask = chipmem_mask = allocated_chipmem - 1;
+ memsize = chipmem_bank.allocated = chipmem_full_size = currprefs.chipmem_size;
+ chipmem_full_mask = chipmem_bank.mask = chipmem_bank.allocated - 1;
+ chipmem_bank.start = chipmem_start_addr;
if (!currprefs.cachesize && memsize < 0x100000)
memsize = 0x100000;
if (memsize > 0x100000 && memsize < 0x200000)
memsize = 0x200000;
- chipmemory = mapped_malloc (memsize, _T("chip"));
- if (chipmemory == 0) {
+ chipmem_bank.baseaddr = mapped_malloc (memsize, _T("chip"));
+ if (chipmem_bank.baseaddr == 0) {
write_log (_T("Fatal error: out of memory for chipmem.\n"));
- allocated_chipmem = 0;
+ chipmem_bank.allocated = 0;
} else {
need_hardreset = true;
- if (memsize > allocated_chipmem)
- memset (chipmemory + allocated_chipmem, 0xff, memsize - allocated_chipmem);
+ if (memsize > chipmem_bank.allocated)
+ memset (chipmem_bank.baseaddr + chipmem_bank.allocated, 0xff, memsize - chipmem_bank.allocated);
}
currprefs.chipset_mask = changed_prefs.chipset_mask;
- chipmem_full_mask = allocated_chipmem - 1;
+ chipmem_full_mask = chipmem_bank.allocated - 1;
if ((currprefs.chipset_mask & CSMASK_ECS_AGNUS) && !currprefs.cachesize) {
- if (allocated_chipmem < 0x100000)
+ if (chipmem_bank.allocated < 0x100000)
chipmem_full_mask = 0x100000 - 1;
- if (allocated_chipmem > 0x100000 && allocated_chipmem < 0x200000)
- chipmem_full_mask = chipmem_mask = 0x200000 - 1;
+ if (chipmem_bank.allocated > 0x100000 && chipmem_bank.allocated < 0x200000)
+ chipmem_full_mask = chipmem_bank.mask = 0x200000 - 1;
}
}
- if (allocated_bogomem != currprefs.bogomem_size) {
- if (!(allocated_bogomem == 0x200000 && currprefs.bogomem_size == 0x180000)) {
- if (bogomemory_allocated)
- mapped_free (bogomemory);
- bogomemory = 0;
- bogomemory_allocated = 0;
+ if (bogomem_bank.allocated != currprefs.bogomem_size) {
+ if (!(bogomem_bank.allocated == 0x200000 && currprefs.bogomem_size == 0x180000)) {
+ mapped_free (bogomem_bank.baseaddr);
+ bogomem_bank.baseaddr = NULL;
+ bogomem_bank.allocated = 0;
- allocated_bogomem = currprefs.bogomem_size;
- if (allocated_bogomem >= 0x180000)
- allocated_bogomem = 0x200000;
- bogomem_mask = allocated_bogomem - 1;
+ bogomem_bank.allocated = currprefs.bogomem_size;
+ if (bogomem_bank.allocated >= 0x180000)
+ bogomem_bank.allocated = 0x200000;
+ bogomem_bank.mask = bogomem_bank.allocated - 1;
+ bogomem_bank.start = bogomem_start_addr;
- if (allocated_bogomem) {
- bogomemory = mapped_malloc (allocated_bogomem, _T("bogo"));
- if (bogomemory == 0) {
+ if (bogomem_bank.allocated) {
+ bogomem_bank.baseaddr = mapped_malloc (bogomem_bank.allocated, _T("bogo"));
+ if (bogomem_bank.baseaddr == 0) {
write_log (_T("Out of memory for bogomem.\n"));
- allocated_bogomem = 0;
+ bogomem_bank.allocated = 0;
}
}
need_hardreset = true;
}
}
- if (allocated_a3000lmem != currprefs.mbresmem_low_size) {
- if (a3000lmemory)
- mapped_free (a3000lmemory);
- a3000lmemory = 0;
-
- allocated_a3000lmem = currprefs.mbresmem_low_size;
- a3000lmem_mask = allocated_a3000lmem - 1;
- a3000lmem_start = 0x08000000 - allocated_a3000lmem;
- if (allocated_a3000lmem) {
- a3000lmemory = mapped_malloc (allocated_a3000lmem, _T("ramsey_low"));
- if (a3000lmemory == 0) {
+ if (a3000lmem_bank.allocated != currprefs.mbresmem_low_size) {
+ mapped_free (a3000lmem_bank.baseaddr);
+ a3000lmem_bank.baseaddr = NULL;
+
+ a3000lmem_bank.allocated = currprefs.mbresmem_low_size;
+ a3000lmem_bank.mask = a3000lmem_bank.allocated - 1;
+ a3000lmem_bank.start = 0x08000000 - a3000lmem_bank.allocated;
+ if (a3000lmem_bank.allocated) {
+ a3000lmem_bank.baseaddr = mapped_malloc (a3000lmem_bank.allocated, _T("ramsey_low"));
+ if (a3000lmem_bank.baseaddr == 0) {
write_log (_T("Out of memory for a3000lowmem.\n"));
- allocated_a3000lmem = 0;
+ a3000lmem_bank.allocated = 0;
}
}
need_hardreset = true;
}
- if (allocated_a3000hmem != currprefs.mbresmem_high_size) {
- if (a3000hmemory)
- mapped_free (a3000hmemory);
- a3000hmemory = 0;
-
- allocated_a3000hmem = currprefs.mbresmem_high_size;
- a3000hmem_mask = allocated_a3000hmem - 1;
- a3000hmem_start = 0x08000000;
- if (allocated_a3000hmem) {
- a3000hmemory = mapped_malloc (allocated_a3000hmem, _T("ramsey_high"));
- if (a3000hmemory == 0) {
+ if (a3000hmem_bank.allocated != currprefs.mbresmem_high_size) {
+ mapped_free (a3000hmem_bank.baseaddr);
+ a3000hmem_bank.baseaddr = NULL;
+
+ a3000hmem_bank.allocated = currprefs.mbresmem_high_size;
+ a3000hmem_bank.mask = a3000hmem_bank.allocated - 1;
+ a3000hmem_bank.start = 0x08000000;
+ if (a3000hmem_bank.allocated) {
+ a3000hmem_bank.baseaddr = mapped_malloc (a3000hmem_bank.allocated, _T("ramsey_high"));
+ if (a3000hmem_bank.baseaddr == 0) {
write_log (_T("Out of memory for a3000highmem.\n"));
- allocated_a3000hmem = 0;
+ a3000hmem_bank.allocated = 0;
}
}
need_hardreset = true;
}
#ifdef CDTV
- if (allocated_cardmem != currprefs.cs_cdtvcard * 1024) {
- if (cardmemory)
- mapped_free (cardmemory);
- cardmemory = 0;
-
- allocated_cardmem = currprefs.cs_cdtvcard * 1024;
- cardmem_mask = allocated_cardmem - 1;
- if (allocated_cardmem) {
- cardmemory = mapped_malloc (allocated_cardmem, _T("rom_e0"));
- if (cardmemory == 0) {
+ if (cardmem_bank.allocated != currprefs.cs_cdtvcard * 1024) {
+ mapped_free (cardmem_bank.baseaddr);
+ cardmem_bank.baseaddr = NULL;
+
+ cardmem_bank.allocated = currprefs.cs_cdtvcard * 1024;
+ cardmem_bank.mask = cardmem_bank.allocated - 1;
+ cardmem_bank.start = 0xe00000;
+ if (cardmem_bank.allocated) {
+ cardmem_bank.baseaddr = mapped_malloc (cardmem_bank.allocated, _T("rom_e0"));
+ if (cardmem_bank.baseaddr == 0) {
write_log (_T("Out of memory for cardmem.\n"));
- allocated_cardmem = 0;
+ cardmem_bank.allocated = 0;
}
}
- cdtv_loadcardmem(cardmemory, allocated_cardmem);
- }
-#endif
- if (allocated_custmem1 != currprefs.custom_memory_sizes[0]) {
- if (custmem1)
- mapped_free (custmem1);
- custmem1 = 0;
- allocated_custmem1 = currprefs.custom_memory_sizes[0];
- custmem1_mask = allocated_custmem1 - 1;
- if (allocated_custmem1) {
- custmem1 = mapped_malloc (allocated_custmem1, _T("custmem1"));
- if (!custmem1)
- allocated_custmem1 = 0;
+ cdtv_loadcardmem(cardmem_bank.baseaddr, cardmem_bank.allocated);
+ }
+#endif
+ if (custmem1_bank.allocated != currprefs.custom_memory_sizes[0]) {
+ mapped_free (custmem1_bank.baseaddr);
+ custmem1_bank.baseaddr = NULL;
+ custmem1_bank.allocated = currprefs.custom_memory_sizes[0];
+ custmem1_bank.mask = custmem1_bank.allocated - 1;
+ custmem1_bank.start = currprefs.custom_memory_addrs[0];
+ if (custmem1_bank.allocated) {
+ custmem1_bank.baseaddr = mapped_malloc (custmem1_bank.allocated, _T("custmem1"));
+ if (!custmem1_bank.baseaddr)
+ custmem1_bank.allocated = 0;
}
}
- if (allocated_custmem2 != currprefs.custom_memory_sizes[1]) {
- if (custmem2)
- mapped_free (custmem2);
- custmem2 = 0;
- allocated_custmem2 = currprefs.custom_memory_sizes[1];
- custmem2_mask = allocated_custmem2 - 1;
- if (allocated_custmem2) {
- custmem2 = mapped_malloc (allocated_custmem2, _T("custmem2"));
- if (!custmem2)
- allocated_custmem2 = 0;
+ if (custmem2_bank.allocated != currprefs.custom_memory_sizes[1]) {
+ mapped_free (custmem2_bank.baseaddr);
+ custmem2_bank.baseaddr = NULL;
+ custmem2_bank.allocated = currprefs.custom_memory_sizes[1];
+ custmem2_bank.mask = custmem2_bank.allocated - 1;
+ custmem2_bank.start = currprefs.custom_memory_addrs[1];
+ if (custmem2_bank.allocated) {
+ custmem2_bank.baseaddr = mapped_malloc (custmem2_bank.allocated, _T("custmem2"));
+ if (!custmem2_bank.baseaddr)
+ custmem2_bank.allocated = 0;
}
}
restore_ram (bootrom_filepos, rtarea);
protect_roms (true);
}
- restore_ram (chip_filepos, chipmemory);
- if (allocated_bogomem > 0)
- restore_ram (bogo_filepos, bogomemory);
- if (allocated_a3000lmem > 0)
- restore_ram (a3000lmem_filepos, a3000lmemory);
- if (allocated_a3000hmem > 0)
- restore_ram (a3000hmem_filepos, a3000hmemory);
- }
- chipmem_bank.baseaddr = chipmemory;
+ restore_ram (chip_filepos, chipmem_bank.baseaddr);
+ if (bogomem_bank.allocated > 0)
+ restore_ram (bogo_filepos, bogomem_bank.baseaddr);
+ if (a3000lmem_bank.allocated > 0)
+ restore_ram (a3000lmem_filepos, a3000lmem_bank.baseaddr);
+ if (a3000hmem_bank.allocated > 0)
+ restore_ram (a3000hmem_filepos, a3000hmem_bank.baseaddr);
+ }
#ifdef AGA
- chipmem_bank_ce2.baseaddr = chipmemory;
+ chipmem_bank_ce2.baseaddr = chipmem_bank.baseaddr;
#endif
- bogomem_bank.baseaddr = bogomemory;
- a3000lmem_bank.baseaddr = a3000lmemory;
- a3000hmem_bank.baseaddr = a3000hmemory;
- cardmem_bank.baseaddr = cardmemory;
bootrom_filepos = 0;
chip_filepos = 0;
bogo_filepos = 0;
memset (ce_cachable, 0, sizeof ce_cachable);
memset (ce_cachable + (0x00200000 >> 16), 1, currprefs.fastmem_size >> 16);
memset (ce_cachable + (0x00c00000 >> 16), 1, currprefs.bogomem_size >> 16);
- memset (ce_cachable + (z3fastmem_start >> 16), 1, currprefs.z3fastmem_size >> 16);
- memset (ce_cachable + (z3fastmem2_start >> 16), 1, currprefs.z3fastmem2_size >> 16);
+ memset (ce_cachable + (z3fastmem_bank.start >> 16), 1, currprefs.z3fastmem_size >> 16);
+ memset (ce_cachable + (z3fastmem2_bank.start >> 16), 1, currprefs.z3fastmem2_size >> 16);
if (&get_mem_bank (0) == &chipmem_bank) {
for (i = 0; i < (0x200000 >> 16); i++)
int size;
addrbank *cb;
- size = allocated_chipmem >= 0x180000 ? (allocated_chipmem >> 16) : 32;
+ size = chipmem_bank.allocated >= 0x180000 ? (chipmem_bank.allocated >> 16) : 32;
cb = &chipmem_bank;
#ifdef AGA
#if 0
if (chip) {
map_banks (&dummy_bank, 0, 32, 0);
if (!isdirectjit ()) {
- map_banks (cb, 0, size, allocated_chipmem);
- if ((currprefs.chipset_mask & CSMASK_ECS_AGNUS) && allocated_bogomem == 0) {
- int start = allocated_chipmem >> 16;
- if (allocated_chipmem < 0x100000) {
- int dummy = (0x100000 - allocated_chipmem) >> 16;
+ map_banks (cb, 0, size, chipmem_bank.allocated);
+ if ((currprefs.chipset_mask & CSMASK_ECS_AGNUS) && bogomem_bank.allocated == 0) {
+ int start = chipmem_bank.allocated >> 16;
+ if (chipmem_bank.allocated < 0x100000) {
+ int dummy = (0x100000 - chipmem_bank.allocated) >> 16;
map_banks (&chipmem_dummy_bank, start, dummy, 0);
map_banks (&chipmem_dummy_bank, start + 16, dummy, 0);
- } else if (allocated_chipmem < 0x200000 && allocated_chipmem > 0x100000) {
- int dummy = (0x200000 - allocated_chipmem) >> 16;
+ } else if (chipmem_bank.allocated < 0x200000 && chipmem_bank.allocated > 0x100000) {
+ int dummy = (0x200000 - chipmem_bank.allocated) >> 16;
map_banks (&chipmem_dummy_bank, start, dummy, 0);
}
}
} else {
- map_banks (cb, 0, allocated_chipmem >> 16, 0);
+ map_banks (cb, 0, chipmem_bank.allocated >> 16, 0);
}
} else {
addrbank *rb = NULL;
mem_hardreset = 0;
if (savestate_state == STATE_RESTORE)
return;
- if (chipmemory)
- memset (chipmemory, 0, allocated_chipmem);
- if (bogomemory)
- memset (bogomemory, 0, allocated_bogomem);
- if (a3000lmemory)
- memset (a3000lmemory, 0, allocated_a3000lmem);
- if (a3000hmemory)
- memset (a3000hmemory, 0, allocated_a3000hmem);
+ if (chipmem_bank.baseaddr)
+ memset (chipmem_bank.baseaddr, 0, chipmem_bank.allocated);
+ if (bogomem_bank.baseaddr)
+ memset (bogomem_bank.baseaddr, 0, bogomem_bank.allocated);
+ if (a3000lmem_bank.baseaddr)
+ memset (a3000lmem_bank.baseaddr, 0, a3000lmem_bank.allocated);
+ if (a3000hmem_bank.baseaddr)
+ memset (a3000hmem_bank.baseaddr, 0, a3000hmem_bank.allocated);
expansion_clear ();
}
memcpy (currprefs.romfile, changed_prefs.romfile, sizeof currprefs.romfile);
memcpy (currprefs.romextfile, changed_prefs.romextfile, sizeof currprefs.romextfile);
need_hardreset = true;
- mapped_free (extendedkickmemory);
- extendedkickmemory = 0;
- extendedkickmem_size = 0;
- extendedkickmemory2 = 0;
- extendedkickmem2_size = 0;
+ mapped_free (extendedkickmem_bank.baseaddr);
+ extendedkickmem_bank.baseaddr = NULL;
+ extendedkickmem_bank.allocated = 0;
+ extendedkickmem2_bank.baseaddr = NULL;
+ extendedkickmem2_bank.allocated = 0;
extendedkickmem_type = 0;
load_extendedkickstart (currprefs.romextfile, 0);
load_extendedkickstart (currprefs.romextfile2, EXTENDED_ROM_CDTV);
- kickmem_mask = 524288 - 1;
+ kickmem_bank.mask = 524288 - 1;
if (!load_kickstart ()) {
if (_tcslen (currprefs.romfile) > 0) {
write_log (_T("Failed to open '%s'\n"), currprefs.romfile);
}
load_kickstart_replacement ();
} else {
- struct romdata *rd = getromdatabydata (kickmemory, kickmem_size);
+ struct romdata *rd = getromdatabydata (kickmem_bank.baseaddr, kickmem_bank.allocated);
if (rd) {
write_log (_T("Known ROM '%s' loaded\n"), rd->name);
if ((rd->cpu & 8) && changed_prefs.cpu_model < 68030) {
protect_roms (true);
}
- if ((cloanto_rom || extendedkickmem_size) && currprefs.maprom && currprefs.maprom < 0x01000000) {
+ if ((cloanto_rom || extendedkickmem_bank.allocated) && currprefs.maprom && currprefs.maprom < 0x01000000) {
currprefs.maprom = changed_prefs.maprom = 0x00a80000;
- if (extendedkickmem2_size) // can't do if 2M ROM
+ if (extendedkickmem2_bank.allocated) // can't do if 2M ROM
currprefs.maprom = changed_prefs.maprom = 0;
}
map_banks (&dummy_bank, 0xD8, 6, 0);
/* map "nothing" to 0x200000 - 0x9FFFFF (0xBEFFFF if Gayle or Fat Gary) */
- bnk = allocated_chipmem >> 16;
+ bnk = chipmem_bank.allocated >> 16;
if (bnk < 0x20 + (currprefs.fastmem_size >> 16))
bnk = 0x20 + (currprefs.fastmem_size >> 16);
bnk_end = gayleorfatgary ? 0xBF : 0xA0;
map_banks (&dummy_bank, 0xc0, 0xd8 - 0xc0, 0);
}
- if (bogomemory != 0) {
+ if (bogomem_bank.baseaddr) {
int t = currprefs.bogomem_size >> 16;
if (t > 0x1C)
t = 0x1C;
a3000scsi_reset ();
#endif
- if (a3000lmemory != 0)
- map_banks (&a3000lmem_bank, a3000lmem_start >> 16, allocated_a3000lmem >> 16, 0);
- if (a3000hmemory != 0)
- map_banks (&a3000hmem_bank, a3000hmem_start >> 16, allocated_a3000hmem >> 16, 0);
+ if (a3000lmem_bank.baseaddr)
+ map_banks (&a3000lmem_bank, a3000lmem_bank.start >> 16, a3000lmem_bank.allocated >> 16, 0);
+ if (a3000hmem_bank.baseaddr)
+ map_banks (&a3000hmem_bank, a3000hmem_bank.start >> 16, a3000hmem_bank.allocated >> 16, 0);
#ifdef CDTV
- if (cardmemory != 0)
- map_banks (&cardmem_bank, cardmem_start >> 16, allocated_cardmem >> 16, 0);
+ if (cardmem_bank.baseaddr)
+ map_banks (&cardmem_bank, cardmem_bank.start >> 16, cardmem_bank.allocated >> 16, 0);
#endif
map_banks (&kickmem_bank, 0xF8, 8, 0);
if (currprefs.maprom)
- map_banks (&kickram_bank, currprefs.maprom >> 16, extendedkickmem2_size ? 32 : (extendedkickmem_size ? 16 : 8), 0);
+ map_banks (&kickram_bank, currprefs.maprom >> 16, extendedkickmem2_bank.allocated ? 32 : (extendedkickmem_bank.allocated ? 16 : 8), 0);
/* map beta Kickstarts at 0x200000/0xC00000/0xF00000 */
- if (kickmemory[0] == 0x11 && kickmemory[2] == 0x4e && kickmemory[3] == 0xf9 && kickmemory[4] == 0x00) {
- uae_u32 addr = kickmemory[5];
+ if (kickmem_bank.baseaddr[0] == 0x11 && kickmem_bank.baseaddr[2] == 0x4e && kickmem_bank.baseaddr[3] == 0xf9 && kickmem_bank.baseaddr[4] == 0x00) {
+ uae_u32 addr = kickmem_bank.baseaddr[5];
if (addr == 0x20 && currprefs.chipmem_size <= 0x200000 && currprefs.fastmem_size == 0)
map_banks (&kickmem_bank, addr, 8, 0);
if (addr == 0xC0 && currprefs.bogomem_size == 0)
break;
#ifdef CDTV
case EXTENDED_ROM_CDTV:
- map_banks (&extendedkickmem_bank, 0xF0, extendedkickmem_size == 2 * 524288 ? 16 : 8, 0);
+ map_banks (&extendedkickmem_bank, 0xF0, extendedkickmem_bank.allocated == 2 * 524288 ? 16 : 8, 0);
break;
#endif
#ifdef CD32
if ((cloanto_rom || currprefs.cs_ksmirror_e0) && (currprefs.maprom != 0xe00000) && !extendedkickmem_type)
map_banks (&kickmem_bank, 0xE0, 8, 0);
if (currprefs.cs_ksmirror_a8) {
- if (extendedkickmem2_size) {
+ if (extendedkickmem2_bank.allocated) {
map_banks (&extendedkickmem2_bank, 0xa8, 16, 0);
} else {
struct romdata *rd = getromdatabypath (currprefs.cartfile);
init_mem_banks ();
virtualdevice_init ();
- allocated_chipmem = 0;
- allocated_bogomem = 0;
- kickmemory = 0;
- extendedkickmemory = 0;
- extendedkickmem_size = 0;
- extendedkickmemory2 = 0;
- extendedkickmem2_size = 0;
+ chipmem_bank.allocated = 0;
+ bogomem_bank.allocated = 0;
+ kickmem_bank.baseaddr = NULL;
+ extendedkickmem_bank.baseaddr = NULL;
+ extendedkickmem_bank.allocated = 0;
+ extendedkickmem2_bank.baseaddr = NULL;
+ extendedkickmem2_bank.allocated = 0;
extendedkickmem_type = 0;
- chipmemory = 0;
- allocated_a3000lmem = allocated_a3000hmem = 0;
- a3000lmemory = a3000hmemory = 0;
- bogomemory = 0;
- cardmemory = 0;
- allocated_custmem1 = allocated_custmem2 = 0;
- custmem1 = 0;
- custmem2 = 0;
-
- kickmemory = mapped_malloc (0x80000, _T("kick"));
- memset (kickmemory, 0, 0x80000);
- kickmem_bank.baseaddr = kickmemory;
+ chipmem_bank.baseaddr = 0;
+ a3000lmem_bank.allocated = a3000hmem_bank.allocated = 0;
+ a3000lmem_bank.baseaddr = a3000hmem_bank.baseaddr = NULL;
+ bogomem_bank.baseaddr = NULL;
+ cardmem_bank.baseaddr = NULL;
+ custmem1_bank.allocated = custmem2_bank.allocated = 0;
+ custmem1_bank.baseaddr = NULL;
+ custmem2_bank.baseaddr = NULL;
+
+ kickmem_bank.baseaddr = mapped_malloc (0x80000, _T("kick"));
+ memset (kickmem_bank.baseaddr, 0, 0x80000);
_tcscpy (currprefs.romfile, _T("<none>"));
currprefs.romextfile[0] = 0;
void memory_cleanup (void)
{
- if (a3000lmemory)
- mapped_free (a3000lmemory);
- if (a3000hmemory)
- mapped_free (a3000hmemory);
- if (bogomemory)
- mapped_free (bogomemory);
- if (kickmemory)
- mapped_free (kickmemory);
- if (a1000_bootrom)
- xfree (a1000_bootrom);
- if (chipmemory)
- mapped_free (chipmemory);
+ mapped_free (a3000lmem_bank.baseaddr);
+ mapped_free (a3000hmem_bank.baseaddr);
+ mapped_free (bogomem_bank.baseaddr);
+ mapped_free (kickmem_bank.baseaddr);
+ xfree (a1000_bootrom);
+ mapped_free (chipmem_bank.baseaddr);
#ifdef CDTV
- if (cardmemory) {
- cdtv_savecardmem (cardmemory, allocated_cardmem);
- mapped_free (cardmemory);
+ if (cardmem_bank.baseaddr) {
+ cdtv_savecardmem (cardmem_bank.baseaddr, cardmem_bank.allocated);
+ mapped_free (cardmem_bank.baseaddr);
}
#endif
- if (custmem1)
- mapped_free (custmem1);
- if (custmem2)
- mapped_free (custmem2);
+ mapped_free (custmem1_bank.baseaddr);
+ mapped_free (custmem2_bank.baseaddr);
- bogomemory = 0;
- kickmemory = 0;
- a3000lmemory = a3000hmemory = 0;
- a1000_bootrom = 0;
+ bogomem_bank.baseaddr = NULL;
+ kickmem_bank.baseaddr = NULL;
+ a3000lmem_bank.baseaddr = a3000hmem_bank.baseaddr = NULL;
+ a1000_bootrom = NULL;
a1000_kickstart_mode = 0;
- chipmemory = 0;
- cardmemory = 0;
- custmem1 = 0;
- custmem2 = 0;
+ chipmem_bank.baseaddr = NULL;
+ cardmem_bank.baseaddr = NULL;
+ custmem1_bank.baseaddr = NULL;
+ custmem2_bank.baseaddr = NULL;
#ifdef ACTION_REPLAY
action_replay_cleanup();
map_banks (bank, start, size, realsize);
}
-void map_banks (addrbank *bank, int start, int size, int realsize)
+static void map_banks2 (addrbank *bank, int start, int size, int realsize, int quick)
{
int bnr, old;
unsigned long int hioffs = 0, endhioffs = 0x100;
addrbank *orgbank = bank;
uae_u32 realstart = start;
- old = debug_bankchange (-1);
+ if (!quick)
+ old = debug_bankchange (-1);
flush_icache (0, 3); /* Sure don't want to keep any old mappings around! */
#ifdef NATMEM_OFFSET
- delete_shmmaps (start << 16, size << 16);
+ if (!quick)
+ delete_shmmaps (start << 16, size << 16);
#endif
if (!realsize)
realstart = bnr;
real_left = realsize >> 16;
#ifdef NATMEM_OFFSET
- add_shmmaps (realstart << 16, bank);
+ if (!quick)
+ add_shmmaps (realstart << 16, bank);
#endif
}
put_mem_bank (bnr << 16, bank, realstart << 16);
real_left--;
}
- debug_bankchange (old);
+ if (!quick)
+ debug_bankchange (old);
return;
}
#endif
realstart = bnr + hioffs;
real_left = realsize >> 16;
#ifdef NATMEM_OFFSET
- add_shmmaps (realstart << 16, bank);
+ if (!quick)
+ add_shmmaps (realstart << 16, bank);
#endif
}
put_mem_bank ((bnr + hioffs) << 16, bank, realstart << 16);
real_left--;
}
}
- debug_bankchange (old);
+ if (!quick)
+ debug_bankchange (old);
fill_ce_banks ();
}
+void map_banks (addrbank *bank, int start, int size, int realsize)
+{
+ map_banks2 (bank, start, size, realsize, 0);
+}
+void map_banks_quick (addrbank *bank, int start, int size, int realsize)
+{
+ map_banks2 (bank, start, size, realsize, 1);
+}
+
+
#ifdef SAVESTATE
/* memory save/restore code */
uae_u8 *save_cram (int *len)
{
- *len = allocated_chipmem;
- return chipmemory;
+ *len = chipmem_bank.allocated;
+ return chipmem_bank.baseaddr;
}
uae_u8 *save_bram (int *len)
{
- *len = allocated_bogomem;
- return bogomemory;
+ *len = bogomem_bank.allocated;
+ return bogomem_bank.baseaddr;
}
uae_u8 *save_a3000lram (int *len)
{
- *len = allocated_a3000lmem;
- return a3000lmemory;
+ *len = a3000lmem_bank.allocated;
+ return a3000lmem_bank.baseaddr;
}
uae_u8 *save_a3000hram (int *len)
{
- *len = allocated_a3000hmem;
- return a3000hmemory;
+ *len = a3000hmem_bank.allocated;
+ return a3000hmem_bank.baseaddr;
}
void restore_bootrom (int len, size_t filepos)
switch (count) {
case 0: /* Kickstart ROM */
mem_start = 0xf80000;
- mem_real_start = kickmemory;
- mem_size = kickmem_size;
+ mem_real_start = kickmem_bank.baseaddr;
+ mem_size = kickmem_bank.allocated;
path = currprefs.romfile;
/* 256KB or 512KB ROM? */
for (i = 0; i < mem_size / 2 - 4; i++) {
case 1: /* Extended ROM */
if (!extendedkickmem_type)
break;
- mem_start = extendedkickmem_start;
- mem_real_start = extendedkickmemory;
- mem_size = extendedkickmem_size;
+ mem_start = extendedkickmem_bank.start;
+ mem_real_start = extendedkickmem_bank.baseaddr;
+ mem_size = extendedkickmem_bank.allocated;
path = currprefs.romextfile;
version = longget (mem_start + 12); /* version+revision */
if (version == 0xffffffff)
buf = p = xmalloc (uae_u8, size);
if (!buf)
return;
- memcpy (p, chipmemory, currprefs.chipmem_size);
+ memcpy (p, chipmem_bank.baseaddr, currprefs.chipmem_size);
p += currprefs.chipmem_size;
- mc (p, fastmem_start, currprefs.fastmem_size);
+ mc (p, fastmem_bank.start, currprefs.fastmem_size);
p += currprefs.fastmem_size;
- mc (p, bogomem_start, currprefs.bogomem_size);
+ mc (p, bogomem_bank.start, currprefs.bogomem_size);
p += currprefs.bogomem_size;
- mc (p, a3000lmem_start, currprefs.mbresmem_low_size);
+ mc (p, a3000lmem_bank.start, currprefs.mbresmem_low_size);
p += currprefs.mbresmem_low_size;
- mc (p, a3000hmem_start, currprefs.mbresmem_high_size);
+ mc (p, a3000hmem_bank.start, currprefs.mbresmem_high_size);
p += currprefs.mbresmem_high_size;
- mc (p, z3fastmem_start, currprefs.z3fastmem_size);
+ mc (p, z3fastmem_bank.start, currprefs.z3fastmem_size);
p += currprefs.z3fastmem_size;
- mc (p, z3fastmem_start + currprefs.z3fastmem_size, currprefs.z3fastmem2_size);
+ mc (p, z3fastmem_bank.start + currprefs.z3fastmem_size, currprefs.z3fastmem2_size);
p += currprefs.z3fastmem2_size;
got = 0;
write_log (_T("ncr_wput %04X=%04X PC=%08X\n"), addr, w & 65535, M68K_GETPC);
#endif
if (addr == 0x44 && !configured) {
- uae_u32 value = (p96ram_start + ((currprefs.rtgmem_size + 0xffffff) & ~0xffffff)) >> 16;
+ uae_u32 value = (gfxmem_bank.start + ((currprefs.rtgmem_size + 0xffffff) & ~0xffffff)) >> 16;
chipmem_wput (regs.regs[11] + 0x20, value);
chipmem_wput (regs.regs[11] + 0x28, value);
map_banks (&ncr_bank, value, BOARD_SIZE >> 16, 0);
while (regs.spcflags & SPCFLAG_STOP) {
- if (uae_int_requested) {
+ if (uae_int_requested || uaenet_int_requested) {
INTREQ_f (0x8008);
set_special (SPCFLAG_INT);
}
- {
- extern int volatile uaenet_int_requested;
- if (uaenet_int_requested) {
- INTREQ_f (0x8000 | 0x2000);
- set_special (SPCFLAG_INT);
- }
- }
{
extern void bsdsock_fake_int_handler (void);
extern int volatile bsd_int_requested;
return 1;
}
- if (!uae_int_requested && currprefs.cpu_idle && currprefs.m68k_speed != 0 && (regs.spcflags & SPCFLAG_STOP)) {
+ if (!uae_int_requested && !uaenet_int_requested && currprefs.cpu_idle && currprefs.m68k_speed != 0 && (regs.spcflags & SPCFLAG_STOP)) {
/* sleep 1ms if STOP-instruction is executed
* but only if we have free frametime left to prevent slowdown
*/
cpu_cycles = adjust_cycles (cpu_cycles);
do_cycles (cpu_cycles);
- if (end_block (opcode) || r->spcflags || uae_int_requested)
+ if (end_block (opcode) || r->spcflags || uae_int_requested || uaenet_int_requested)
return; /* We will deal with the spcflags in the caller */
}
}
total_cycles += cpu_cycles;
pc_hist[blocklen].specmem = special_mem;
blocklen++;
- if (end_block (opcode) || blocklen >= MAXRUN || r->spcflags || uae_int_requested) {
+ if (end_block (opcode) || blocklen >= MAXRUN || r->spcflags || uae_int_requested || uaenet_int_requested) {
compile_block (pc_hist, blocklen, total_cycles);
return; /* We will deal with the spcflags in the caller */
}
for (;;) {
((compiled_handler*)(pushall_call_handler))();
/* Whenever we return from that, we should check spcflags */
- if (uae_int_requested) {
+ if (uae_int_requested || uaenet_int_requested) {
INTREQ_f (0x8008);
set_special (SPCFLAG_INT);
}
int removablemedia;
int nomedia;
int dangerous;
+ bool partitiondrive;
int readonly;
int cylinders, sectors, heads;
};
hfd->offset = udi->offset;
hfd->physsize = hfd->virtsize = udi->size;
hfd->ci.blocksize = udi->bytespersector;
+ if (udi->partitiondrive)
+ hfd->flags |= HFD_FLAGS_REALDRIVEPARTITION;
if (hfd->offset == 0 && !hfd->drive_empty) {
int sf = safetycheck (hfd->handle->h, udi->device_path, 0, hfd->cache, hfd->ci.blocksize);
if (sf > 0)
if (hfd->handle_valid == HDF_HANDLE_WIN32) {
TCHAR *name = hfd->emptyname == NULL ? _T("<unknown>") : hfd->emptyname;
if (offset == 0) {
- if (!hfd->handle->firstwrite && (hfd->flags & HFD_FLAGS_REALDRIVE)) {
+ if (!hfd->handle->firstwrite && (hfd->flags & HFD_FLAGS_REALDRIVE) && !(hfd->flags & HFD_FLAGS_REALDRIVEPARTITION)) {
hfd->handle->firstwrite = true;
if (ismounted (hfd->device_name, hfd->handle->h)) {
gui_message (_T("\"%s\"\n\nBlock zero write attempt but drive has one or more mounted PC partitions or WinUAE does not have Administrator privileges. Erase the drive or unmount all PC partitions first."), name);
write_log (_T("used\n"));
_stprintf (udi->device_name, _T(":P#%d_%s"), pi->PartitionNumber, orgname);
udi->dangerous = -5;
+ udi->partitiondrive = true;
udi++;
(*index2)++;
safepart = 1;
{
shmpiece *x = shm_start;
+ if (mem == NULL)
+ return;
if (mem == filesysory) {
while(x) {
if (mem == x->native_address) {
got = TRUE;
p96special = TRUE;
shmaddr = natmem_offset + start;
- p96ram_start = start;
+ gfxmem_bank.start = start;
if (start + currprefs.rtgmem_size < 10 * 1024 * 1024)
size += BARRIER;
} else if(!_tcscmp (shmids[shmid].name, _T("ramsey_low"))) {
- shmaddr=natmem_offset + a3000lmem_start;
- if (!a3000hmem_start)
+ shmaddr=natmem_offset + a3000lmem_bank.start;
+ if (!a3000hmem_bank.start)
size += BARRIER;
got = TRUE;
} else if(!_tcscmp (shmids[shmid].name, _T("ramsey_high"))) {
- shmaddr=natmem_offset + a3000hmem_start;
+ shmaddr=natmem_offset + a3000hmem_bank.start;
got = TRUE;
} else if(!_tcscmp (shmids[shmid].name, _T("z3"))) {
- shmaddr=natmem_offset + z3fastmem_start;
+ shmaddr=natmem_offset + z3fastmem_bank.start;
if (!currprefs.z3fastmem2_size)
size += BARRIER;
got = TRUE;
} else if(!_tcscmp (shmids[shmid].name, _T("z3_2"))) {
- shmaddr=natmem_offset + z3fastmem_start + currprefs.z3fastmem_size;
+ shmaddr=natmem_offset + z3fastmem_bank.start + currprefs.z3fastmem_size;
size += BARRIER;
got = TRUE;
} else if(!_tcscmp (shmids[shmid].name, _T("z3_chip"))) {
- shmaddr=natmem_offset + z3chipmem_start;
+ shmaddr=natmem_offset + z3chipmem_bank.start;
size += BARRIER;
got = TRUE;
} else if(!_tcscmp (shmids[shmid].name, _T("z3_gfx"))) {
got = TRUE;
p96special = TRUE;
- p96ram_start = p96mem_offset - natmem_offset;
- shmaddr = natmem_offset + p96ram_start;
+ gfxmem_bank.start = p96mem_offset - natmem_offset;
+ shmaddr = natmem_offset + gfxmem_bank.start;
size += BARRIER;
} else if(!_tcscmp (shmids[shmid].name, _T("bogo"))) {
shmaddr=natmem_offset+0x00C00000;
#endif
#define P96TRACE2(x) do { write_log x; } while(0)
-static void REGPARAM2 gfxmem_lputx (uaecptr, uae_u32) REGPARAM;
-static void REGPARAM2 gfxmem_wputx (uaecptr, uae_u32) REGPARAM;
-static void REGPARAM2 gfxmem_bputx (uaecptr, uae_u32) REGPARAM;
-
static uae_u8 all_ones_bitmap, all_zeros_bitmap; /* yuk */
struct picasso96_state_struct picasso96_state;
{
if (! picasso_on)
return 0;
- if (ri->Memory != gfxmemory + (picasso96_state.Address - gfxmem_start))
+ if (ri->Memory != gfxmem_bank.baseaddr + (picasso96_state.Address - gfxmem_bank.start))
return 0;
return 1;
}
;
} else {
if (uaegfx) {
- flushed = picasso_flushpixels (p96ram_start + natmem_offset, picasso96_state.XYOffset - gfxmem_start);
+ flushed = picasso_flushpixels (gfxmem_bank.start + natmem_offset, picasso96_state.XYOffset - gfxmem_bank.start);
} else {
gfxboard_vsync_handler ();
}
unsigned int width, height;
/* blit the stuff from our static frame-buffer to the gfx-card */
- ri.Memory = gfxmemory + (picasso96_state.Address - gfxmem_start);
+ ri.Memory = gfxmem_bank.baseaddr + (picasso96_state.Address - gfxmem_bank.start);
ri.BytesPerRow = picasso96_state.BytesPerRow;
ri.RGBFormat = picasso96_state.RGBFormat;
{
uaecptr AmigaBoardInfo = m68k_areg (regs, 0);
/* NOTES: See BoardInfo struct definition in Picasso96 dev info */
- if (!uaegfx_active || !gfxmem_start)
+ if (!uaegfx_active || !gfxmem_bank.start)
return 0;
if (uaegfx_base) {
put_long (uaegfx_base + CARD_BOARDINFO, AmigaBoardInfo);
picasso96_alloc2 (ctx);
}
boardinfo = AmigaBoardInfo;
- if (allocated_gfxmem && !picasso96_state.CardFound) {
+ if (gfxmem_bank.allocated && !picasso96_state.CardFound) {
/* Fill in MemoryBase, MemorySize */
- put_long (AmigaBoardInfo + PSSO_BoardInfo_MemoryBase, gfxmem_start);
- put_long (AmigaBoardInfo + PSSO_BoardInfo_MemorySize, allocated_gfxmem - reserved_gfxmem);
+ put_long (AmigaBoardInfo + PSSO_BoardInfo_MemoryBase, gfxmem_bank.start);
+ put_long (AmigaBoardInfo + PSSO_BoardInfo_MemorySize, gfxmem_bank.allocated - reserved_gfxmem);
picasso96_state.CardFound = 1; /* mark our "card" as being found */
return -1;
} else
{
ULONG ps;
writewatchcount = gwwbufsize;
- if (GetWriteWatch (WRITE_WATCH_FLAG_RESET, p96ram_start + natmem_offset, (gwwbufsize - 1) * gwwpagesize, gwwbuf, &writewatchcount, &ps)) {
+ if (GetWriteWatch (WRITE_WATCH_FLAG_RESET, gfxmem_bank.start + natmem_offset, (gwwbufsize - 1) * gwwpagesize, gwwbuf, &writewatchcount, &ps)) {
write_log (_T("picasso_getwritewatch %d\n"), GetLastError ());
writewatchcount = 0;
return;
picasso96_amem = get_long (uaegfx_base + CARD_RESLIST);
} else if (uaegfx_active) {
reserved_gfxmem = size;
- picasso96_amem = gfxmem_start + allocated_gfxmem - size;
+ picasso96_amem = gfxmem_bank.start + gfxmem_bank.allocated - size;
}
picasso96_amemend = picasso96_amem + size;
write_log (_T("P96 RESINFO: %08X-%08X (%d,%d)\n"), picasso96_amem, picasso96_amemend, size / PSSO_ModeInfo_sizeof, size);
- picasso_allocatewritewatch (allocated_gfxmem);
+ picasso_allocatewritewatch (gfxmem_bank.allocated);
}
static int p96depth (int depth)
xfree (newmodes);
newmodes = NULL;
picasso96_amem = picasso96_amemend = 0;
- if (allocated_gfxmem == 0)
+ if (gfxmem_bank.allocated == 0)
return;
misscnt = 0;
newmodes = xmalloc (struct PicassoResolution, MAX_PICASSO_MODES);
for (depth = 8; depth <= 32; depth++) {
if (!p96depth (depth))
continue;
- if(allocated_gfxmem >= w * h * (depth + 7) / 8) {
+ if(gfxmem_bank.allocated >= w * h * (depth + 7) / 8) {
FillBoardInfo (*amem, res, w, h, depth);
*amem += PSSO_ModeInfo_sizeof;
}
picasso_refresh ();
}
init_picasso_screen_called = 1;
- mman_ResetWatch (p96ram_start + natmem_offset, allocated_gfxmem);
+ mman_ResetWatch (gfxmem_bank.start + natmem_offset, gfxmem_bank.allocated);
}
uae_u8 *getrtgbuffer (int *widthp, int *heightp, int *pitch, int *depth, uae_u8 *palette)
{
- uae_u8 *src = p96ram_start + natmem_offset;
- int off = picasso96_state.XYOffset - gfxmem_start;
+ uae_u8 *src = gfxmem_bank.start + natmem_offset;
+ int off = picasso96_state.XYOffset - gfxmem_bank.start;
int width, height, pixbytes;
uae_u8 *dst;
int convert;
return lock != 0;
}
-static uae_u32 REGPARAM2 gfxmem_lgetx (uaecptr addr)
-{
- uae_u32 *m;
-
- addr -= gfxmem_start & gfxmem_mask;
- addr &= gfxmem_mask;
- m = (uae_u32 *)(gfxmemory + addr);
- return do_get_mem_long (m);
-}
-
-static uae_u32 REGPARAM2 gfxmem_wgetx (uaecptr addr)
-{
- uae_u16 *m;
- addr -= gfxmem_start & gfxmem_mask;
- addr &= gfxmem_mask;
- m = (uae_u16 *)(gfxmemory + addr);
- return do_get_mem_word (m);
-}
-
-static uae_u32 REGPARAM2 gfxmem_bgetx (uaecptr addr)
-{
- addr -= gfxmem_start & gfxmem_mask;
- addr &= gfxmem_mask;
- return gfxmemory[addr];
-}
-
-static void REGPARAM2 gfxmem_lputx (uaecptr addr, uae_u32 l)
-{
- uae_u32 *m;
- addr -= gfxmem_start & gfxmem_mask;
- addr &= gfxmem_mask;
- m = (uae_u32 *)(gfxmemory + addr);
- do_put_mem_long (m, l);
-}
-
-static void REGPARAM2 gfxmem_wputx (uaecptr addr, uae_u32 w)
-{
- uae_u16 *m;
- addr -= gfxmem_start & gfxmem_mask;
- addr &= gfxmem_mask;
- m = (uae_u16 *)(gfxmemory + addr);
- do_put_mem_word (m, (uae_u16)w);
-}
-
-static void REGPARAM2 gfxmem_bputx (uaecptr addr, uae_u32 b)
-{
- addr -= gfxmem_start & gfxmem_mask;
- addr &= gfxmem_mask;
- gfxmemory[addr] = b;
-}
-
-static int REGPARAM2 gfxmem_check (uaecptr addr, uae_u32 size)
-{
- addr -= gfxmem_start & gfxmem_mask;
- addr &= gfxmem_mask;
- return (addr + size) < allocated_gfxmem;
-}
-
-static uae_u8 *REGPARAM2 gfxmem_xlate (uaecptr addr)
-{
- addr -= gfxmem_start & gfxmem_mask;
- addr &= gfxmem_mask;
- return gfxmemory + addr;
-}
+MEMORY_FUNCTIONS(gfxmem);
addrbank gfxmem_bank = {
- gfxmem_lgetx, gfxmem_wgetx, gfxmem_bgetx,
- gfxmem_lputx, gfxmem_wputx, gfxmem_bputx,
+ gfxmem_lget, gfxmem_wget, gfxmem_bget,
+ gfxmem_lput, gfxmem_wput, gfxmem_bput,
gfxmem_xlate, gfxmem_check, NULL, _T("RTG RAM"),
dummy_lgeti, dummy_wgeti, ABFLAG_RAM
};
uaecptr findcardfunc, initcardfunc;
uaecptr exec = get_long (4);
- if (uaegfx_old || !gfxmem_start)
+ if (uaegfx_old || !gfxmem_bank.start)
return NULL;
uaegfx_resid = ds (_T("UAE Graphics Card 3.3"));
case 31: return picasso_InvertRect (ctx);
case 32: return picasso_BlitPlanar2Direct (ctx);
//case 34: return picasso_WaitVerticalSync (ctx);
- case 35: return allocated_gfxmem ? 1 : 0;
+ case 35: return gfxmem_bank.allocated ? 1 : 0;
case 36: return picasso_SetSprite (ctx);
case 37: return picasso_SetSpritePosition (ctx);
case 38: return picasso_SetSpriteImage (ctx);
extern void InitPicasso96 (void);
-extern uae_u32 gfxmem_mask;
-extern uae_u8 *gfxmemory;
-
extern int uaegfx_card_found;
extern struct picasso96_state_struct picasso96_state;
copy winuaesrc.zip d:\amiga\winuaepackets\winuaesrc%1.zip
move winuaesrc.zip d:\amiga
cd c:\projects\winuae\src\od-win32
-zip -9 winuaedebug%1 winuae_msvc10\release\winuae.pdb winuae_msvc10\fullrelease\winuae.pdb
+zip -9 winuaedebug%1 winuae_msvc11\release\winuae.pdb winuae_msvc11\fullrelease\winuae.pdb
move winuaedebug%1.zip d:\amiga\winuaepackets\debug\
-copy winuae_msvc10\fullrelease\winuae.pdb d:\amiga\dump
+copy winuae_msvc11\fullrelease\winuae.pdb d:\amiga\dump
copy d:\amiga\winuae.exe d:\amiga\dump
p->rtg_hardwareinterrupt = false;
p->rtg_hardwaresprite = false;
p->win32_rtgmatchdepth = false;
+ if (gfxboard_need_byteswap (p->rtgmem_type))
+ p->color_mode = 5;
}
}
#define LANG_DLL 1
#if WINUAEPUBLICBETA
-#define WINUAEBETA _T("1")
+#define WINUAEBETA _T("2")
#else
#define WINUAEBETA _T("")
#endif
-#define WINUAEDATE MAKEBD(2013, 7, 7)
+#define WINUAEDATE MAKEBD(2013, 7, 18)
#define WINUAEEXTRA _T("")
//#define WINUAEEXTRA _T("AmiKit Preview")
//#define WINUAEEXTRA _T("Amiga Forever Edition")
static int filterstackpos = 2 * MAX_FILTERSHADERS;
static const int defaultaspectratios[] = {
- 4, 3, 16, 10, 15, 9, 27, 16, 128, 75, 16, 9, 256, 135, 21, 9, 16, 3,
+ 5, 4, 4, 3, 16, 10, 15, 9, 27, 16, 128, 75, 16, 9, 256, 135, 21, 9, 16, 3,
-1
};
static int getaspectratioindex (int ar)
SendDlgItemMessage (hDlg, IDC_RTG_Z2Z3, CB_ADDSTRING, 0, (LPARAM)_T("Picasso II Zorro II"));
SendDlgItemMessage (hDlg, IDC_RTG_Z2Z3, CB_ADDSTRING, 0, (LPARAM)_T("Picasso II+ Zorro II"));
SendDlgItemMessage (hDlg, IDC_RTG_Z2Z3, CB_ADDSTRING, 0, (LPARAM)_T("Piccolo Zorro II"));
+ SendDlgItemMessage (hDlg, IDC_RTG_Z2Z3, CB_ADDSTRING, 0, (LPARAM)_T("Piccolo Zorro III"));
SendDlgItemMessage (hDlg, IDC_RTG_Z2Z3, CB_ADDSTRING, 0, (LPARAM)_T("Piccolo SD64 Zorro II"));
SendDlgItemMessage (hDlg, IDC_RTG_Z2Z3, CB_ADDSTRING, 0, (LPARAM)_T("Piccolo SD64 Zorro III"));
SendDlgItemMessage (hDlg, IDC_RTG_Z2Z3, CB_ADDSTRING, 0, (LPARAM)_T("Spectrum28/24 Zorro II"));
<UseOfMfc>false</UseOfMfc>
<CharacterSet>Unicode</CharacterSet>
<WholeProgramOptimization>true</WholeProgramOptimization>
- <PlatformToolset>v110_xp</PlatformToolset>
+ <PlatformToolset>v120_xp</PlatformToolset>
</PropertyGroup>
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'" Label="Configuration">
<ConfigurationType>Application</ConfigurationType>
<FavorSizeOrSpeed>Speed</FavorSizeOrSpeed>
<OmitFramePointers>true</OmitFramePointers>
<WholeProgramOptimization>true</WholeProgramOptimization>
- <AdditionalIncludeDirectories>..\..\include;..\..;..\;..\resources;..\osdep;..\sounddep;..\..\prowizard\include;%(AdditionalIncludeDirectories)</AdditionalIncludeDirectories>
+ <AdditionalIncludeDirectories>..\..\include;..\..;..\;..\resources;..\osdep;..\sounddep;..\..\prowizard\include;..\..\slirp;%(AdditionalIncludeDirectories)</AdditionalIncludeDirectories>
<PreprocessorDefinitions>WINVER=0x0500;NDEBUG;_WIN32_IE=0x0700;WIN32;%(PreprocessorDefinitions)</PreprocessorDefinitions>
<StringPooling>true</StringPooling>
<ExceptionHandling>Sync</ExceptionHandling>
<Culture>0x0409</Culture>
</ResourceCompile>
<Link>
- <AdditionalDependencies>ws2_32.lib;ddraw.lib;dxguid.lib;winmm.lib;comctl32.lib;version.lib;msacm32.lib;dsound.lib;dinput8.lib;d3d9.lib;d3dx9.lib;winio.lib;setupapi.lib;wininet.lib;dxerr.lib;shlwapi.lib;zlibstat.lib;libpng15.lib;lglcd.lib;wpcap.lib;packet.lib;openal32.lib;wintab32.lib;portaudio_x86.lib;vfw32.lib;wtsapi32.lib;avrt.lib;enet.lib;prowizard.lib;lzmalib.lib;libFLAC_static.lib;Avrt.lib;hid.lib;%(AdditionalDependencies)</AdditionalDependencies>
+ <AdditionalDependencies>ws2_32.lib;ddraw.lib;dxguid.lib;winmm.lib;comctl32.lib;version.lib;msacm32.lib;dsound.lib;dinput8.lib;d3d9.lib;d3dx9.lib;winio.lib;setupapi.lib;wininet.lib;dxerr.lib;shlwapi.lib;zlibstat.lib;libpng15.lib;lglcd.lib;wpcap.lib;packet.lib;openal32.lib;wintab32.lib;portaudio_x86.lib;vfw32.lib;wtsapi32.lib;avrt.lib;enet.lib;prowizard.lib;lzmalib.lib;libFLAC_static.lib;Avrt.lib;hid.lib;Iphlpapi.lib;luastatic.lib;%(AdditionalDependencies)</AdditionalDependencies>
<OutputFile>$(OutDir)$(TargetName)$(TargetExt)</OutputFile>
<SuppressStartupBanner>true</SuppressStartupBanner>
<AdditionalLibraryDirectories>%(AdditionalLibraryDirectories);$(SolutionDir)\..\lib\</AdditionalLibraryDirectories>
<AdditionalManifestDependencies>%(AdditionalManifestDependencies)</AdditionalManifestDependencies>
<IgnoreSpecificDefaultLibraries>%(IgnoreSpecificDefaultLibraries)</IgnoreSpecificDefaultLibraries>
- <DelayLoadDLLs>wpcap.dll;packet.dll;d3dx9_43.dll;openal32.dll;wintab32.dll;portaudio_x86.dll;ws2_32.dll;msacm32.dll;wtsapi32.dll;dsound.dll;wininet.dll;avrt.dll;ddraw.dll;%(DelayLoadDLLs)</DelayLoadDLLs>
+ <DelayLoadDLLs>wpcap.dll;packet.dll;d3dx9_43.dll;openal32.dll;wintab32.dll;portaudio_x86.dll;ws2_32.dll;msacm32.dll;wtsapi32.dll;dsound.dll;wininet.dll;avrt.dll;ddraw.dll;Iphlpapi.dll;%(DelayLoadDLLs)</DelayLoadDLLs>
<GenerateDebugInformation>true</GenerateDebugInformation>
<ProgramDatabaseFile>.\FullRelease/winuae.pdb</ProgramDatabaseFile>
<SubSystem>Windows</SubSystem>
<StackCommitSize>2621440</StackCommitSize>
<LargeAddressAware>true</LargeAddressAware>
<OptimizeReferences>true</OptimizeReferences>
- <EnableCOMDATFolding>true</EnableCOMDATFolding>
+ <EnableCOMDATFolding>false</EnableCOMDATFolding>
<LinkTimeCodeGeneration>UseLinkTimeCodeGeneration</LinkTimeCodeGeneration>
<RandomizedBaseAddress>true</RandomizedBaseAddress>
<FixedBaseAddress>false</FixedBaseAddress>
<TargetMachine>MachineX86</TargetMachine>
<MinimumRequiredVersion>5.01</MinimumRequiredVersion>
<ImageHasSafeExceptionHandlers>false</ImageHasSafeExceptionHandlers>
+ <SetChecksum>true</SetChecksum>
</Link>
<Manifest>
<AdditionalManifestFiles>../resources/winuae.exe.manifest</AdditionalManifestFiles>
- restore only single input target to default.
+Beta 1:
+
+- Hardware Cirrus Logic based SVGA Zorro II/III RTG board emulation.
+- SLIRP user mode NAT emulation.
+- Added SCSI tape emulation. Amix tape based install works, also tested with
+ Quarterback and Diavolo.
+- lua scripting support added from fs-uae. Very minimal at the moment.
+- SCSI HD/CD/TAPE statefile compatibility improved.
+- SCSI emulation compatibility improved, Amix use of WD Select and Transfer
+ used wrong data size when direction was from WD to device and command was not
+ write command, for example MODE SELECT.
+- Show custom chip mode as interlace/not interlaced decision now more closely matches
+ real hardware behavior. (No, it isn't as simple as BPLCON0 LACE bit set/not set)
+- Show also device type (HDF, CD, TAPE) in Harddrives panel.
+- Joystick axis dead-zone fix, wired xbox 360 d-pad missed events, it didn't affect
+ wireless version. (261b2)
+- Top and/or bottom border showed graphics garbage if AGA sprites outside of bitplane
+ area feature was enabled and in use and screen mode was HAM. (Tint / Black Lotus)
+- Dragging and dropping archive/file to WB tried (unsuccesfully) replace already
+ existing normal directory harddrive if dropped file and directory harddrive had same
+ base path.
+- Renamed CPU cycle exact speed multipliers and added 1x speed (1:1 CPU/DMA clock sync)
+- It was impossible to select RTG aspect ratio select box Automatic value.
+- Display panel depth select box was not updated if new resolution had more or less
+ depth choices than previously selected resolution.
+- Mouse was captured even if "Start mouse uncaptured" was ticked and booting to RTG mode.
+- Amiga side does not anymore see .lnk extension if it is valid Windows shortcut softlink.
+- Enabling JIT for the first time in GUI now always forces JIT Direct mode.
+- If blitter was started one cycle before final D write (Cycle which is always unused by
+ blitter), new blit's 2 cycle startup incorrectly accepted DMA cycles that were not free.
+ (Day of Reckoning / Digital)
+- Bitplane DMA incorrectly stole sprite DMA in some situations (Plastic Passion / Upfront)
+- Sync clock when resuming from sleep/hibernate (if clock sync option is ticked)
+
+SLIRP notes:
+
+- Available for A2065 and uaenet.device (uaenet unit 0 = slirp, 1 = first WinPCap device)
+- Does not need any drivers, uses normal WinSock API.
+- NAT, outbound connections only.
+- TCP and UDP only (no ICMP or other ethernet frame types)
+- DHCP supported.
+- Manual settings: IP 10.0.2.15, Gateway 10.0.2.2, DNS 10.0.2.3, Mask 255.255.255.0.
+
+Hardware graphics board emulation notes:
+
+- Currently emulates following Cirrus Logic GD542X/543X based boards:
+ - Picasso II
+ - Picasso II+
+ - Piccolo
+ - Piccolo SD 64 (Zorro II and III)
+ - Spectrum 28/24 (Zorro II and III)
+ - Picasso IV may be implemented in future.
+- Uses QEMU Cirrus Logic SVGA graphics chip emulation.
+- Picasso 96 and CyberGraphX v4 tested.
+- Works with non-AmigaOS operating systems that don't support UAEGFX RTG board.
+- Vertical blank timing uses GUI configured refresh rate value, display sync settings programmed
+ to VGA chip are completely ignored.
+- Only single VRAM size supported which is hardware supported max VRAM. Smaller VRAM requires
+ emulating of VRAM aliasing and banking stuff that drivers use for VRAM size detection. It would
+ become too Direct mode JIT unfriendly. Future "more compatible but slower" option is possible.
+
+SCSI Tape notes:
+
+- Tape path can point to directory, archive or plain file.
+- Directory: all files in directory are included in virtual tape, ordered in whatever
+ order OS returns the directory (unless index.tape is found), emulated file mark
+ is between each file. Subdirectories are ignored.
+- Archive: All files in archive are included, including subdirectories.
+- Plain single file: tape only contains selected single file.
+- If directory or archive and index.tape is found, it is assumed to contain order of
+ files in virtual tape, plain file name strings separated by line feeds.
+- Writing is also supported if path points to a directory. Creates files named
+ xxxxx.tape where xxxxx is file number.
+- Tape ERASE command only deletes files that have extension .tape to prevent
+ accidental data loss. Subdirectories are also ignored.
+- Can be connected to SCSI hardware emulation (SCSI0-6) or uaescsi.device (UAE),
+ uaescsi.device unit number is always 4 or larger (if 4 was already used by
+ some CD device).
+- Tape change on the fly is supported.
+
+lua scripting:
+
+- very minimal and basic at the moment.
+- lua=<path to script> in config file, multiple files supported.
+- lua/default.lua is loaded by default.
+- supported UAE-specific functions:
+ uae_log, uae_read_u8, uae_read_u16, uae_peek_u16, uae_write_u8, uae_write_u16
+ uae_read_config, uae_write_config.
+- lua functions:
+ on_uae_vsync (every vsync)
+ on_uae_config_changed (any config value has changed)
+
+
2.6.1
Beta 4:
*/
#if 0
#include "hw/hw.h"
-#include "hw/pci/pci.h"
+#include "hw/pci/pci.h"6
#include "ui/console.h"
#include "vga_int.h"
#include "hw/loader.h"
*/
//#define DEBUG_CIRRUS
+//#define DEBUG_VGA_REG
//#define DEBUG_BITBLT
+#define TARGET_FMT_plx "%x"
/***************************************
*
if (((old_value & CIRRUS_BLT_RESET) != 0) &&
((reg_value & CIRRUS_BLT_RESET) == 0)) {
cirrus_bitblt_reset(s);
- } else if (((old_value & CIRRUS_BLT_START) == 0) &&
- ((reg_value & CIRRUS_BLT_START) != 0)) {
+ }
+ // Blitter will start if old = CIRRUS_BLT_RESET and new = CIRRUS_BLT_START. TW.
+ if (((old_value & CIRRUS_BLT_START) == 0) &&
+ ((reg_value & (CIRRUS_BLT_START | CIRRUS_BLT_RESET)) == CIRRUS_BLT_START)) {
cirrus_bitblt_start(s);
}
}
int width, height;
width = (s->cr[0x01] + 1) * 8;
- /* TW: if 16 bit mdoe but SR7 bit 7 == 0: 2x width and palette mode */
+ /* TW: if 16 bit mode but SR7 bit 7 == 0: 2x width and palette mode */
if ((cs->cirrus_hidden_dac_data & 0x80) == 0) {
switch (s->sr[0x07] & CIRRUS_SR7_BPP_MASK) {
case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
if (s->cirrus_hidden_dac_lockindex == 4) {
s->cirrus_hidden_dac_data = reg_value;
- s->vga.gr[5] |= 0x40;
+ //s->vga.gr[5] |= 0x40; /* TW */
#if defined(DEBUG_CIRRUS)
static void cirrus_vga_write_palette(CirrusVGAState * s, int reg_value)
{
-// if (s->vga.dac_write_index < 8)
-// write_log ("PAL: %d %d: %02X\n", s->vga.dac_write_index, s->vga.dac_sub_index, reg_value);
- s->vga.dac_cache[s->vga.dac_sub_index] = reg_value;
+#ifdef DEBUG_CIRRUS
+ if (s->vga.dac_write_index < 16)
+ write_log ("PAL: %d %d: %02X\n", s->vga.dac_write_index, s->vga.dac_sub_index, reg_value);
+#endif
+ s->vga.dac_cache[s->vga.dac_sub_index] = reg_value;
if (++s->vga.dac_sub_index == 3) {
if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
memcpy(&s->cirrus_hidden_palette[(s->vga.dac_write_index & 0x0f) * 3],
static void
cirrus_vga_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
{
-#if defined(DEBUG_BITBLT) && 0
- write_log("gr%02x: %02x\n", reg_index, reg_value);
+#if defined(DEBUG_CIRRUS)
+ if (reg_index > 1 && reg_index < 0x10)
+ write_log("gr%02x: %02x\n", reg_index, reg_value);
#endif
switch (reg_index) {
case 0x00: // Standard VGA, BGCOLOR 0x000000ff
void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr, hwaddr size)
{
}
-void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
-{
-}
-void memory_region_set_alias_offset(MemoryRegion *mr,
- hwaddr offset)
-{
-}
void memory_region_add_subregion(MemoryRegion *mr,
hwaddr offset,
MemoryRegion *subregion)
void memory_region_destroy(MemoryRegion *mr)
{
}
-void memory_region_init_alias(MemoryRegion *mr,
- const char *name,
- MemoryRegion *orig,
- hwaddr offset,
- uint64_t size)
-{
-}
void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
{
}
disp_width = width;
shift_control = (s->gr[VGA_GFX_MODE] >> 5) & 3;
+
+ // cirrus hack TW
+ if (s->sr[7] & 1)
+ shift_control = 2;
+
double_scan = (s->cr[VGA_CRTC_MAX_SCAN] >> 7);
if (shift_control != 1) {
multi_scan = (((s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1) << double_scan)
put_long (p + 10, ROM_netdev_resid);
put_long (p + 18, tmp1);
m68k_areg (regs, 1) = p;
- m68k_dreg (regs, 0) = 13; /* EXTER */
+ m68k_dreg (regs, 0) = 3; /* PORTS */
dw (0x4a80); /* TST.L D0 */
dw (0x4e75); /* RTS */
CallLib (ctx, get_long (4), -168); /* AddIntServer */
if (handleread (ctx, pdev, request, p->data, p->len, command)) {
if (log_net)
write_log (_T("-> %p Accepted, CMD_READ, REQ=%08X LEN=%d\n"), p, request, p->len);
+ ar->ready = 1;
write_comm_pipe_u32 (&dev->requests, request, 1);
dev->packetsreceived++;
gotit = 1;
if (log_net)
write_log (_T("-> %p Accepted, S2_READORPHAN, REQ=%08X LEN=%d\n"), p, request, p->len);
handleread (ctx, pdev, request, p->data, p->len, command);
+ ar->ready = 1;
write_comm_pipe_u32 (&dev->requests, request, 1);
dev->packetsreceived++;
dev->unknowntypesreceived++;
dev->online_micro = get_long (pdev->tempbuf + 4);
checkevents (dev, S2EVENT_ONLINE, 0);
dev->online = 1;
+ ar->ready = 1;
write_comm_pipe_u32 (&dev->requests, request, 1);
uaenet_vsync_requested--;
} else if (command == CMD_FLUSH) {
if (dev->ar->next == NULL) {
if (log_net)
write_log (_T("CMD_FLUSH replied %08x\n"), request);
+ ar->ready = 1;
write_comm_pipe_u32 (&dev->requests, request, 1);
uaenet_vsync_requested--;
} else {
p = restore_p96 (p);
#endif
len = restore_u32_func (&p);
- memcpy (chipmemory, p, currprefs.chipmem_size > len ? len : currprefs.chipmem_size);
+ memcpy (chipmem_bank.baseaddr, p, currprefs.chipmem_size > len ? len : currprefs.chipmem_size);
p += len;
len = restore_u32_func (&p);
memcpy (save_bram (&dummy), p, currprefs.bogomem_size > len ? len : currprefs.bogomem_size);
}
static void showsense(struct scsi_data *sd)
{
-#if 1
+#if 0
write_log (_T("REQUEST SENSE %d, "), sd->data_len);
for (int i = 0; i < sd->data_len; i++) {
if (i > 0)
int i, j;
put_long (place, version);
- put_long (place + 4, allocated_chipmem);
- put_long (place + 8, allocated_bogomem);
- put_long (place + 12, allocated_fastmem);
+ put_long (place + 4, chipmem_bank.allocated);
+ put_long (place + 8, bogomem_bank.allocated);
+ put_long (place + 12, fastmem_bank.allocated);
put_long (place + 16, currprefs.gfx_framerate);
put_long (place + 20, currprefs.produce_sound);
put_long (place + 24, currprefs.jports[0].id | (currprefs.jports[1].id << 8));
projects / francis / winuae.git / commitdiff