static char outbuffer[30000];
static int last_access_offset_ipl;
+static int last_access_offset_ipl_prev;
static void out(const char *format, ...)
{
last_access_offset_ipl = strlen(outbuffer);
}
+static void set_last_access_ipl_prev(void)
+{
+ last_access_offset_ipl_prev = strlen(outbuffer);
+}
+
+
NORETURN static void term (void)
{
out("Abort!\n");
static void check_ipl(void)
{
- set_last_access_ipl();
+ // So far it seems 68000 IPL fetch happens when CPU is doing
+ // memory cycle data part followed by prefetch cycle. It must
+ // happen after possible bus error has been detected but before
+ // following prefetch memory cycle.
+ if (last_access_offset_ipl_prev < 0) {
+ set_last_access_ipl();
+ } else {
+ // if memory cycle happened previously: use it.
+ last_access_offset_ipl = last_access_offset_ipl_prev;
+ ipl_fetched = 1;
+ }
}
static void check_ipl_always(void)
addmmufixup(reg, size, mode);
}
+ set_last_access_ipl_prev();
+
if (getv == 1) {
const char *srcbx = !(flags & GF_FC) ? srcb : "sfc_nommu_get_byte";
const char *srcwx = !(flags & GF_FC) ? srcw : "sfc_nommu_get_word";
check_address_error(to, mode, reg, size, 2, 0, flags);
}
+ set_last_access_ipl_prev();
+
switch (mode) {
case Dreg:
switch (size) {
fill_prefetch_next_after(0, NULL);
insn_n_cycles += 4;
}
+ set_last_access_ipl_prev();
out("%s(%sa, %s >> 16);\n", dstwx, to, from);
sprintf(tmp, "%s >> 16", from);
count_writew++;
if (flags & GF_SECONDWORDSETFLAGS) {
genflags(flag_logical, g_instr->size, "src", "", "");
}
+ set_last_access_ipl_prev();
out("%s(%sa + 2, %s);\n", dstwx, to, from);
count_writew++;
check_bus_error(to, 2, 1, 1, from, 1, pcoffset);
if (store_dir > 1) {
fill_prefetch_next_after(0, NULL);
}
+ set_last_access_ipl_prev();
out("%s(%sa, %s >> 16); \n", dstwx, to, from);
sprintf(tmp, "%s >> 16", from);
count_writew++;
if (flags & GF_SECONDWORDSETFLAGS) {
genflags(flag_logical, g_instr->size, "src", "", "");
}
+ set_last_access_ipl_prev();
out("%s(%sa + 2, %s); \n", dstwx, to, from);
count_writew++;
check_bus_error(to, 2, 1, 1, from, 1, pcoffset);
bus_error_code2[0] = 0;
opcode_nextcopy = 0;
last_access_offset_ipl = -1;
+ last_access_offset_ipl_prev = -1;
loopmode = 0;
// 68010 loop mode available if