regs.mmu_ssw |= read ? MMU030_SSW_RW : 0;
regs.mmu_ssw |= flags;
regs.mmu_ssw |= fc;
+ // store in wb3_data because stack frame creation may modify data buffer.
+ regs.wb3_data = mmu030_data_buffer_out;
bBusErrorReadWrite = read;
mm030_stageb_address = addr;
}
#endif
-#if 0
+#if MMU030_DEBUG
write_log(_T("%08x %08x %08x %08x %08x %d %d %d %08x %08x\n"),
mmu030_state[1], mmu030_state[2], mmu030_disp_store[0], mmu030_disp_store[1],
addr, read, size, fc, mmu030_data_buffer_out, mmu030_ad[idxsize].val);
mmu030_ad[idxsize].done = true;
}
} else {
- // NeXTstep 1.0a modifies DOB and it must be ignored.
- mmu030_data_buffer_out = mmu030_ad[mmu030_idx].val;
if (mmu030_state[1] & MMU030_STATEFLAG1_SUBACCESS0) {
mmu030_unaligned_write_continue(addr, fc, mmu030_put_generic);
} else {
}
#endif
if (!(ssw & MMU030_SSW_RW)) {
- // NeXTstep 1.0a modifies DOB so store value in storage too.
- mmu030_ad[mmu030_idx].val = mmu030_data_buffer_out;
+ mmu030_ad[mmu030_idx].val = regs.wb3_data;
}
for (i = 0; i < mmu030_idx + 1; i++) {
m68k_areg (regs, 7) -= 4;
x_put_long (m68k_areg (regs, 7), mmu030_disp_store[0]);
m68k_areg (regs, 7) -= 4;
// Data output buffer = value that was going to be written
- x_put_long (m68k_areg (regs, 7), mmu030_data_buffer_out);
+ x_put_long (m68k_areg (regs, 7), regs.wb3_data);
m68k_areg (regs, 7) -= 4;
x_put_long (m68k_areg (regs, 7), (mmu030_opcode & 0xffff) | (regs.prefetch020[0] << 16)); // Internal register (opcode storage)
m68k_areg (regs, 7) -= 4;