68030 MMU datacache mode LRMW support.

diff --git a/cpummu30.cpp b/cpummu30.cpp
index 7f0cf982d6c4550f679ae24c0bf64499382f5e84..77f0dde6df5c6e352ce36cbd0d29d36172dee81b 100644 (file)
--- a/cpummu30.cpp
+++ b/cpummu30.cpp
@@ -3001,17 +3001,21 @@ void m68k_do_rte_mmu030c (uaecptr a7)
 
                        if (read) {
                                uae_u32 val = 0;
-                               switch (size)
-                               {
-                                       case sz_byte:
-                                       val = read_dcache030_bget(addr, fc);
-                                       break;
-                                       case sz_word:
-                                       val = read_dcache030_wget(addr, fc);
-                                       break;
-                                       case sz_long:
-                                       val = read_dcache030_lget(addr, fc);
-                                       break;
+                               if (ssw & MMU030_SSW_RM) {
+                                       val = read_dcache030_lrmw_mmu_fcx(addr, size, fc);
+                               } else {
+                                       switch (size)
+                                       {
+                                               case sz_byte:
+                                               val = read_dcache030_bget(addr, fc);
+                                               break;
+                                               case sz_word:
+                                               val = read_dcache030_wget(addr, fc);
+                                               break;
+                                               case sz_long:
+                                               val = read_dcache030_lget(addr, fc);
+                                               break;
+                                       }
                                }
                                if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM1) {
                                        mmu030_data_buffer = val;
@@ -3027,17 +3031,21 @@ void m68k_do_rte_mmu030c (uaecptr a7)
                                        val = mdata;
                                else
                                        val = mmu030_ad[idxsize].val;
-                               switch (size)
-                               {
-                                       case sz_byte:
-                                       write_dcache030_bput(addr, val, fc);
-                                       break;
-                                       case sz_word:
-                                       write_dcache030_wput(addr, val, fc);
-                                       break;
-                                       case sz_long:
-                                       write_dcache030_lput(addr, val, fc);
-                                       break;
+                               if (ssw & MMU030_SSW_RM) {
+                                       write_dcache030_lrmw_mmu_fcx(addr, val, size, fc);
+                               } else {
+                                       switch (size)
+                                       {
+                                               case sz_byte:
+                                               write_dcache030_bput(addr, val, fc);
+                                               break;
+                                               case sz_word:
+                                               write_dcache030_wput(addr, val, fc);
+                                               break;
+                                               case sz_long:
+                                               write_dcache030_lput(addr, val, fc);
+                                               break;
+                                       }
                                }
                                if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM1) {
                                        mmu030_state[1] |= MMU030_STATEFLAG1_MOVEM2;

diff --git a/include/newcpu.h b/include/newcpu.h
index 572f41bb0df04d22d70f2744a11da89b34a7246d..f139275d172a4d8a37d56dbe217359236c5609ec 100644 (file)
--- a/include/newcpu.h
+++ b/include/newcpu.h
@@ -595,7 +595,9 @@ extern uae_u32 read_dcache030_mmu_bget(uaecptr);
 extern uae_u32 read_dcache030_mmu_wget(uaecptr);
 extern uae_u32 read_dcache030_mmu_lget(uaecptr);
 extern void write_dcache030_lrmw_mmu(uaecptr, uae_u32, uae_u32);
+extern void write_dcache030_lrmw_mmu_fcx(uaecptr, uae_u32, uae_u32, int);
 extern uae_u32 read_dcache030_lrmw_mmu(uaecptr, uae_u32);
+extern uae_u32 read_dcache030_lrmw_mmu_fcx(uaecptr, uae_u32, int);
 
 extern void check_t0_trace(void);
 extern uae_u32 get_word_icache030(uaecptr addr);

diff --git a/newcpu.cpp b/newcpu.cpp
index eadf10182738059cc2ab07d66ed4650a57864ab4..63ff67d19bf8dc1cb3a5ae390d6769d9023c3385 100644 (file)
--- a/newcpu.cpp
+++ b/newcpu.cpp
@@ -9994,15 +9994,15 @@ void write_dcache030_mmu_lput(uaecptr addr, uae_u32 val)
        write_dcache030_lput(addr, val, (regs.s ? 4 : 0) | 1);
 }
 
-uae_u32 read_dcache030_lrmw_mmu(uaecptr addr, uae_u32 size)
+uae_u32 read_dcache030_lrmw_mmu_fcx(uaecptr addr, uae_u32 size, int fc)
 {
        if (currprefs.cpu_data_cache) {
                mmu030_cache_state = CACHE_DISABLE_MMU;
                if (size == 0)
-                       return read_dcache030_bget(addr, (regs.s ? 4 : 0) | 1);
+                       return read_dcache030_bget(addr, fc);
                if (size == 1)
-                       return read_dcache030_wget(addr, (regs.s ? 4 : 0) | 1);
-               return read_dcache030_lget(addr, (regs.s ? 4 : 0) | 1);
+                       return read_dcache030_wget(addr, fc);
+               return read_dcache030_lget(addr, fc);
        } else {
                if (size == 0)
                        return read_data_030_bget(addr);
@@ -10011,16 +10011,20 @@ uae_u32 read_dcache030_lrmw_mmu(uaecptr addr, uae_u32 size)
                return read_data_030_lget(addr);
        }
 }
-void write_dcache030_lrmw_mmu(uaecptr addr, uae_u32 val, uae_u32 size)
+uae_u32 read_dcache030_lrmw_mmu(uaecptr addr, uae_u32 size)
+{
+       return read_dcache030_lrmw_mmu_fcx(addr, size, (regs.s ? 4 : 0) | 1);
+}
+void write_dcache030_lrmw_mmu_fcx(uaecptr addr, uae_u32 val, uae_u32 size, int fc)
 {
        if (currprefs.cpu_data_cache) {
                mmu030_cache_state = CACHE_DISABLE_MMU;
                if (size == 0)
-                       write_dcache030_bput(addr, val, (regs.s ? 4 : 0) | 1);
+                       write_dcache030_bput(addr, val, fc);
                else if (size == 1)
-                       write_dcache030_wput(addr, val, (regs.s ? 4 : 0) | 1);
+                       write_dcache030_wput(addr, val, fc);
                else
-                       write_dcache030_lput(addr, val, (regs.s ? 4 : 0) | 1);
+                       write_dcache030_lput(addr, val, fc);
        } else {
                if (size == 0)
                        write_data_030_bput(addr, val);
@@ -10030,6 +10034,10 @@ void write_dcache030_lrmw_mmu(uaecptr addr, uae_u32 val, uae_u32 size)
                        write_data_030_lput(addr, val);
        }
 }
+void write_dcache030_lrmw_mmu(uaecptr addr, uae_u32 val, uae_u32 size)
+{
+       write_dcache030_lrmw_mmu_fcx(addr, val, size, (regs.s ? 4 : 0) | 1);
+}
 
 static void do_access_or_bus_error(uaecptr pc, uaecptr pcnow)
 {