curr_color_changes[idx + 1].regno = -1;
}
record_color_change2 (hpos, regno, value);
+
+ if (regno == 0 && value != 0 && vpos >= 32) {
+ // autoscale if COLOR00 changes in top or bottom of screen
+ if (vpos < first_planes_vpos || vpos < plffirstline_total)
+ plffirstline_total = first_planes_vpos = vpos - 2;
+ if (vpos > last_planes_vpos || vpos > plflastline_total)
+ plflastline_total = last_planes_vpos = vpos + 3;
+ }
}
static void record_register_change (int hpos, int regno, unsigned long value)
uae_u16 old = intena;
setclr (&intena, v);
- if (old != intena || (v & 0x8000)) {
- if (use_eventmode ())
- event2_newevent_xx (-1, INT_PROCESSING_DELAY * CYCLE_UNIT, intena, send_intena_do);
- else
- send_intena_do (intena);
- }
+ if (use_eventmode ())
+ event2_newevent_xx (-1, INT_PROCESSING_DELAY * CYCLE_UNIT, intena, send_intena_do);
+ else
+ send_intena_do (intena);
#if 0
if (v & 0x40)
write_log (L"INTENA %04X (%04X) %p\n", intena, v, M68K_GETPC);
if (v & (0x0080 | 0x0100 | 0x0200 | 0x0400))
audio_update_irq (v);
- if (old != intreq || (v & 0x8000)) {
- if (use_eventmode ())
- event2_newevent_xx (-1, INT_PROCESSING_DELAY * CYCLE_UNIT, intreq, send_intreq_do);
- else
- send_intreq_do (intreq);
- }
+ if (use_eventmode ())
+ event2_newevent_xx (-1, INT_PROCESSING_DELAY * CYCLE_UNIT, intreq, send_intreq_do);
+ else
+ send_intreq_do (intreq);
}
void INTREQ (uae_u16 data)
decide_fetch (hpos);
}
+STATIC_INLINE void ipl_check (void)
+{
+ if (debug_dma) {
+ if (regs.ipl == regs.ipl_pin)
+ return;
+ regs.ipl = regs.ipl_pin;
+ record_dma_event (DMA_EVENT_INTREQ, current_hpos (), vpos);
+ } else {
+ regs.ipl = regs.ipl_pin;
+ }
+}
+
#define BLIT_NASTY 4
+static int ipl_checked;
+
// blitter not in nasty mode = CPU gets one cycle if it has been waiting
// at least 4 cycles (all DMA cycles count, not just blitter cycles, even
// blitter idle cycles do count!)
}
regs.ce020memcycles -= CYCLE_UNIT;
do_cycles (1 * CYCLE_UNIT);
+ if (!ipl_checked)
+ ipl_check ();
+ ipl_checked = 1;
/* bus was allocated to dma channel, wait for next cycle.. */
}
return hpos_old;
int hpos;
struct dma_rec *dr;
+ ipl_checked = 0;
hpos = dma_cycle ();
- regs.ipl = regs.ipl_pin;
do_cycles_ce (CYCLE_UNIT);
+ if (!ipl_checked)
+ ipl_check ();
#ifdef DEBUGGER
if (debug_dma) {
{
int hpos;
+ ipl_checked = 0;
hpos = dma_cycle ();
- regs.ipl = regs.ipl_pin;
do_cycles_ce (CYCLE_UNIT);
+ if (!ipl_checked)
+ ipl_check ();
#ifdef DEBUGGER
if (debug_dma) {
ret = -1;
if (doublescan <= 0) {
- if (diwfirstword_total < (48 << currprefs.gfx_resolution))
- diwfirstword_total = 48 << currprefs.gfx_resolution;
- if (diwlastword_total > (448 << currprefs.gfx_resolution))
- diwlastword_total = 448 << currprefs.gfx_resolution;
+ int min = coord_diw_to_window_x (116);
+ int max = coord_diw_to_window_x (460);
+ if (diwfirstword_total < min)
+ diwfirstword_total = min;
+ if (diwlastword_total > max)
+ diwlastword_total = max;
ddffirstword_total = coord_hw_to_window_x (ddffirstword_total * 2 + DIW_DDF_OFFSET);
ddflastword_total = coord_hw_to_window_x (ddflastword_total * 2 + DIW_DDF_OFFSET);
- if (ddffirstword_total < (48 << currprefs.gfx_resolution))
- ddffirstword_total = 48 << currprefs.gfx_resolution;
- if (ddflastword_total > (448 << currprefs.gfx_resolution))
- ddflastword_total = 448 << currprefs.gfx_resolution;
+ if (ddffirstword_total < min)
+ ddffirstword_total = min;
+ if (ddflastword_total > max)
+ ddflastword_total = max;
if (0 && !(currprefs.chipset_mask & CSMASK_AGA)) {
if (ddffirstword_total > diwfirstword_total)
diwfirstword_total = ddffirstword_total;
// handle interrupt delay (few cycles)
STATIC_INLINE int time_for_interrupt (void)
{
- if (regs.ipl > 0 && (regs.ipl > regs.intmask || regs.ipl == 7)) {
+ if (regs.ipl > regs.intmask || regs.ipl == 7) {
#if 0
if (regs.ipl == 3 && current_hpos () < 11) {
write_log (L"%d\n", current_hpos ());
{
if (currprefs.cpu_cycle_exact) {
int newipl = intlev ();
-
- if (newipl == regs.ipl_pin)
- return;
regs.ipl_pin = newipl;
if (currprefs.cpu_model != 68000)
regs.ipl = regs.ipl_pin;
di->lun = 0;
di->media_inserted = 0;
di->bytespersector = 2048;
- _stprintf (di->mediapath, L"\\\\.\\%s", ciw32[unitnum].drvletter);
+ _stprintf (di->mediapath, L"\\\\.\\%c:", ciw32[unitnum].drvletter);
if (fetch_geometry (unitnum, di)) { // || ioctl_command_toc (unitnum))
di->media_inserted = 1;
ciw32[unitnum].blocksize = di->bytespersector;
#define WINUAEPUBLICBETA 1
#define LANG_DLL 1
-#define WINUAEBETA L"8"
-#define WINUAEDATE MAKEBD(2010, 2, 6)
+#define WINUAEBETA L"9"
+#define WINUAEDATE MAKEBD(2010, 2, 7)
#define WINUAEEXTRA L""
#define WINUAEREV L""
DWORD dwDriveMask;
int drvnum = 0;
+ if (!currprefs.win32_automount_cddrives && !currprefs.win32_automount_netdrives
+ && !currprefs.win32_automount_drives && !currprefs.win32_automount_removabledrives)
+ return;
errormode = SetErrorMode (SEM_FAILCRITICALERRORS | SEM_NOOPENFILEERRORBOX);
dwDriveMask = GetLogicalDrives ();
dwDriveMask >>= 2; // Skip A and B drives...
if (item != CB_ERR) {
workprefs.gfx_filter_autoscale = item;
if (workprefs.gfx_filter_autoscale && workprefs.gfx_filter == 0) {
- if (D3D_goodenough ()) {
- workprefs.gfx_filter = 2; // D3D
- workprefs.gfx_filter_filtermode = 2;
- } else {
+ if (!workprefs.gfx_api)
workprefs.gfx_filter = 1; // NULL
- }
}
values_to_hw3ddlg (hDlg);
enable_for_hw3ddlg (hDlg);
+Beta 9:
+
+- CE 68000 interrupt handling update, Spectre Party Demo /
+ Phenomena works without jumping
+- autoscale left and right border position restricted to sane max
+ overscan values
+- enabling autoscale changed filter mode to scale2x
+- autoscale detects COLOR00 (background color) changes outside of
+ bitplane area
+- do not enumerate drives if every "Include .. drives" is not ticked
+- CD32/CDTV crash fix (IOCTL CD crash) (b8?)
+
Beta 8:
- do not use D3D9Ex if no v3 shader or dynamic texture support
put_byte (request + 31, 32);
return get_byte (request + 31);
}
- put_byte (request+31, 0);
+ put_byte (request + 31, 0);
if ((flags & 1) && dev_canquick (dev, request)) {
if (dev_do_io (dev, request))
write_log (L"device %s command %d bug with IO_QUICK\n", getdevname (pdev->type), command);
return get_byte (request + 31);
} else {
add_async_request (dev, request, ASYNC_REQUEST_TEMP, 0);
- put_byte (request+30, get_byte (request + 30) & ~1);
+ put_byte (request + 30, get_byte (request + 30) & ~1);
write_comm_pipe_u32 (&dev->requests, request, 1);
return 0;
}