},
{
GFXBOARD_ID_RETINA_Z2,
- _T("Retina [Zorro II]"), _T("Macro System"), _T("Retina_Z2"),
+ _T("Retina [Zorro II]"), _T("MacroSystem"), _T("Retina_Z2"),
18260, 6, 0, 0,
0x00000000, 0x00100000, 0x00400000, 0x00020000, 0, 2, 2, false, false,
0, 0, NULL, &ncr_retina_z2_device
},
{
GFXBOARD_ID_RETINA_Z3,
- _T("Retina [Zorro III]"), _T("Macro System"), _T("Retina_Z3"),
+ _T("Retina [Zorro III]"), _T("MacroSystem"), _T("Retina_Z3"),
18260, 16, 0, 0,
0x00000000, 0x00100000, 0x00400000, 0x00400000, 0, 3, 2, false, false,
0, 0, NULL, &ncr_retina_z3_device
{
case 0x11:
if (!(val & 0x10)) {
- if (ncr->vblank_irq > 0)
- ncr->vblank_irq = -1;
- } else if (ncr->vblank_irq < 0) {
ncr->vblank_irq = 0;
}
ncr_update_irqs(ncr);
dst /= 3;
int off = dst & 3;
int rgboff = 0;
- if (off == 2) {
+ if (off == 1) {
+ rgboff = 3;
+ } else if (off == 2) {
rgboff = 5;
} else if (off == 3) {
rgboff = 10;
}
int mode = svga->seqregs[0x1e] >> 5;
if (mode != 2 && mode != 3 && mode != 6) {
- pclog("unsupport banking mode %d\n", mode);
+ pclog("unsupported banking mode %d\n", mode);
}
// Primary at A0000h-AFFFFh, Secondary at B0000h-BFFFFh. Both Read / Write.
if (mode == 2) {
}
svga->vblank_start = ncr_vblank_start;
- ncr->vblank_irq = -1;
ncr_io_set(ncr);
bool svga_on(void *p)
{
svga_t *svga = (svga_t*)p;
- return svga->scrblank == 0 && svga->hdisp >= 128;
+ return svga->scrblank == 0 && svga->hdisp >= 128 && (svga->crtc[0x17] & 0x80);
}
int svga_get_vtotal(void *p)
svga->vgapal[svga->dac_write].r = svga->dac_r;
svga->vgapal[svga->dac_write].g = svga->dac_g;
svga->vgapal[svga->dac_write].b = val;
+ //pclog("%d: %02x %02x %02x\n", svga->dac_write, svga->dac_r, svga->dac_g, val);
if (svga->ramdac_type == RAMDAC_8BIT)
svga->pallook[svga->dac_write] = makecol32(svga->vgapal[svga->dac_write].r, svga->vgapal[svga->dac_write].g, svga->vgapal[svga->dac_write].b);
else
}
if (svga->vc == svga->dispend)
{
- if (svga->vblank_start)
+ if (svga->vblank_start && (svga->crtc[0x17] & 0x80))
svga->vblank_start(svga);
// pclog("VC dispend\n");
svga->dispon=0;