out("uae_s32 %s = %s(%sa + 2);\n", name, srcwx, name);
count_readw++;
check_bus_error(name, 0, 0, 1, NULL, 1, 0);
+ set_last_access_ipl_prev();
out("%s |= %s(%sa) << 16; \n", name, srcwx, name);
count_readw++;
check_bus_error(name, -2, 0, 1, NULL, 1, 0);
out("uae_s32 %s = %s(%sa) << 16;\n", name, srcwx, name);
count_readw++;
check_bus_error(name, 0, 0, 1, NULL, 1, 0);
+ set_last_access_ipl_prev();
out("%s |= %s(%sa + 2); \n", name, srcwx, name);
count_readw++;
check_bus_error(name, 2, 0, 1, NULL, 1, 0);
check_address_error(to, mode, reg, size, 2, 0, flags);
}
- set_last_access_ipl_prev();
-
switch (mode) {
case Dreg:
switch (size) {
const char *dstbx = !(flags & GF_FC) ? dstb : "dfc_nommu_put_byte";
const char *dstwx = !(flags & GF_FC) ? dstw : "dfc_nommu_put_word";
const char *dstlx = !(flags & GF_FC) ? dstl : "dfc_nommu_put_long";
+
+ set_last_access_ipl_prev();
if (!(flags & GF_NOFAULTPC))
gen_set_fault_pc (false, false);
if (using_mmu) {
if (table68k[opcode].dmode == Aipi) {
out("m68k_areg(regs, dstreg) = srca;\n");
}
+ set_last_access_ipl_prev();
if (cpu_level <= 1) {
out("%s(srca);\n", srcw); // and final extra word fetch that goes nowhere..
count_readw++;
out("amask = movem_next[amask];\n");
out("}\n");
}
+ set_last_access_ipl_prev();
out("%s(srca);\n", srcw); // and final extra word fetch that goes nowhere..
count_readw++;
check_bus_error("src", 0, 0, 1, NULL, 1, -1);
next_level_020_to_010();
}
count_ncycles++;
+ set_last_access_ipl_prev();
fill_prefetch_next_t();
get_prefetch_020();
}
}
}
count_ncycles++;
+ set_last_access_ipl_prev();
fill_prefetch_next_t();
}