Assume TAS is supported if not chip bus access.

diff --git a/cputest.cpp b/cputest.cpp
index 6bd63b37ede3e7bab60acdc2833e4cfa4cb0b4c0..ce3ba0d7031dca9b783702deb34b2c66aa0ac110 100644 (file)
--- a/cputest.cpp
+++ b/cputest.cpp
@@ -679,7 +679,7 @@ bool mmu_op30(uaecptr pc, uae_u32 opcode, uae_u16 extra, uaecptr extraa)
        return true;
 }
 
-int is_cycle_ce(void)
+bool is_cycle_ce(uaecptr addr)
 {
        return 0;
 }

diff --git a/custom.cpp b/custom.cpp
index 9827691342de426ef8c6215efd83229c2877ca00..cad7516ec8fa5db4c7e34447c7c557eff18b347a 100644 (file)
--- a/custom.cpp
+++ b/custom.cpp
@@ -11843,10 +11843,14 @@ void do_cycles_ce020 (unsigned long cycles)
 }
 
 
-int is_cycle_ce (void)
+bool is_cycle_ce(uaecptr addr)
 {
-       int hpos = current_hpos ();
-       return cycle_line[hpos] & CYCLE_MASK;
+       addrbank *ab = get_mem_bank_real(addr);
+       if ((ab->flags & ABFLAG_CHIPRAM) || ab == &custom_bank) {
+               int hpos = current_hpos();
+               return (cycle_line[hpos] & CYCLE_MASK) != 0;
+       }
+       return 0;
 }
 
 #endif

diff --git a/gencpu.cpp b/gencpu.cpp
index 8e4218afce5ee5a3b41edf418d4867a62400c082..1f25fc7ab2288b691834b03d8c0522c05d389fbd 100644 (file)
--- a/gencpu.cpp
+++ b/gencpu.cpp
@@ -8025,7 +8025,7 @@ bccl_not68020:
                        if (isreg(curi->smode) || !using_ce) {
                                genastore_tas("src", curi->smode, "srcreg", curi->size, "src");
                        } else {
-                               out("if (!is_cycle_ce()) {\n");
+                               out("if (!is_cycle_ce(srca)) {\n");
                                genastore("src", curi->smode, "srcreg", curi->size, "src");
                                out("} else {\n");
                                out("%s(4);\n", do_cycles);
@@ -8048,7 +8048,7 @@ bccl_not68020:
                        if (isreg(curi->smode) || !using_ce) {
                                genastore_tas("src", curi->smode, "srcreg", curi->size, "src");
                        } else {
-                               out("if (!is_cycle_ce()) {\n");
+                               out("if (!is_cycle_ce(srca)) {\n");
                                genastore("src", curi->smode, "srcreg", curi->size, "src");
                                out("} else {\n");
                                out("%s(4);\n", do_cycles);

diff --git a/include/events.h b/include/events.h
index ee580416ac643f9042e0f42fb1f565421cf6d074..1ea2eda509d6448d0e69562f52c4063757ca0974 100644 (file)
--- a/include/events.h
+++ b/include/events.h
@@ -35,7 +35,7 @@ extern void events_schedule (void);
 extern void do_cycles_slow (unsigned long cycles_to_add);
 extern void events_reset_syncline(void);
 
-extern int is_cycle_ce (void);
+extern bool is_cycle_ce(uaecptr);
 
 extern unsigned long currcycle, nextevent;
 extern int is_syncline, is_syncline_end;