p->sound_filter_type = FILTER_SOUND_TYPE_A1200;
else if (p->sound_filter_type == FILTER_SOUND_TYPE_A1200 && !(p->chipset_mask & CSMASK_AGA))
p->sound_filter_type = FILTER_SOUND_TYPE_A500;
+ if (p->cpu_model >= 68040)
+ p->cs_bytecustomwritebug = true;
return v;
}
p->cs_slowmemisfast = 0;
p->cs_ciatodbug = false;
p->cs_z3autoconfig = false;
+ p->cs_bytecustomwritebug = false;
switch (p->cs_compatible)
{
p->cs_z3autoconfig = true;
break;
}
+ if (p->cpu_model >= 68040)
+ p->cs_bytecustomwritebug = true;
return 1;
}
refptr = v;
refptr_val = (v & 0xfe00) | ((v & 0x01fe) >> 1);
if (v & 1) {
- v |= 0x80 << 9;
+ refptr_val |= 0x80 << 9;
}
if (v & 2) {
refptr_val |= 1;
// CPU in STOP state: sleep if enough time left.
frame_time_t rpt = read_processor_time ();
while (!vsync_isdone () && (int)vsyncmintime - (int)(rpt + vsynctimebase / 10) > 0 && (int)vsyncmintime - (int)rpt < vsynctimebase) {
- cpu_sleep_millis(1);
+ if (!execute_other_cpu(rpt + vsynctimebase / 10))
+ cpu_sleep_millis(1);
rpt = read_processor_time ();
}
} else if (currprefs.m68k_speed_throttle) {
frame_time_t rpt = read_processor_time ();
// sleep if more than 2ms "free" time
while (!vsync_isdone () && (int)vsyncmintime - (int)(rpt + vsynctimebase / 10) > 0 && (int)vsyncmintime - (int)rpt < vsynctimebase) {
- cpu_sleep_millis(1);
+ if (!execute_other_cpu(rpt + vsynctimebase / 10))
+ cpu_sleep_millis(1);
rpt = read_processor_time ();
//write_log (_T("*"));
}
#ifdef JIT
special_mem |= S_WRITE;
#endif
- if (currprefs.cpu_model == 68060) {
+ if (currprefs.cs_bytecustomwritebug) {
if (addr & 1)
custom_wput (addr & ~1, rval);
else
int revolutions;
int prevtracklen;
int trackspeed;
- int num_tracks, write_num_tracks, num_secs;
+ int num_tracks, write_num_tracks, num_secs, num_heads;
int hard_num_cyls;
bool dskeject;
bool dskchange;
if (drv->forcedwrprot)
drv->wrprot = true;
drv->ddhd = 1;
+ drv->num_heads = 2;
drv->num_secs = 0;
drv->hard_num_cyls = p->floppyslots[dnum].dfxtype == DRV_525_SD ? 40 : 80;
drv->tracktiming[0] = 0;
} else if (canauto && (
- // double sided
+ // 320k double sided
+ size == 8 * 40 * 2 * 512 ||
+ // 320k single sided
+ size == 8 * 40 * 1 * 512 ||
+
+ // 360k double sided
size == 9 * 40 * 2 * 512 ||
- // single sided
+ // 360k single sided
size == 9 * 40 * 1 * 512 ||
- // double sided
+ // 1.2M double sided
+ size == 15 * 80 * 2 * 512 ||
+
+ // 720k/1440k double sided
size == 9 * 80 * 2 * 512 || size == 18 * 80 * 2 * 512 || size == 10 * 80 * 2 * 512 || size == 20 * 80 * 2 * 512 ||
size == 9 * 81 * 2 * 512 || size == 18 * 81 * 2 * 512 || size == 10 * 81 * 2 * 512 || size == 20 * 81 * 2 * 512 ||
size == 9 * 82 * 2 * 512 || size == 18 * 82 * 2 * 512 || size == 10 * 82 * 2 * 512 || size == 20 * 82 * 2 * 512 ||
- // single sided
+ // 720k/1440k single sided
size == 9 * 80 * 1 * 512 || size == 18 * 80 * 1 * 512 || size == 10 * 80 * 1 * 512 || size == 20 * 80 * 1 * 512 ||
size == 9 * 81 * 1 * 512 || size == 18 * 81 * 1 * 512 || size == 10 * 81 * 1 * 512 || size == 20 * 81 * 1 * 512 ||
size == 9 * 82 * 1 * 512 || size == 18 * 82 * 1 * 512 || size == 10 * 82 * 1 * 512 || size == 20 * 82 * 1 * 512)) {
/* PC formatted image */
int i, side;
+ drv->num_secs = 9;
+ drv->ddhd = 1;
+
for (side = 2; side > 0; side--) {
if ( size == 9 * 80 * side * 512 || size == 9 * 81 * side * 512 || size == 9 * 82 * side * 512) {
drv->num_secs = 9;
drv->num_secs = 9;
drv->ddhd = 1;
break;
+ } else if (size == 8 * 40 * side * 512) {
+ drv->num_secs = 8;
+ drv->ddhd = 1;
+ break;
+ } else if (size == 15 * 80 * side * 512) {
+ drv->num_secs = 15;
+ drv->ddhd = 1;
+ break;
}
}
+
drv->num_tracks = size / (drv->num_secs * 512);
drv->filetype = ADF_PCDOS;
tid++;
}
+ drv->num_heads = side;
if (side == 1)
drv->num_tracks *= 2;
drive *drv = &floppy[i];
reserved_side = head;
drv->cyl = cyl;
- drv->state = motor;
+ drv->state = motor != 0;
update_drive_gui(i, false);
}
}
fr->cyls = drv->num_tracks / 2;
fr->drive_cyls = currprefs.floppyslots[i].dfxtype == DRV_PC_ONLY_40 ? 40 : 80;
fr->secs = drv->num_secs;
- fr->heads = 2;
+ fr->heads = drv->num_heads;
fr->disk_changed = drv->dskchange || fr->img == NULL;
if (currprefs.floppyslots[i].dfxtype == DRV_PC_ONLY_80) {
if (fr->cyls < 80) {
- // 360k in 80 track drive
- fr->rate = FLOPPY_RATE_300K;
+ if (drv->num_secs < 9)
+ fr->rate = FLOPPY_RATE_250K; // 320k in 80 track drive
+ else
+ fr->rate = FLOPPY_RATE_300K; // 360k in 80 track drive
} else {
if (drv->num_secs > 14)
- fr->rate = FLOPPY_RATE_500K; // 1.4M
+ fr->rate = FLOPPY_RATE_500K; // 1.2M/1.4M
else
fr->rate = FLOPPY_RATE_250K; // 720K
}
} else {
- fr->rate = FLOPPY_RATE_300K;
+ if (drv->num_secs < 9)
+ fr->rate = FLOPPY_RATE_300K;// 320k in 40 track drive
+ else
+ fr->rate = FLOPPY_RATE_250K;// 360k in 40 track drive
+ // yes, above values are swapped compared to 1.2M drive case
}
return true;
}
extern double vblank_hz;
extern unsigned long int timeframes;
extern int vpos;
+extern bool x86_turbo_on;
Bitu cmos_readreg(Bitu port,Bitu iolen) {
#if 0
return 0xff;
}
#endif
- Bitu drive_a, drive_b;
- Bit8u hdparm;
time_t curtime;
struct tm *loctime;
int reg = cmos.reg;
case 0x05: /* Hours Alarm */
return cmos.regs[reg];
case 0x0a: /* Status register A */
- if (vblank_hz > 0 && (timeframes % (int)vblank_hz) == 0 && vpos == 0) { // && PIC_TickIndex()<0.002) {
- return (cmos.regs[0x0a]&0x7f) | 0x80;
+ if (x86_turbo_on) {
+ static bool toggle;
+ toggle = !toggle;
+ if (toggle) {
+ return (cmos.regs[0x0a] & 0x7f) | 0x80;
+ } else {
+ return (cmos.regs[0x0a] & 0x7f);
+ }
} else {
- return (cmos.regs[0x0a]&0x7f);
+ if (vblank_hz > 0 && (timeframes % (int)vblank_hz) == 0 && vpos == 0) { // && PIC_TickIndex()<0.002) {
+ return (cmos.regs[0x0a]&0x7f) | 0x80;
+ } else {
+ return (cmos.regs[0x0a]&0x7f);
+ }
}
case 0x0c: /* Status register C */
cmos.timer.acknowledged=true;
#include "memory.h"
#include "newcpu.h"
#include "uae/ppc.h"
+#include "x86.h"
static const int pissoff_nojit_value = 256 * CYCLE_UNIT;
void do_cycles_slow (unsigned long cycles_to_add)
{
+#ifdef WITH_X86
+ if (x86_turbo_on) {
+ execute_other_cpu_single();
+ }
+#endif
+
if ((pissoff -= cycles_to_add) >= 0)
return;
static const struct expansionboardsettings x86at_bridge_settings[] = {
{
// 14
- _T("Default video\0Monochrome\0Color\0"),
- _T("video\0mono\0color\0"),
+ _T("Default video\0") _T("Monochrome\0") _T("Color\0"),
+ _T("video\0") _T("mono\0") _T("color\0"),
true, false, 14
},
{
false
},
{ // 16 - 18
- _T("Memory\0""1M\0""2M\0""4M\0""8M\0""16M\0""32M\0"),
- _T("memory\0""1M\0""2M\0""4M\0""8M\0""16M\0""32M\0"),
+ _T("Memory\0") _T("1M\0") _T("2M\0") _T("4M\0") _T("8M\0") _T("16M\0") _T("32M\0"),
+ _T("memory\0") _T("1M\0") _T("2M\0") _T("4M\0") _T("8M\0") _T("16M\0") _T("32M\0"),
true, false, 0
},
{ // 19 - 20
- _T("CPU core\0DOSBox simple\0DOSBox normal\0DOSBox full\0DOSBox auto"),
- _T("cpu\0dbsimple\0dbnormal\0dbfull\0dbauto\0"),
+ _T("CPU core\0") _T("DOSBox simple\0") _T("DOSBox normal\0") _T("DOSBox full\0") _T("DOSBox auto\0"),
+ _T("cpu\0") _T("dbsimple\0") _T("dbnormal\0") _T("dbfull\0") _T("dbauto\0"),
true, false, 0
},
{ // 22
static const struct expansionboardsettings x86_bridge_settings[] = {
{
// 2-3
- _T("Memory (SW1:3-4)\0""128K\0""256K\0""512K\0""640K\0"),
- _T("memory\0""128k\0""256k\0""512k\0""640k\0"),
+ _T("Memory (SW1:3-4)\0") _T("128K\0") _T("256K\0") _T("512K\0") _T("640K\0"),
+ _T("memory\0") _T("128k\0") _T("256k\0") _T("512k\0") _T("640k\0"),
true, false, 2
},
{
// 4-5
- _T("Default video (J1)\0Monochrome\0Color 40x25\0Color 80x25\0None\0"),
- _T("video\0mono\0color40\0color80\0none\0"),
+ _T("Default video (J1)\0") _T("Monochrome\0") _T("Color 40x25\0") _T("Color 80x25\0") _T("None\0"),
+ _T("video\0") _T("mono\0") _T("color40\0") _T("color80\0") _T("none\0"),
true, false, 0
},
{ // 19 - 21
- _T("CPU core\0Fake86\0DOSBox simple\0DOSBox normal\0DOSBox full\0DOSBox auto\0"),
- _T("cpu\0fake86\0dbsimple\0dbnormal\0dbfull\0dbauto\0"),
+ _T("CPU core\0") _T("Fake86\0") _T("DOSBox simple\0") _T("DOSBox normal\0") _T("DOSBox full\0") _T("DOSBox auto\0"),
+ _T("cpu\0") _T("fake86\0") _T("dbsimple\0") _T("dbnormal\0") _T("dbfull\0") _T("dbauto\0"),
true, false, 19 - 6
},
{ // 22
},
{
// 2-3
- _T("Memory (SW1:3-4)\0""128K\0""256K\0""512K\0""640K\0"),
- _T("memory\0""128k\0""256k\0""512k\0""640k\0"),
+ _T("Memory (SW1:3-4)\0") _T("128K\0") _T("256K\0") _T("512K\0") _T("640K\0"),
+ _T("memory\0") _T("128k\0") _T("256k\0") _T("512k\0") _T("640k\0"),
true
},
{
// 4-5
- _T("Default video (SW1:5-6)\0Monochrome\0Color 40x25\0Color 80x25\0None\0"),
- _T("video\0mono\0color40\0color80\0none\0"),
+ _T("Default video (SW1:5-6)\0") _T("Monochrome\0") _T("Color 40x25\0") _T("Color 80x25\0") _T("None\0"),
+ _T("video\0") _T("mono\0") _T("color40\0") _T("color80\0") _T("none\0"),
true
},
{
// 6-7
- _T("Floppy drives (SW1:7-8)\0""1\0""2\0""3\0""4\0"),
- _T("floppy\0""floppy1\0""floppy2\0""floppy3\0""floppy4\0"),
+ _T("Floppy drives (SW1:7-8)\0") _T("1\0") _T("2\0") _T("3\0") _T("4\0"),
+ _T("floppy\0") _T("floppy1\0") _T("floppy2\0") _T("floppy3\0") _T("floppy4\0"),
true
},
{
},
{
// 10-11
- _T("Address sector (SW2:3-4)\0A0000-AFFFF (1)\0A0000-AFFFF (2)\0D0000-DFFFF\0E0000-EFFFF\0"),
- _T("memory\0sector_a0000_1\0sector_a0000_2\0sector_d0000\0sector_e0000\0"),
+ _T("Address sector (SW2:3-4)\0") _T("A0000-AFFFF (1)\0") _T("A0000-AFFFF (2)\0") _T("D0000-DFFFF\0") _T("E0000-EFFFF\0"),
+ _T("memory\0") _T("sector_a0000_1\0") _T("sector_a0000_2\0") _T("sector_d0000\0") _T("sector_e0000\0"),
true
},
{
_T("parport_card")
},
{ // 19 - 22
- _T("CPU core\0Fake86\0DOSBox simple\0DOSBox normal\0DOSBox full\0DOSBox auto\0"),
- _T("cpu\0fake86\0dbsimple\0dbnormal\0dbfull\0dbauto\0"),
+ _T("CPU core\0") _T("Fake86\0") _T("DOSBox simple\0") _T("DOSBox normal\0") _T("DOSBox full\0") _T("DOSBox auto\0"),
+ _T("cpu\0") _T("fake86\0") _T("dbsimple\0") _T("dbnormal\0") _T("dbfull\0") _T("dbauto\0"),
true, false, 19 - 13
},
{
},
#endif
{
- _T("x86_at_hd_1"), _T("x86 AT IDE Primary"), _T("x86"),
+ _T("x86athdprimary"), _T("AT IDE Primary"), _T("x86"),
x86_at_hd_init_1, NULL, x86_add_at_hd_unit_1, ROMTYPE_X86_AT_HD1 | ROMTYPE_NOT, 0, 0, BOARD_NONAUTOCONFIG, true,
NULL, 0,
false, EXPANSIONTYPE_IDE
},
{
- _T("x86_at_hd_2"), _T("x86 AT IDE Secondary"), _T("x86"),
+ _T("x86athdsecondary"), _T("AT IDE Secondary"), _T("x86"),
x86_at_hd_init_2, NULL, x86_add_at_hd_unit_2, ROMTYPE_X86_AT_HD2 | ROMTYPE_NOT, 0, 0, BOARD_NONAUTOCONFIG, true,
NULL, 0,
false, EXPANSIONTYPE_IDE
},
{
- _T("x86_at_hd_xt"), _T("x86 XTIDE Universal BIOS HD"), _T("x86"),
+ _T("x86athdxt"), _T("XTIDE Universal BIOS HD"), _T("x86"),
x86_at_hd_init_xt, NULL, x86_add_at_hd_unit_xt, ROMTYPE_X86_XT_IDE | ROMTYPE_NONE, 0, 0, BOARD_NONAUTOCONFIG, true,
NULL, 0,
false, EXPANSIONTYPE_IDE
false, EXPANSIONTYPE_RTG,
},
{
- _T("x86_vga"), _T("x86 VGA"), _T("x86"),
+ _T("x86vga"), _T("x86 VGA"), _T("x86"),
NULL, NULL, NULL, ROMTYPE_x86_VGA | ROMTYPE_NONE, 0, 0, BOARD_IGNORE, true,
NULL, 0,
false, EXPANSIONTYPE_RTG,
; 164: input.device ioreq (disk inserted/removed input message)
; 168: timer.device ioreq
; 172: disk change from host
- ; 173: clock reset
+ ; 173: bit 0: clock reset, bit 1: debugger start
; 176: my task
; 180: device node
move.l #12+20+(80+44+1)+(1+3)+4+4+4+(1+3)+4+4,d0
.msg
; SIGBREAK_CTRL_D checks
; clock reset
- tst.b 173(a3)
+ btst #0,173(a3)
beq.s .noclk
bsr.w clockreset
- clr.b 173(a3)
+ bclr #0,173(a3)
.noclk
+ btst #1,173(a3)
+ beq.s .nodebug
+ bsr.w debuggerstart
+ bclr #1,173(a3)
+.nodebug
; disk change notification from native code
tst.b 172(a3)
beq.s .nodc
asl.l #8,d0
move.l d0,(a1)+
.noax
- move.w MH_MAXAY++MH_DATA(a5),d0
+ move.w MH_MAXAY+MH_DATA(a5),d0
bmi.s .noay
move.l #TABLETA_AngleY,(a1)+
move.w MH_AY+MH_DATA(a5),d0
asl.l #8,d0
move.l d0,(a1)+
.noay
- move.w MH_MAXAZ++MH_DATA(a5),d0
+ move.w MH_MAXAZ+MH_DATA(a5),d0
bmi.s .noaz
move.l #TABLETA_AngleZ,(a1)+
move.w MH_AZ+MH_DATA(a5),d0
movem.l (sp)+,d0-d1/a0
rts
+debuggerstart
+ move.l 4.w,a6
+ lea debuggerprocname(pc),a0
+ lea debuggerproc(pc),a1
+ moveq #15,d0
+ move.l #8000,d1
+ bsr.w createproc
+ rts
+ cnop 0,4
+ dc.l 16
+debuggerproc
+ dc.l 0
+ move.l 4.w,a6
+ moveq #0,d0
+ lea doslibname(pc),a1
+ jsr -$0228(a6) ; OpenLibrary
+ moveq #2,d1
+ move.w #$FF3C,d0
+ bsr.w getrtbase
+ move.l a0,a2
+ moveq #1,d1
+ jsr (a0) ; debugger init
+ tst.l d1
+ beq.s .dend
+ move.l d1,a3
+ jsr -$1f8(a6) ; RunCommand
+ moveq #2,d1
+ move.l a3,a0
+ jsr (a2) ; debugger end
+.dend
+ move.l a6,a1
+ move.l 4.w,a6
+ jsr -$19e(a6)
+ rts
+
getrtbase:
lea start-8-4(pc),a0
and.l #$FFFF,d0
exter_name: dc.b 'UAE filesystem',0
fstaskname: dc.b 'UAE fs automounter',0
fsprocname: dc.b 'UAE fs automount process',0
+debuggerprocname: dc.b 'UAE debugger',0
doslibname: dc.b 'dos.library',0
intlibname: dc.b 'intuition.library',0
gfxlibname: dc.b 'graphics.library',0
void cpu_semaphore_get(void);
void cpu_semaphore_release(void);
+bool execute_other_cpu(int until);
+void execute_other_cpu_single(void);
bool cs_z3autoconfig;
bool cs_1mchipjumper;
bool cs_cia6526;
+ bool cs_bytecustomwritebug;
int cs_hacks;
struct boardromconfig expansionboard[MAX_EXPANSION_BOARDS];
#define X86_STATE_ACTIVE 2
int is_x86_cpu(struct uae_prefs*);
+void x86_bridge_execute_until(int until);
+extern bool x86_turbo_on;
static void inputdevice_mh_abs (int x, int y, uae_u32 buttonbits)
{
- uae_u8 *p;
-
x -= mouseoffset_x + 1;
y -= mouseoffset_y + 2;
mousehack_enable ();
if (mousehack_address) {
uae_u8 tmp1[4], tmp2[4];
- p = get_real_address (mousehack_address);
+ uae_u8 *p = get_real_address (mousehack_address);
memcpy (tmp1, p + MH_ABSX, sizeof tmp1);
memcpy (tmp2, p + MH_BUTTONBITS, sizeof tmp2);
}
#endif
}
- p = uaeboard_bank.baseaddr + 0x200;
- if (p) {
+ if (uaeboard_bank.baseaddr) {
uae_u8 tmp[16];
+ uae_u8 *p = uaeboard_bank.baseaddr + 0x200;
memcpy(tmp, p + 2, 2 * 5);
p[0] = 0;
p[1] = 0;
#include "uae/ppc.h"
#include "cpuboard.h"
#include "threaddep/thread.h"
+#include "x86.h"
#ifdef JIT
#include "jit/compemu.h"
#include <signal.h>
}
}
+void execute_other_cpu_single(void)
+{
+#ifdef WITH_X86
+ if (!x86_turbo_on)
+ return;
+ x86_bridge_execute_until(0);
+#endif
+}
+
+bool execute_other_cpu(int until)
+{
+#ifdef WITH_X86
+ if (!x86_turbo_on)
+ return false;
+ if (!until)
+ until++;
+ x86_bridge_execute_until(until);
+#endif
+ return true;
+}
+
void cpu_sleep_millis(int ms)
{
#ifdef WITH_THREADED_CPU
if (state)
uae_ppc_spinlock_release();
#endif
- sleep_millis_main(ms);
+#ifdef WITH_X86
+ if (x86_turbo_on) {
+ execute_other_cpu(read_processor_time() + vsynctimebase / 20);
+ } else {
+ sleep_millis_main(ms);
+ }
+#endif
#ifdef WITH_PPC
if (state)
uae_ppc_spinlock_get();
#define IDC_DBG_MEMDOWN 1754
#define IDC_CS_1MCHIPJUMPER 1754
#define IDC_DBG_MEMUP 1755
+#define IDC_CS_BYTECUSTOMWRITEBUG 1755
#define IDC_DBG_MEM 1756
#define IDC_DBG_DASM 1757
#define IDC_DBG_MEMDOWNFAST 1758
CONTROL "Vertical Sync",IDC_CS_CIAA_TOD1,"Button",BS_AUTORADIOBUTTON | WS_GROUP | WS_TABSTOP,41,68,86,10
CONTROL "Power Supply 50Hz",IDC_CS_CIAA_TOD2,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,133,68,109,10
CONTROL "Power Supply 60Hz",IDC_CS_CIAA_TOD3,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,249,68,116,10
- GROUPBOX "Chipset Features",IDC_STATIC,0,88,395,123
+ GROUPBOX "Chipset Features",IDC_STATIC,0,88,395,128
CONTROL "CIA ROM Overlay",IDC_CS_CIAOVERLAY,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,14,102,104,11
CONTROL "CD32 CD",IDC_CS_CD32CD,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,14,116,104,11
CONTROL "CDTV CD",IDC_CS_CDTVCD,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,14,130,105,11
CONTROL "PCMCIA",IDC_CS_PCMCIA,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,264,156,125,11
CONTROL "C00000 is Fast RAM",IDC_CS_SLOWISFAST,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,264,170,125,11
CONTROL "A1000 Agnus (8361/8367)",IDC_CS_DIPAGNUS,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,264,184,125,11
- GROUPBOX "Internal SCSI Hardware",IDC_STATIC,0,212,395,45
- CONTROL "A3000 WD33C93 SCSI",IDC_CS_DMAC,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,34,227,121,11
- CONTROL "CDTV WD33C93 SCSI",IDC_CS_CDTVSCSI,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,34,240,121,11
- CONTROL "A4000T NCR53C710 SCSI",IDC_CS_DMAC2,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,171,227,125,11
+ GROUPBOX "Internal SCSI Hardware",IDC_STATIC,0,218,395,39
+ CONTROL "A3000 WD33C93 SCSI",IDC_CS_DMAC,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,14,236,108,11
+ CONTROL "CDTV WD33C93 SCSI",IDC_CS_CDTVSCSI,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,264,236,121,11
+ CONTROL "A4000T NCR53C710 SCSI",IDC_CS_DMAC2,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,127,236,125,11
GROUPBOX "Chipset Revision",IDC_STATIC,1,259,393,46
CONTROL "Ramsey revision:",IDC_CS_RAMSEY,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,34,275,97,11
CONTROL "Fat Gary revision:",IDC_CS_FATGARY,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,34,289,97,11
CONTROL "Denise/Lisa revision:",IDC_CS_DENISE,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,200,289,107,11
EDITTEXT IDC_CS_AGNUSREV,311,274,45,13,ES_AUTOHSCROLL
EDITTEXT IDC_CS_DENISEREV,311,289,45,13,ES_AUTOHSCROLL
+ CONTROL "Custom register byte write bug",IDC_CS_BYTECUSTOMWRITEBUG,
+ "Button",BS_AUTOCHECKBOX | WS_TABSTOP,127,197,130,11
END
IDD_AVIOUTPUT DIALOGEX 0, 0, 396, 260
<compatibility xmlns="urn:schemas-microsoft-com:compatibility.v1">
<application>
+ <supportedOS Id="{8e0f7a12-bfb3-4fe8-b9a5-48fd50a15a9a}"/>
<supportedOS Id="{1f676c76-80e1-4239-95bb-83d0f6d0da78}"/>
<supportedOS Id="{e2011457-1546-43c5-a5fe-008deee3d3f0}"/>
<supportedOS Id="{35138b9a-5d96-4fbd-8e2d-a2440225f93a}"/>
copy winuaesrc.zip d:\amiga\winuaepackets\winuaesrc%1.zip
move winuaesrc.zip d:\amiga
cd c:\projects\winuae\src\od-win32
-zip -9 winuaedebug%1 winuae_msvc11\fullrelease\winuae.pdb winuae_msvc11\x64\fullrelease\winuae.pdb
+zip -9 winuaedebug%1 winuae_msvc14\fullrelease\winuae.pdb winuae_msvc14\x64\fullrelease\winuae.pdb
move winuaedebug%1.zip d:\amiga\winuaepackets\debug\
-copy winuae_msvc11\fullrelease\winuae.pdb winuae_msvc11\x64\fullrelease\winuae.pdb d:\amiga\dump
+copy winuae_msvc14\fullrelease\winuae.pdb winuae_msvc14\x64\fullrelease\winuae.pdb d:\amiga\dump
copy d:\amiga\winuae.exe d:\amiga\dump
#define LANG_DLL_FULL_VERSION_MATCH 1
#if WINUAEPUBLICBETA
-#define WINUAEBETA _T("8")
+#define WINUAEBETA _T("9")
#else
#define WINUAEBETA _T("")
#endif
-#define WINUAEDATE MAKEBD(2015, 8, 16)
+#define WINUAEDATE MAKEBD(2015, 8, 20)
//#define WINUAEEXTRA _T("AmiKit Preview")
//#define WINUAEEXTRA _T("Amiga Forever Edition")
CheckRadioButton(hDlg, IDC_CS_RTC1, IDC_CS_RTC4, IDC_CS_RTC4);
break;
}
- CheckDlgButton (hDlg, IDC_CS_COMPATIBLE, workprefs.cs_compatible);
- CheckDlgButton (hDlg, IDC_CS_RESETWARNING, workprefs.cs_resetwarning);
- CheckDlgButton (hDlg, IDC_CS_NOEHB, workprefs.cs_denisenoehb);
- CheckDlgButton (hDlg, IDC_CS_DIPAGNUS, workprefs.cs_dipagnus);
- CheckDlgButton (hDlg, IDC_CS_KSMIRROR_E0, workprefs.cs_ksmirror_e0);
- CheckDlgButton (hDlg, IDC_CS_KSMIRROR_A8, workprefs.cs_ksmirror_a8);
- CheckDlgButton (hDlg, IDC_CS_CIAOVERLAY, workprefs.cs_ciaoverlay);
- CheckDlgButton (hDlg, IDC_CS_DF0IDHW, workprefs.cs_df0idhw);
- CheckDlgButton (hDlg, IDC_CS_CD32CD, workprefs.cs_cd32cd);
- CheckDlgButton (hDlg, IDC_CS_CD32C2P, workprefs.cs_cd32c2p);
- CheckDlgButton (hDlg, IDC_CS_CD32NVRAM, workprefs.cs_cd32nvram);
- CheckDlgButton (hDlg, IDC_CS_CDTVCD, workprefs.cs_cdtvcd);
- CheckDlgButton (hDlg, IDC_CS_CDTVCR, workprefs.cs_cdtvcr);
- CheckDlgButton (hDlg, IDC_CS_CDTVRAM, workprefs.cs_cdtvram);
- CheckDlgButton (hDlg, IDC_CS_CDTVRAMEXP, workprefs.cs_cdtvcard);
- CheckDlgButton (hDlg, IDC_CS_A1000RAM, workprefs.cs_a1000ram);
- CheckDlgButton (hDlg, IDC_CS_RAMSEY, workprefs.cs_ramseyrev >= 0);
- CheckDlgButton (hDlg, IDC_CS_FATGARY, workprefs.cs_fatgaryrev >= 0);
- CheckDlgButton (hDlg, IDC_CS_AGNUS, workprefs.cs_agnusrev >= 0);
- CheckDlgButton (hDlg, IDC_CS_DENISE, workprefs.cs_deniserev >= 0);
- CheckDlgButton (hDlg, IDC_CS_DMAC, workprefs.cs_mbdmac & 1);
- CheckDlgButton (hDlg, IDC_CS_DMAC2, workprefs.cs_mbdmac & 2);
- CheckDlgButton (hDlg, IDC_CS_CDTVSCSI, workprefs.cs_cdtvscsi);
- CheckDlgButton (hDlg, IDC_CS_PCMCIA, workprefs.cs_pcmcia);
- CheckDlgButton (hDlg, IDC_CS_SLOWISFAST, workprefs.cs_slowmemisfast);
- CheckDlgButton (hDlg, IDC_CS_CIATODBUG, workprefs.cs_ciatodbug);
- CheckDlgButton (hDlg, IDC_CS_Z3AUTOCONFIG, workprefs.cs_z3autoconfig);
- CheckDlgButton (hDlg, IDC_CS_IDE1, workprefs.cs_ide > 0 && (workprefs.cs_ide & 1));
- CheckDlgButton (hDlg, IDC_CS_IDE2, workprefs.cs_ide > 0 && (workprefs.cs_ide & 2));
- CheckDlgButton (hDlg, IDC_CS_1MCHIPJUMPER, workprefs.cs_1mchipjumper || workprefs.chipmem_size >= 0x100000);
+ CheckDlgButton(hDlg, IDC_CS_COMPATIBLE, workprefs.cs_compatible);
+ CheckDlgButton(hDlg, IDC_CS_RESETWARNING, workprefs.cs_resetwarning);
+ CheckDlgButton(hDlg, IDC_CS_NOEHB, workprefs.cs_denisenoehb);
+ CheckDlgButton(hDlg, IDC_CS_DIPAGNUS, workprefs.cs_dipagnus);
+ CheckDlgButton(hDlg, IDC_CS_KSMIRROR_E0, workprefs.cs_ksmirror_e0);
+ CheckDlgButton(hDlg, IDC_CS_KSMIRROR_A8, workprefs.cs_ksmirror_a8);
+ CheckDlgButton(hDlg, IDC_CS_CIAOVERLAY, workprefs.cs_ciaoverlay);
+ CheckDlgButton(hDlg, IDC_CS_DF0IDHW, workprefs.cs_df0idhw);
+ CheckDlgButton(hDlg, IDC_CS_CD32CD, workprefs.cs_cd32cd);
+ CheckDlgButton(hDlg, IDC_CS_CD32C2P, workprefs.cs_cd32c2p);
+ CheckDlgButton(hDlg, IDC_CS_CD32NVRAM, workprefs.cs_cd32nvram);
+ CheckDlgButton(hDlg, IDC_CS_CDTVCD, workprefs.cs_cdtvcd);
+ CheckDlgButton(hDlg, IDC_CS_CDTVCR, workprefs.cs_cdtvcr);
+ CheckDlgButton(hDlg, IDC_CS_CDTVRAM, workprefs.cs_cdtvram);
+ CheckDlgButton(hDlg, IDC_CS_CDTVRAMEXP, workprefs.cs_cdtvcard);
+ CheckDlgButton(hDlg, IDC_CS_A1000RAM, workprefs.cs_a1000ram);
+ CheckDlgButton(hDlg, IDC_CS_RAMSEY, workprefs.cs_ramseyrev >= 0);
+ CheckDlgButton(hDlg, IDC_CS_FATGARY, workprefs.cs_fatgaryrev >= 0);
+ CheckDlgButton(hDlg, IDC_CS_AGNUS, workprefs.cs_agnusrev >= 0);
+ CheckDlgButton(hDlg, IDC_CS_DENISE, workprefs.cs_deniserev >= 0);
+ CheckDlgButton(hDlg, IDC_CS_DMAC, workprefs.cs_mbdmac & 1);
+ CheckDlgButton(hDlg, IDC_CS_DMAC2, workprefs.cs_mbdmac & 2);
+ CheckDlgButton(hDlg, IDC_CS_CDTVSCSI, workprefs.cs_cdtvscsi);
+ CheckDlgButton(hDlg, IDC_CS_PCMCIA, workprefs.cs_pcmcia);
+ CheckDlgButton(hDlg, IDC_CS_SLOWISFAST, workprefs.cs_slowmemisfast);
+ CheckDlgButton(hDlg, IDC_CS_CIATODBUG, workprefs.cs_ciatodbug);
+ CheckDlgButton(hDlg, IDC_CS_Z3AUTOCONFIG, workprefs.cs_z3autoconfig);
+ CheckDlgButton(hDlg, IDC_CS_IDE1, workprefs.cs_ide > 0 && (workprefs.cs_ide & 1));
+ CheckDlgButton(hDlg, IDC_CS_IDE2, workprefs.cs_ide > 0 && (workprefs.cs_ide & 2));
+ CheckDlgButton(hDlg, IDC_CS_1MCHIPJUMPER, workprefs.cs_1mchipjumper || workprefs.chipmem_size >= 0x100000);
+ CheckDlgButton(hDlg, IDC_CS_BYTECUSTOMWRITEBUG, workprefs.cs_bytecustomwritebug);
txt[0] = 0;
_stprintf (txt, _T("%d"), workprefs.cs_rtc_adjust);
SetDlgItemText(hDlg, IDC_CS_RTCADJUST, txt);
: (ischecked (hDlg, IDC_CS_CIAA_TOD2) ? 1 : 2);
workprefs.cs_rtc = ischecked (hDlg, IDC_CS_RTC1) ? 0
: ischecked (hDlg, IDC_CS_RTC2) ? 1 : ischecked (hDlg, IDC_CS_RTC3) ? 2 : 3;
- workprefs.cs_1mchipjumper = ischecked (hDlg, IDC_CS_1MCHIPJUMPER);
+ workprefs.cs_1mchipjumper = ischecked(hDlg, IDC_CS_1MCHIPJUMPER);
+ workprefs.cs_bytecustomwritebug = ischecked(hDlg, IDC_CS_BYTECUSTOMWRITEBUG);
if (workprefs.cs_rtc) {
txt[0] = 0;
{
int e = workprefs.cs_compatible ? FALSE : TRUE;
- ew (hDlg, IDC_CS_FATGARY, e);
- ew (hDlg, IDC_CS_RAMSEY, e);
- ew (hDlg, IDC_CS_AGNUS, e);
- ew (hDlg, IDC_CS_DENISE, e);
- ew (hDlg, IDC_CS_FATGARYREV, e);
- ew (hDlg, IDC_CS_RAMSEYREV, e);
- ew (hDlg, IDC_CS_AGNUSREV, e);
- ew (hDlg, IDC_CS_DENISEREV, e);
- ew (hDlg, IDC_CS_IDE1, e);
- ew (hDlg, IDC_CS_IDE2, e);
- ew (hDlg, IDC_CS_DMAC, e);
- ew (hDlg, IDC_CS_DMAC2, e);
- ew (hDlg, IDC_CS_CDTVSCSI, e);
- ew (hDlg, IDC_CS_PCMCIA, e);
- ew (hDlg, IDC_CS_SLOWISFAST, e);
- ew (hDlg, IDC_CS_CD32CD, e);
- ew (hDlg, IDC_CS_CD32NVRAM, e);
- ew (hDlg, IDC_CS_CD32C2P, e);
- ew (hDlg, IDC_CS_CDTVCD, e);
- ew (hDlg, IDC_CS_CDTVCR, e);
- ew (hDlg, IDC_CS_CDTVRAM, e);
- ew (hDlg, IDC_CS_CDTVRAMEXP, e);
- ew (hDlg, IDC_CS_RESETWARNING, e);
- ew (hDlg, IDC_CS_CIATODBUG, e);
- ew (hDlg, IDC_CS_NOEHB, e);
- ew (hDlg, IDC_CS_DIPAGNUS, e);
- ew (hDlg, IDC_CS_Z3AUTOCONFIG, e);
- ew (hDlg, IDC_CS_KSMIRROR_E0, e);
- ew (hDlg, IDC_CS_KSMIRROR_A8, e);
- ew (hDlg, IDC_CS_CIAOVERLAY, e);
- ew (hDlg, IDC_CS_A1000RAM, e);
- ew (hDlg, IDC_CS_DF0IDHW, e);
- ew (hDlg, IDC_CS_CIAA_TOD1, e);
- ew (hDlg, IDC_CS_CIAA_TOD2, e);
- ew (hDlg, IDC_CS_CIAA_TOD3, e);
- ew (hDlg, IDC_CS_RTC1, e);
- ew (hDlg, IDC_CS_RTC2, e);
- ew (hDlg, IDC_CS_RTC3, e);
- ew (hDlg, IDC_CS_RTC4, e);
- ew (hDlg, IDC_CS_RTCADJUST, e);
- ew (hDlg, IDC_CS_1MCHIPJUMPER, e && workprefs.chipmem_size < 0x100000);
+ ew(hDlg, IDC_CS_FATGARY, e);
+ ew(hDlg, IDC_CS_RAMSEY, e);
+ ew(hDlg, IDC_CS_AGNUS, e);
+ ew(hDlg, IDC_CS_DENISE, e);
+ ew(hDlg, IDC_CS_FATGARYREV, e);
+ ew(hDlg, IDC_CS_RAMSEYREV, e);
+ ew(hDlg, IDC_CS_AGNUSREV, e);
+ ew(hDlg, IDC_CS_DENISEREV, e);
+ ew(hDlg, IDC_CS_IDE1, e);
+ ew(hDlg, IDC_CS_IDE2, e);
+ ew(hDlg, IDC_CS_DMAC, e);
+ ew(hDlg, IDC_CS_DMAC2, e);
+ ew(hDlg, IDC_CS_CDTVSCSI, e);
+ ew(hDlg, IDC_CS_PCMCIA, e);
+ ew(hDlg, IDC_CS_SLOWISFAST, e);
+ ew(hDlg, IDC_CS_CD32CD, e);
+ ew(hDlg, IDC_CS_CD32NVRAM, e);
+ ew(hDlg, IDC_CS_CD32C2P, e);
+ ew(hDlg, IDC_CS_CDTVCD, e);
+ ew(hDlg, IDC_CS_CDTVCR, e);
+ ew(hDlg, IDC_CS_CDTVRAM, e);
+ ew(hDlg, IDC_CS_CDTVRAMEXP, e);
+ ew(hDlg, IDC_CS_RESETWARNING, e);
+ ew(hDlg, IDC_CS_CIATODBUG, e);
+ ew(hDlg, IDC_CS_NOEHB, e);
+ ew(hDlg, IDC_CS_DIPAGNUS, e);
+ ew(hDlg, IDC_CS_Z3AUTOCONFIG, e);
+ ew(hDlg, IDC_CS_KSMIRROR_E0, e);
+ ew(hDlg, IDC_CS_KSMIRROR_A8, e);
+ ew(hDlg, IDC_CS_CIAOVERLAY, e);
+ ew(hDlg, IDC_CS_A1000RAM, e);
+ ew(hDlg, IDC_CS_DF0IDHW, e);
+ ew(hDlg, IDC_CS_CIAA_TOD1, e);
+ ew(hDlg, IDC_CS_CIAA_TOD2, e);
+ ew(hDlg, IDC_CS_CIAA_TOD3, e);
+ ew(hDlg, IDC_CS_RTC1, e);
+ ew(hDlg, IDC_CS_RTC2, e);
+ ew(hDlg, IDC_CS_RTC3, e);
+ ew(hDlg, IDC_CS_RTC4, e);
+ ew(hDlg, IDC_CS_RTCADJUST, e);
+ ew(hDlg, IDC_CS_1MCHIPJUMPER, e && workprefs.chipmem_size < 0x100000);
+ ew(hDlg, IDC_CS_BYTECUSTOMWRITEBUG, e);
}
static INT_PTR CALLBACK ChipsetDlgProc2 (HWND hDlg, UINT msg, WPARAM wParam, LPARAM lParam)
+Beta 9:
+
+- x86 floppy controller EOT parameter was read from wrong offset. Note that previously 1.4M floppy in
+ 720K drive (configured in 2286+ BIOS) worked, not anymore.
+- Added x86 bridgeboard 1.2M PC floppy image support.
+- Added Advanced chipset option that emulates some 68040/060 board's (for example Blizzard 1240/1260)
+ custom register byte write "bug" where byte write to custom register does not write same value to
+ both upper and lower byte. Previously this was always enabled if CPU type was 68060.
+ (Writing to even address: zero written to odd address, writing to odd address: works "correctly")
+- Fixed emulation boot crash if mouse driver was enabled (b8)
+- x86 IDE config didn't load correctly. (Reset and save needed to fix it). x86 VGA also needs config
+ reset.
+
Beta 8:
- Many saved accelerator board enabled configurations loaded incorrectly in b7.
void x86_doirq(uint8_t irqnum);
static frame_time_t last_cycles;
+static bool x86_turbo_allowed;
+static bool x86_turbo_enabled;
+bool x86_turbo_on;
+bool x86_cpu_active;
void CPU_Init(Section*);
void CPU_ShutDown(Section*);
static int floppy_delay_hsync;
static bool floppy_did_reset;
static bool floppy_irq;
-static uae_u8 floppy_rate;
+static uae_s8 floppy_rate;
#define PC_SEEK_DELAY 50
static void floppy_reset(void)
{
+ struct x86_bridge *xb = bridges[0];
+
write_log(_T("Floppy reset\n"));
floppy_idx = 0;
floppy_dir = 0;
floppy_did_reset = true;
+ if (0 && xb->type == TYPE_2286) {
+ // apparently A2286 BIOS AT driver assumes
+ // floppy reset also resets IDE.
+ // Perhaps this is forgotten feature from
+ // Commodore PC model that uses same BIOS variant?
+ x86_ide_hd_put(-1, 0, 0);
+ }
}
static void floppy_hardreset(void)
{
- floppy_rate = FLOPPY_RATE_300K;
+ floppy_rate = -1;
floppy_reset();
}
static bool floppy_valid_rate(struct floppy_reserved *fr)
{
- return fr->rate == floppy_rate;
+ return fr->rate == floppy_rate || floppy_rate < 0;
}
static void floppy_do_cmd(struct x86_bridge *xb)
write_log(_T("Floppy%d write MT=%d MF=%d C=%d:H=%d:R=%d:N=%d:EOT=%d:GPL=%d:DTL=%d\n"),
(floppy_cmd[0] & 0x80) ? 1 : 0, (floppy_cmd[0] & 0x40) ? 1 : 0,
floppy_cmd[2], floppy_cmd[3], floppy_cmd[4], floppy_cmd[5],
- floppy_cmd[6], floppy_cmd[7], floppy_cmd[8], floppy_cmd[9]);
+ floppy_cmd[6], floppy_cmd[7], floppy_cmd[8]);
write_log(_T("DMA addr %08x len %04x\n"), dmachan[2].page | dmachan[2].addr, dmachan[2].reload);
floppy_delay_hsync = 50;
- int eot = floppy_cmd[7];
+ int eot = floppy_cmd[6];
bool mt = (floppy_cmd[0] & 0x80) != 0;
int cyl = pcf->cyl;
if (valid_floppy) {
break;
if (pcf->sector == eot) {
pcf->sector = 0;
- if (pcf->head)
- pcf->cyl++;
- if (mt)
+ if (mt) {
+ if (pcf->head)
+ pcf->cyl++;
pcf->head ^= 1;
+ }
break;
}
if (pcf->sector >= fr.secs) {
write_log(_T("Floppy%d read MT=%d MF=%d SK=%d C=%d:H=%d:R=%d:N=%d:EOT=%d:GPL=%d:DTL=%d\n"),
floppy_num, (floppy_cmd[0] & 0x80) ? 1 : 0, (floppy_cmd[0] & 0x40) ? 1 : 0, (floppy_cmd[0] & 0x20) ? 1 : 0,
floppy_cmd[2], floppy_cmd[3], floppy_cmd[4], floppy_cmd[5],
- floppy_cmd[6], floppy_cmd[7], floppy_cmd[8], floppy_cmd[9]);
+ floppy_cmd[6], floppy_cmd[7], floppy_cmd[8]);
write_log(_T("DMA addr %08x len %04x\n"), dmachan[2].page | dmachan[2].addr, dmachan[2].reload);
floppy_delay_hsync = 50;
- int eot = floppy_cmd[7];
+ int eot = floppy_cmd[6];
bool mt = (floppy_cmd[0] & 0x80) != 0;
int cyl = pcf->cyl;
bool nodata = false;
if (valid_floppy) {
if (!floppy_valid_rate(&fr)) {
nodata = true;
+ } else if (pcf->head && fr.heads == 1) {
+ nodata = true;
} else if (fr.img && pcf->cyl != floppy_cmd[2]) {
floppy_status[0] |= 0x40; // abnormal termination
floppy_status[2] |= 0x20; // wrong cylinder
break;
if (pcf->sector == eot) {
pcf->sector = 0;
- if (pcf->head)
- pcf->cyl++;
- if (mt)
+ if (mt) {
+ if (pcf->head)
+ pcf->cyl++;
pcf->head ^= 1;
+ }
break;
}
if (pcf->sector >= fr.secs) {
case 10:
write_log(_T("Floppy read ID\n"));
- if (!valid_floppy || !fr.img || !floppy_valid_rate(&fr)) {
+ if (!valid_floppy || !fr.img || !floppy_valid_rate(&fr) || (pcf->head && fr.heads == 1)) {
floppy_status[0] |= 0x40; // abnormal termination
floppy_status[1] |= 0x04; // no data
}
static void outfloppy(struct x86_bridge *xb, int portnum, uae_u8 v)
{
+ if (!x86_turbo_allowed) {
+ x86_turbo_allowed = true;
+ }
+
switch (portnum)
{
case 0x3f2: // dpc
write_log(_T("FDC Control Register %02x\n"), v);
floppy_rate = v & 3;
} else {
- floppy_rate = FLOPPY_RATE_300K;
+ floppy_rate = -1;
}
break;
}
x86_ide_hd_put(portnum, v, 0);
break;
+ case 0x101:
+ case 0x102:
+ // A2286 BIOS timer test fails if CPU is too fast
+ // so we'll run normal speed until tests are done
+ if (!x86_turbo_allowed) {
+ x86_turbo_allowed = true;
+ }
+ break;
+
default:
write_log(_T("X86_OUT unknown %02x %02x\n"), portnum, v);
break;
}
}
+static void x86_cpu_execute(int cnt)
+{
+ struct x86_bridge *xb = bridges[0];
+ if (!xb->x86_reset) {
+ if (xb->dosbox_cpu) {
+ if (xb->x86_reset_requested) {
+ xb->x86_reset_requested = false;
+ reset_x86_cpu(xb);
+ }
+ CPU_Cycles = cnt;
+ (*cpudecoder)();
+ check_x86_irq();
+ } else {
+ exec86(cnt);
+ }
+ }
+}
+
+void x86_bridge_execute_until(int until)
+{
+ struct x86_bridge *xb = bridges[0];
+ if (!xb)
+ return;
+ if (!x86_turbo_allowed)
+ return;
+ for (;;) {
+ x86_cpu_execute(until ? 10 : 1);
+ if (until == 0)
+ break;
+ frame_time_t rpt = read_processor_time();
+ if ((int)until - (int)rpt <= 0)
+ break;
+ }
+}
+
void x86_bridge_hsync(void)
{
struct x86_bridge *xb = bridges[0];
do_floppy_irq();
}
- if (!xb->x86_reset) {
- if (xb->dosbox_cpu) {
- if (xb->x86_reset_requested) {
- xb->x86_reset_requested = false;
- reset_x86_cpu(xb);
- }
- int maxcnt = 3;
- for (int i = 0; i < maxcnt; i++) {
- CPU_Cycles = 40;
- (*cpudecoder)();
- check_x86_irq();
- timing(maxhpos / maxcnt);
- }
- } else {
- exec86(30);
- timing(maxhpos / 3);
- exec86(30);
- timing(maxhpos / 3);
- exec86(30);
- timing(maxhpos / 3);
- }
+ for (int i = 0; i < 3; i++) {
+ x86_cpu_execute(40);
+ timing(maxhpos / 3);
}
+
+ if (x86_turbo_allowed && x86_turbo_enabled && !x86_turbo_on) {
+ x86_turbo_on = true;
+ } else if ((!x86_turbo_allowed || !x86_turbo_enabled) && x86_turbo_on) {
+ x86_turbo_on = false;
+ }
+
}
static void ew(uae_u8 *acmemory, int addr, uae_u8 value)
xb->amiga_forced_interrupts = false;
xb->amiga_irq = false;
xb->pc_irq3a = xb->pc_irq3b = xb->pc_irq7 = false;
+ x86_turbo_allowed = false;
+ x86_cpu_active = false;
memset(xb->amiga_io, 0, 0x10000);
memset(xb->io_ports, 0, 0x10000);
for (int i = 0; i < 2; i++) {