fix LSIGN opcode and modify ISIGN opcode for symmetry

diff --git a/ChangeLog b/ChangeLog
index ecce64a0819eaf4258da6795c977f97e86d844b1..7928b3426fa45c8067af02554fbd7de76249a61d 100644 (file)
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,8 @@
+2008-04-20  Aleksey Demakov  <ademakov@gmail.com>
+
+       * jit/jit-rules-x86.ins: fix the sign opcode for longs (based on
+       a patch from Klaus) and slightly modify it for ints.
+
 2008-04-19  Klaus Treichel  <ktreichel@web.de>
 
        * jit/jit-insn.c (jit_insn_sign): the dest value of the sign insn

diff --git a/jit/jit-rules-x86.ins b/jit/jit-rules-x86.ins
index f9017cb7524d72b556a89279b77a4a9d063a0cd4..4861ffcca7cad6a31a82d03ac3f7a8c19f1d9bc8 100644 (file)
--- a/jit/jit-rules-x86.ins
+++ b/jit/jit-rules-x86.ins
@@ -1481,17 +1481,17 @@ JIT_OP_ISIGN:
                        x86_clear_reg(inst, $1);
                }
        }
-       [reg, scratch reg] -> {
-               x86_clear_reg(inst, $2);
-               x86_test_reg_reg(inst, $1, $1);
-               x86_set_reg(inst,X86_CC_GT, $2, 1);
-               x86_shift_reg_imm(inst, X86_SAR, $1, 31);
-               x86_alu_reg_reg(inst, X86_ADD, $1, $2);
+       [=+reg, +reg] -> {
+               x86_clear_reg(inst, $1);
+               x86_test_reg_reg(inst, $2, $2);
+               x86_set_reg(inst, X86_CC_NZ, $1, 0);
+               x86_shift_reg_imm(inst, X86_SAR, $2, 31);
+               x86_alu_reg_reg(inst, X86_OR, $1, $2);
        }
 
 JIT_OP_LSIGN:
        [=reg, imm] -> {
-               jit_int value = ((jit_int *)($2))[1];
+               jit_long value = *((jit_long *)($2));
                if(value < 0)
                {
                        x86_mov_reg_imm(inst, $1, -1);
@@ -1505,12 +1505,12 @@ JIT_OP_LSIGN:
                        x86_clear_reg(inst, $1);
                }
        }
-       [=reg, lreg] -> {
-               if($1 != %2)
-               {
-                       x86_mov_reg_reg(inst, $1, %2, 4);
-               }
-               x86_shift_reg_imm(inst, X86_SAR, $1, 31);
+       [=+reg, +lreg] -> {
+               x86_clear_reg(inst, $1);
+               x86_alu_reg_reg(inst, X86_OR, $2, %2);
+               x86_set_reg(inst, X86_CC_NZ, $1, 0);
+               x86_shift_reg_imm(inst, X86_SAR, %2, 31);
+               x86_alu_reg_reg(inst, X86_OR, $1, %2);
        }
 
 /*