--- /dev/null
+ /*
+ * UAE - The Un*x Amiga Emulator
+ *
+ * A590/A2091/A3000 (DMAC/SuperDMAC + WD33C93) emulation
+ *
+ * Copyright 2007 Toni Wilen
+ *
+ */
+
+#define A2091_DEBUG 0
+#define A3000_DEBUG 0
+#define WD33C93_DEBUG 1
+
+#include "sysconfig.h"
+#include "sysdeps.h"
+
+#include "options.h"
+#include "uae.h"
+#include "memory.h"
+#include "custom.h"
+#include "newcpu.h"
+#include "debug.h"
+#include "a2091.h"
+#include "blkdev.h"
+#include "gui.h"
+#include "zfile.h"
+#include "threaddep/thread.h"
+
+#define ROM_VECTOR 0x2000
+#define ROM_OFFSET 0x2000
+#define ROM_SIZE 16384
+#define ROM_MASK (ROM_SIZE - 1)
+
+/* SuperDMAC CNTR bits. */
+#define SCNTR_TCEN (1<<5)
+#define SCNTR_PREST (1<<4)
+#define SCNTR_PDMD (1<<3)
+#define SCNTR_INTEN (1<<2)
+#define SCNTR_DDIR (1<<1)
+#define SCNTR_IO_DX (1<<0)
+/* DMAC CNTR bits. */
+#define CNTR_TCEN (1<<7)
+#define CNTR_PREST (1<<6)
+#define CNTR_PDMD (1<<5)
+#define CNTR_INTEN (1<<4)
+#define CNTR_DDIR (1<<3)
+/* ISTR bits. */
+#define ISTR_INTX (1<<8)
+#define ISTR_INT_F (1<<7)
+#define ISTR_INTS (1<<6)
+#define ISTR_E_INT (1<<5)
+#define ISTR_INT_P (1<<4)
+#define ISTR_UE_INT (1<<3)
+#define ISTR_OE_INT (1<<2)
+#define ISTR_FF_FLG (1<<1)
+#define ISTR_FE_FLG (1<<0)
+
+/* wd register names */
+#define WD_OWN_ID 0x00
+#define WD_CONTROL 0x01
+#define WD_TIMEOUT_PERIOD 0x02
+#define WD_CDB_1 0x03
+#define WD_CDB_2 0x04
+#define WD_CDB_3 0x05
+#define WD_CDB_4 0x06
+#define WD_CDB_5 0x07
+#define WD_CDB_6 0x08
+#define WD_CDB_7 0x09
+#define WD_CDB_8 0x0a
+#define WD_CDB_9 0x0b
+#define WD_CDB_10 0x0c
+#define WD_CDB_11 0x0d
+#define WD_CDB_12 0x0e
+#define WD_TARGET_LUN 0x0f
+#define WD_COMMAND_PHASE 0x10
+#define WD_SYNCHRONOUS_TRANSFER 0x11
+#define WD_TRANSFER_COUNT_MSB 0x12
+#define WD_TRANSFER_COUNT 0x13
+#define WD_TRANSFER_COUNT_LSB 0x14
+#define WD_DESTINATION_ID 0x15
+#define WD_SOURCE_ID 0x16
+#define WD_SCSI_STATUS 0x17
+#define WD_COMMAND 0x18
+#define WD_DATA 0x19
+#define WD_QUEUE_TAG 0x1a
+#define WD_AUXILIARY_STATUS 0x1f
+/* WD commands */
+#define WD_CMD_RESET 0x00
+#define WD_CMD_ABORT 0x01
+#define WD_CMD_ASSERT_ATN 0x02
+#define WD_CMD_NEGATE_ACK 0x03
+#define WD_CMD_DISCONNECT 0x04
+#define WD_CMD_RESELECT 0x05
+#define WD_CMD_SEL_ATN 0x06
+#define WD_CMD_SEL 0x07
+#define WD_CMD_SEL_ATN_XFER 0x08
+#define WD_CMD_SEL_XFER 0x09
+#define WD_CMD_RESEL_RECEIVE 0x0a
+#define WD_CMD_RESEL_SEND 0x0b
+#define WD_CMD_WAIT_SEL_RECEIVE 0x0c
+#define WD_CMD_TRANS_ADDR 0x18
+#define WD_CMD_TRANS_INFO 0x20
+#define WD_CMD_TRANSFER_PAD 0x21
+#define WD_CMD_SBT_MODE 0x80
+
+#define CSR_MSGIN 0x20
+#define CSR_SDP 0x21
+#define CSR_SEL_ABORT 0x22
+#define CSR_RESEL_ABORT 0x25
+#define CSR_RESEL_ABORT_AM 0x27
+#define CSR_ABORT 0x28
+
+static int configured;
+static uae_u8 dmacmemory[100];
+static uae_u8 *rom;
+
+static uae_u32 dmac_istr, dmac_cntr;
+static uae_u32 dmac_dawr;
+static uae_u32 dmac_acr;
+static uae_u32 dmac_wtc;
+static int dmac_dma;
+static uae_u8 sasr, scmd, auxstatus;
+static int wd_used;
+
+static int superdmac;
+
+static uae_u8 wdregs[32];
+
+#define WD33C93 "WD33C93"
+
+void rethink_a2091(void)
+{
+ if (dmac_istr & ISTR_INTS)
+ INTREQ_0 (0x8000 | 0x0008);
+}
+
+static void INT2(void)
+{
+ int irq = 0;
+
+ if (!(auxstatus & 0x80))
+ return;
+ dmac_istr |= ISTR_INTS;
+ if (superdmac) {
+ if ((dmac_cntr & SCNTR_INTEN) && (dmac_istr & ISTR_INTS))
+ irq = 1;
+ } else {
+ if ((dmac_cntr & CNTR_INTEN) && (dmac_istr & ISTR_INTS))
+ irq = 1;
+ }
+ if (irq) {
+ if (!(intreq & 8))
+ INTREQ_f(0x8000 | 0x0008);
+ }
+}
+
+static void dmac_reset(void)
+{
+#if WD33C93_DEBUG > 0
+ if (superdmac)
+ write_log("A3000 %s SCSI reset\n", WD33C93);
+ else
+ write_log("A2091 %s SCSI reset\n", WD33C93);
+#endif
+}
+
+static void incsasr(void)
+{
+ if (sasr == WD_AUXILIARY_STATUS || sasr == WD_DATA || sasr == WD_COMMAND)
+ return;
+ sasr++;
+ sasr &= 0x1f;
+}
+
+static void dmac_cint(void)
+{
+ dmac_istr = 0;
+}
+
+static void set_status(uae_u8 status)
+{
+ wdregs[WD_SCSI_STATUS] = status;
+ auxstatus |= 0x80;
+ INT2();
+}
+
+static void wd_cmd_sel(void)
+{
+#if WD33C93_DEBUG > 0
+ write_log("%s select, ID=%d\n", WD33C93, wdregs[WD_DESTINATION_ID]);
+#endif
+ set_status(0x42);
+}
+
+static void wd_cmd_abort(void)
+{
+#if WD33C93_DEBUG > 0
+ write_log("%s abort\n", WD33C93);
+#endif
+ set_status(0x22);
+}
+
+static void putwd(uae_u8 d)
+{
+#if WD33C93_DEBUG > 1
+ write_log("%s REG %02.2X (%d) = %02.2X (%d)\n", WD33C93, sasr, sasr, d, d);
+#endif
+ wdregs[sasr] = d;
+ if (!wd_used) {
+ wd_used = 1;
+ write_log("%s in use\n", WD33C93);
+ }
+ if (sasr == WD_COMMAND) {
+ switch (d)
+ {
+ case WD_CMD_SEL_ATN:
+ case WD_CMD_SEL:
+ wd_cmd_sel();
+ break;
+ }
+ }
+ incsasr();
+}
+static uae_u8 getwd(void)
+{
+ uae_u8 v;
+
+ v = wdregs[sasr];
+ if (sasr == WD_SCSI_STATUS) {
+ auxstatus &= ~0x80;
+ dmac_istr &= ~ISTR_INTS;
+ }
+ incsasr();
+ return v;
+}
+
+static uae_u32 dmac_bget2 (uaecptr addr)
+{
+ uae_u32 v = 0;
+
+ if (addr < 0x40)
+ return dmacmemory[addr];
+ if (addr >= ROM_OFFSET)
+ return rom[addr & ROM_MASK];
+
+ switch (addr)
+ {
+ case 0x41:
+ v = dmac_istr;
+ if (v)
+ v |= ISTR_INT_P;
+ break;
+ case 0x43:
+ v = dmac_cntr;
+ break;
+ case 0x91:
+ v = auxstatus;
+ break;
+ case 0x93:
+ v = getwd();
+ break;
+ /* XT IO */
+ case 0xa1:
+ case 0xa3:
+ case 0xa5:
+ case 0xa7:
+ v = 0xff;
+ break;
+ }
+#if A2091_DEBUG > 0
+ write_log ("dmac_bget %04.4X=%02.2X PC=%08.8X\n", addr, v, M68K_GETPC);
+#endif
+ return v;
+}
+
+static void dmac_bput2 (uaecptr addr, uae_u32 b)
+{
+ if (addr < 0x40)
+ return;
+ if (addr >= ROM_OFFSET)
+ return;
+
+ switch (addr)
+ {
+ case 0x43:
+ dmac_cntr = b;
+ if (dmac_cntr & CNTR_PREST)
+ dmac_reset ();
+ break;
+ case 0x80:
+ dmac_wtc &= 0x00ffffff;
+ dmac_wtc |= b << 24;
+ break;
+ case 0x81:
+ dmac_wtc &= 0xff00ffff;
+ dmac_wtc |= b << 16;
+ break;
+ case 0x82:
+ dmac_wtc &= 0xffff00ff;
+ dmac_wtc |= b << 8;
+ break;
+ case 0x83:
+ dmac_wtc &= 0xffffff00;
+ dmac_wtc |= b << 0;
+ break;
+ case 0x84:
+ dmac_acr &= 0x00ffffff;
+ dmac_acr |= b << 24;
+ break;
+ case 0x85:
+ dmac_acr &= 0xff00ffff;
+ dmac_acr |= b << 16;
+ break;
+ case 0x86:
+ dmac_acr &= 0xffff00ff;
+ dmac_acr |= b << 8;
+ break;
+ case 0x87:
+ dmac_acr &= 0xffffff01;
+ dmac_acr |= (b & ~ 1) << 0;
+ break;
+ case 0x8e:
+ dmac_dawr &= 0x00ff;
+ dmac_dawr |= b << 8;
+ break;
+ case 0x8f:
+ dmac_dawr &= 0xff00;
+ dmac_dawr |= b << 0;
+ break;
+ case 0x91:
+ sasr = b;
+ break;
+ case 0x93:
+ putwd(b);
+ break;
+ case 0xe0:
+ case 0xe1:
+ if (!dmac_dma) {
+ dmac_dma = 1;
+ write_log("a2091 dma started\n");
+ }
+ break;
+ case 0xe2:
+ case 0xe3:
+ dmac_dma = 0;
+ break;
+ case 0xe4:
+ case 0xe5:
+ dmac_cint();
+ break;
+ case 0xe8:
+ case 0xe9:
+ dmac_dma = 0;
+ break;
+ }
+#if A2091_DEBUG > 0
+ write_log ("dmac_bput %04.4X=%02.2X PC=%08.8X\n", addr, b & 255, M68K_GETPC);
+#endif
+}
+
+
+
+static uae_u32 REGPARAM2 dmac_lget (uaecptr addr)
+{
+ uae_u32 v;
+#ifdef JIT
+ special_mem |= S_READ;
+#endif
+ addr &= 65535;
+ v = (dmac_bget2 (addr) << 24) | (dmac_bget2 (addr + 1) << 16) |
+ (dmac_bget2 (addr + 2) << 8) | (dmac_bget2 (addr + 3));
+#ifdef A2091_DEBUG
+ if (addr >= 0x40 && addr < ROM_OFFSET)
+ write_log ("dmac_lget %08.8X=%08.8X PC=%08.8X\n", addr, v, M68K_GETPC);
+#endif
+ return v;
+}
+
+static uae_u32 REGPARAM2 dmac_wget (uaecptr addr)
+{
+ uae_u32 v;
+#ifdef JIT
+ special_mem |= S_READ;
+#endif
+ addr &= 65535;
+ v = (dmac_bget2 (addr) << 8) | dmac_bget2 (addr + 1);
+#if A2091_DEBUG > 0
+ if (addr >= 0x40 && addr < ROM_OFFSET)
+ write_log ("dmac_wget %08.8X=%04.4X PC=%08.8X\n", addr, v, M68K_GETPC);
+#endif
+ return v;
+}
+
+static uae_u32 REGPARAM2 dmac_bget (uaecptr addr)
+{
+ uae_u32 v;
+#ifdef JIT
+ special_mem |= S_READ;
+#endif
+ addr &= 65535;
+ v = dmac_bget2 (addr);
+ if (!configured)
+ return v;
+ return v;
+}
+
+static void REGPARAM2 dmac_lput (uaecptr addr, uae_u32 l)
+{
+#ifdef JIT
+ special_mem |= S_WRITE;
+#endif
+ addr &= 65535;
+#if A2091_DEBUG > 0
+ if (addr >= 0x40 && addr < ROM_OFFSET)
+ write_log ("dmac_lput %08.8X=%08.8X PC=%08.8X\n", addr, l, M68K_GETPC);
+#endif
+ dmac_bput2 (addr, l >> 24);
+ dmac_bput2 (addr + 1, l >> 16);
+ dmac_bput2 (addr + 2, l >> 8);
+ dmac_bput2 (addr + 3, l);
+}
+
+static void REGPARAM2 dmac_wput (uaecptr addr, uae_u32 w)
+{
+#ifdef JIT
+ special_mem |= S_WRITE;
+#endif
+ addr &= 65535;
+#if A2091_DEBUG > 0
+ if (addr >= 0x40 && addr < ROM_OFFSET)
+ write_log ("dmac_wput %04.4X=%04.4X PC=%08.8X\n", addr, w & 65535, M68K_GETPC);
+#endif
+ dmac_bput2 (addr, w >> 8);
+ dmac_bput2 (addr + 1, w);
+}
+
+static void REGPARAM2 dmac_bput (uaecptr addr, uae_u32 b)
+{
+#ifdef JIT
+ special_mem |= S_WRITE;
+#endif
+ b &= 0xff;
+ addr &= 65535;
+ if (addr == 0x48) {
+ map_banks (&dmaca2091_bank, b, 0x10000 >> 16, 0x10000);
+ write_log ("A590/A2091 autoconfigured at %02.2X0000\n", b);
+ configured = 1;
+ expamem_next();
+ return;
+ }
+ if (addr == 0x4c) {
+ write_log ("A590/A2091 DMAC AUTOCONFIG SHUT-UP!\n");
+ configured = 1;
+ expamem_next();
+ return;
+ }
+ if (!configured)
+ return;
+ dmac_bput2 (addr, b);
+}
+
+static uae_u32 REGPARAM2 dmac_wgeti (uaecptr addr)
+{
+ uae_u32 v = 0xffff;
+#ifdef JIT
+ special_mem |= S_READ;
+#endif
+ addr &= 65535;
+ if (addr >= ROM_OFFSET)
+ v = (rom[addr & ROM_MASK] << 8) | rom[(addr + 1) & ROM_MASK];
+ return v;
+}
+static uae_u32 REGPARAM2 dmac_lgeti (uaecptr addr)
+{
+ uae_u32 v = 0xffff;
+#ifdef JIT
+ special_mem |= S_READ;
+#endif
+ addr &= 65535;
+ v = (dmac_wgeti(addr) << 16) | dmac_wgeti(addr + 2);
+ return v;
+}
+
+addrbank dmaca2091_bank = {
+ dmac_lget, dmac_wget, dmac_bget,
+ dmac_lput, dmac_wput, dmac_bput,
+ default_xlate, default_check, NULL, "A2091/A590",
+ dmac_lgeti, dmac_wgeti, ABFLAG_IO
+};
+
+
+static void dmac_start_dma(void)
+{
+}
+static void dmac_stop_dma(void)
+{
+}
+
+static void dmacreg_write(uae_u32 *reg, int addr, uae_u32 val, int size)
+{
+ addr = (size - 1) - addr;
+ (*reg) &= ~(0xff << (addr * 8));
+ (*reg) |= (val & 0xff) << (addr * 8);
+}
+static uae_u32 dmacreg_read(uae_u32 val, int addr, int size)
+{
+ addr = (size - 1) - addr;
+ return (val >> (addr * 8)) & 0xff;
+}
+
+static void mbdmac_write (uae_u32 addr, uae_u32 val)
+{
+ if (currprefs.cs_mbdmac > 1)
+ return;
+#if A3000_DEBUG > 0
+ write_log ("DMAC_WRITE %08.8X=%02.2X PC=%08.8X\n", addr, val & 0xff, M68K_GETPC);
+#endif
+ addr &= 0xffff;
+ switch (addr)
+ {
+ case 0x02:
+ case 0x03:
+ dmacreg_write(&dmac_dawr, addr - 0x02, val, 2);
+ break;
+ case 0x04:
+ case 0x05:
+ case 0x06:
+ case 0x07:
+ dmacreg_write(&dmac_wtc, addr - 0x04, val, 4);
+ break;
+ case 0x0a:
+ case 0x0b:
+ dmacreg_write(&dmac_cntr, addr - 0x0a, val, 2);
+ if (dmac_cntr & SCNTR_PREST)
+ dmac_reset();
+ break;
+ case 0x0c:
+ case 0x0d:
+ case 0x0e:
+ case 0x0f:
+ dmacreg_write(&dmac_acr, addr - 0x0c, val, 4);
+ break;
+ case 0x12:
+ case 0x13:
+ if (!dmac_dma) {
+ dmac_dma = 1;
+ dmac_start_dma();
+ }
+ break;
+ case 0x16:
+ case 0x17:
+ /* FLUSH */
+ break;
+ case 0x1a:
+ case 0x1b:
+ dmac_cint();
+ break;
+ case 0x1e:
+ case 0x1f:
+ /* ISTR */
+ break;
+ case 0x3e:
+ case 0x3f:
+ dmac_dma = 0;
+ dmac_stop_dma();
+ break;
+ case 0x49:
+ sasr = val;
+ break;
+ case 0x43:
+ putwd(val);
+ break;
+ }
+}
+
+static uae_u32 mbdmac_read (uae_u32 addr)
+{
+ uae_u32 vaddr = addr;
+ uae_u32 v = 0xffffffff;
+
+ if (currprefs.cs_mbdmac > 1)
+ return 0;
+
+ addr &= 0xffff;
+ switch (addr)
+ {
+ case 0x02:
+ case 0x03:
+ v = dmacreg_read(dmac_dawr, addr - 0x02, 2);
+ break;
+ case 0x04:
+ case 0x05:
+ case 0x06:
+ case 0x07:
+ v = dmacreg_read(dmac_wtc, addr - 0x04, 4);
+ break;
+ case 0x0a:
+ case 0x0b:
+ v = dmacreg_read(dmac_cntr, addr - 0x0a, 2);
+ break;
+ case 0x0c:
+ case 0x0d:
+ case 0x0e:
+ case 0x0f:
+ v = dmacreg_read(dmac_acr, addr - 0x0c, 4);
+ break;
+ case 0x12:
+ case 0x13:
+ if (dmac_dma) {
+ dmac_dma = 1;
+ dmac_start_dma();
+ }
+ v = 0;
+ break;
+ case 0x1a:
+ case 0x1b:
+ dmac_cint();
+ v = 0;
+ break;;
+ case 0x1e:
+ case 0x1f:
+ v = dmacreg_read(dmac_istr, addr - 0x1e, 2);
+ if (v)
+ v |= ISTR_INT_P;
+ break;
+ case 0x3e:
+ case 0x3f:
+ dmac_dma = 0;
+ dmac_stop_dma();
+ v = 0;
+ break;
+ case 0x49:
+ v = sasr;
+ break;
+ case 0x43:
+ v = getwd();
+ break;
+ }
+#if A3000_DEBUG > 0
+ write_log ("DMAC_READ %08.8X=%02.2X PC=%X\n", vaddr, v & 0xff, M68K_GETPC);
+#endif
+ return v;
+}
+
+
+static uae_u32 REGPARAM3 mbdmac_lget (uaecptr) REGPARAM;
+static uae_u32 REGPARAM3 mbdmac_wget (uaecptr) REGPARAM;
+static uae_u32 REGPARAM3 mbdmac_bget (uaecptr) REGPARAM;
+static void REGPARAM3 mbdmac_lput (uaecptr, uae_u32) REGPARAM;
+static void REGPARAM3 mbdmac_wput (uaecptr, uae_u32) REGPARAM;
+static void REGPARAM3 mbdmac_bput (uaecptr, uae_u32) REGPARAM;
+
+static uae_u32 REGPARAM2 mbdmac_lget (uaecptr addr)
+{
+#ifdef JIT
+ special_mem |= S_READ;
+#endif
+ return (mbdmac_wget (addr) << 16) | mbdmac_wget (addr + 2);
+}
+static uae_u32 REGPARAM2 mbdmac_wget (uaecptr addr)
+{
+#ifdef JIT
+ special_mem |= S_READ;
+#endif
+ return (mbdmac_bget (addr) << 8) | mbdmac_bget(addr + 1);;
+}
+static uae_u32 REGPARAM2 mbdmac_bget (uaecptr addr)
+{
+#ifdef JIT
+ special_mem |= S_READ;
+#endif
+ return mbdmac_read (addr);
+}
+static void REGPARAM2 mbdmac_lput (uaecptr addr, uae_u32 value)
+{
+#ifdef JIT
+ special_mem |= S_WRITE;
+#endif
+ mbdmac_wput (addr, value >> 16);
+ mbdmac_wput (addr + 2, value & 0xffff);
+}
+static void REGPARAM2 mbdmac_wput (uaecptr addr, uae_u32 value)
+{
+#ifdef JIT
+ special_mem |= S_WRITE;
+#endif
+ mbdmac_bput (addr, value);
+ mbdmac_bput (addr, value + 1);
+}
+static void REGPARAM2 mbdmac_bput (uaecptr addr, uae_u32 value)
+{
+#ifdef JIT
+ special_mem |= S_WRITE;
+#endif
+ mbdmac_write (addr, value);
+}
+
+addrbank mbdmac_a3000_bank = {
+ mbdmac_lget, mbdmac_wget, mbdmac_bget,
+ mbdmac_lput, mbdmac_wput, mbdmac_bput,
+ default_xlate, default_check, NULL, "A3000 DMAC",
+ dummy_lgeti, dummy_wgeti, ABFLAG_IO
+};
+
+static void ew (int addr, uae_u32 value)
+{
+ addr &= 0xffff;
+ if (addr == 00 || addr == 02 || addr == 0x40 || addr == 0x42) {
+ dmacmemory[addr] = (value & 0xf0);
+ dmacmemory[addr + 2] = (value & 0x0f) << 4;
+ } else {
+ dmacmemory[addr] = ~(value & 0xf0);
+ dmacmemory[addr + 2] = ~((value & 0x0f) << 4);
+ }
+}
+void a2091_free (void)
+{
+}
+
+void a2091_reset (void)
+{
+ configured = 0;
+ wd_used = 0;
+ superdmac = 0;
+ superdmac = currprefs.cs_mbdmac ? 1 : 0;
+}
+
+void a2091_init (void)
+{
+ struct zfile *z;
+ char path[MAX_DPATH];
+
+ configured = 0;
+ memset (dmacmemory, 0xff, 100);
+ ew (0x00, 0xc0 | 0x01 | 0x10);
+ /* A590/A2091 hardware id */
+ ew (0x04, 0x03);
+ ew (0x08, 0x40);
+ /* commodore's manufacturer id */
+ ew (0x10, 0x02);
+ ew (0x14, 0x02);
+ /* rom vector */
+ ew (0x28, ROM_VECTOR >> 8);
+ ew (0x2c, ROM_VECTOR);
+ /* KS autoconfig handles the rest */
+ map_banks (&dmaca2091_bank, 0xe80000 >> 16, 0x10000 >> 16, 0x10000);
+ if (!rom) {
+ fetch_datapath (path, sizeof path);
+ strcat (path, "roms\\a2091_rev7.rom");
+ write_log("A590/A2091 ROM path: '%s'\n", path);
+ z = zfile_fopen(path, "rb");
+ if (z) {
+ rom = xmalloc (ROM_SIZE);
+ zfile_fread (rom, ROM_SIZE, 1, z);
+ zfile_fclose(z);
+ }
+ }
+}
*/
//#define CDTV_DEBUG
-#define CDTV_DEBUG_CMD
+//#define CDTV_DEBUG_CMD
//#define CDTV_DEBUG_6525
#include "sysconfig.h"
static void INT2(void)
{
- INTREQ_f(0x8000 | 0x0008);
+ if (!(intreq & 8))
+ INTREQ_f(0x8000 | 0x0008);
}
static int cdrom_command_cnt_out, cdrom_command_size_out;
{
static int subqcnt;
- if (!currprefs.cs_cdtvcd)
+ if (!currprefs.cs_cdtvcd || !configured)
return;
cdtv_hsync++;
if (dma_wait >= 0 && dma_wait < 1024 && dma_finished) {
if ((dmac_cntr & (CNTR_INTEN | CNTR_TCEN)) == (CNTR_INTEN | CNTR_TCEN)) {
dmac_istr |= ISTR_INT_P | ISTR_E_INT;
- INT2();
}
dma_finished = 0;
cdtv_hsync = -1;
}
+ if (dmac_istr & ISTR_E_INT)
+ INT2();
if (cdrom_command_done) {
cdrom_command_done = 0;
return v;
}
-uae_u32 REGPARAM2 dmac_lget (uaecptr addr)
+static uae_u32 REGPARAM2 dmac_lget (uaecptr addr)
{
uae_u32 v;
#ifdef JIT
return v;
}
-uae_u32 REGPARAM2 dmac_wget (uaecptr addr)
+static uae_u32 REGPARAM2 dmac_wget (uaecptr addr)
{
uae_u32 v;
#ifdef JIT
return v;
}
-uae_u32 REGPARAM2 dmac_bget (uaecptr addr)
+static uae_u32 REGPARAM2 dmac_bget (uaecptr addr)
{
uae_u32 v;
#ifdef JIT
special_mem |= S_WRITE;
#endif
addr &= 65535;
+ b &= 0xff;
if (addr == 0x48) {
- map_banks (&dummy_bank, 0xe80000 >> 16, 0x10000 >> 16, 0x10000);
map_banks (&dmac_bank, b, 0x10000 >> 16, 0x10000);
write_log ("CDTV DMAC autoconfigured at %02.2X0000\n", b & 0xff);
configured = 1;
+ expamem_next();
return;
}
if (addr == 0x4c) {
- map_banks (&dummy_bank, 0xe80000 >> 16, 0x10000 >> 16, 0x10000);
write_log ("CDTV DMAC AUTOCONFIG SHUT-UP!\n");
configured = 1;
+ expamem_next();
return;
}
if (!configured)
cfgfile_write (f, "a1000ram=%s\n", p->cs_a1000ram ? "true" : "false");
cfgfile_write (f, "fatgary=%d\n", p->cs_fatgaryrev);
cfgfile_write (f, "ramsey=%d\n", p->cs_ramseyrev);
+ cfgfile_write (f, "scsi_a2091=%s\n", p->cs_a2091 ? "true" : "false");
+ cfgfile_write (f, "scsi_a3000=%s\n", p->cs_mbdmac ? "true" : "false");
cfgfile_write (f, "fastmem_size=%d\n", p->fastmem_size / 0x100000);
cfgfile_write (f, "a3000mem_size=%d\n", p->mbresmem_low_size / 0x100000);
|| cfgfile_yesno (option, value, "cdtvcd", &p->cs_cdtvcd)
|| cfgfile_yesno (option, value, "cdtvram", &p->cs_cdtvram)
|| cfgfile_yesno (option, value, "a1000ram", &p->cs_a1000ram)
+ || cfgfile_yesno (option, value, "scsi_a2091", &p->cs_a2091)
+ || cfgfile_yesno (option, value, "scsi_a3000", &p->cs_mbdmac)
|| cfgfile_yesno (option, value, "kickshifter", &p->kickshifter)
|| cfgfile_yesno (option, value, "ntsc", &p->ntscmode)
p->cs_ramseyrev = -1;
p->cs_agnusrev = -1;
p->cs_deniserev = -1;
- p->cs_mbdmac = -1;
+ p->cs_mbdmac = 0;
+ p->cs_a2091 = 0;
p->cs_cd32c2p = p->cs_cd32cd = p->cs_cd32nvram = 0;
p->cs_cdtvcd = p->cs_cdtvram = p->cs_cdtvcard = 0;
p->cs_pcmcia = 0;
p->cs_ramseyrev = -1;
p->cs_agnusrev = -1;
p->cs_deniserev = -1;
- p->cs_mbdmac = -1;
+ p->cs_mbdmac = 0;
+ p->cs_a2091 = 0;
p->cs_cd32c2p = p->cs_cd32cd = p->cs_cd32nvram = 0;
p->cs_cdtvcd = p->cs_cdtvram = p->cs_cdtvcard = 0;
p->cs_ide = 0;
p->cs_ramseyrev = -1;
p->cs_deniserev = -1;
p->cs_agnusrev = -1;
- p->cs_mbdmac = -1;
+ p->cs_mbdmac = 0;
+ p->cs_a2091 = 0;
p->cs_pcmcia = 0;
p->cs_ksmirror = 1;
p->cs_ciaatod = 0;
p->cs_fatgaryrev = 0;
p->cs_ramseyrev = 0x0f;
p->cs_ide = 2;
- p->cs_mbdmac = 1;
+ p->cs_mbdmac = 2;
break;
case 13: // A4000T
p->cs_rtc = 2;
p->cs_fatgaryrev = 0;
p->cs_ramseyrev = 0x0f;
p->cs_ide = 2;
- p->cs_mbdmac = 1;
+ p->cs_mbdmac = 2;
break;
}
return 1;
#endif
#include "gayle.h"
#include "gfxfilter.h"
+#include "a2091.h"
STATIC_INLINE int nocustom(void)
{
INTREQ_0 (data);
serial_check_irq ();
rethink_cias ();
+#ifdef A2091
+ rethink_a2091 ();
+#endif
}
static void INTREQ_d (uae_u16 v, int d)
}
inputdevice_hsync ();
- mbdmac_hsync();
+ gayle_hsync();
hsync_counter++;
//copper_check (2);
DISK_reset ();
CIA_reset ();
gayle_reset (0);
+#ifdef A2091
+ a2091_reset ();
+#endif
#ifdef JIT
compemu_reset ();
#endif
}
if (brk) {
if (m->frozen) {
- if (m->val_enabled)
- *valp = m->val;
+ if (m->val_enabled) {
+ int shift = addr - m->addr;
+ int max = 0;
+ if (m->val > 256)
+ max = 1;
+ if (m->val > 65536)
+ max = 3;
+ shift &= max;
+ *valp = m->val >> ((max - shift) * 8);
+ }
return 0;
}
mwhit.addr = addr;
}
}
}
+ if (mwn->frozen && mwn->rwi == 0)
+ mwn->rwi = 3;
memwatch_dump (num);
}
#include "zfile.h"
#include "catweasel.h"
#include "cdtv.h"
+#include "a2091.h"
#include "debug.h"
#define MAX_EXPANSION_BOARDS 8
static void expamem_init_fastcard (void)
{
+ uae_u16 mid = currprefs.cs_a2091 ? commodore : uae_id;
+ uae_u8 pid = currprefs.cs_a2091 ? commodore_a2091_ram : 1;
+
expamem_init_clear();
if (allocated_fastmem == 0x100000)
expamem_write (0x00, Z2_MEM_1MB + add_memory + zorroII);
expamem_write (0x08, care_addr);
- expamem_write (0x04, 1);
+ expamem_write (0x04, pid);
- expamem_write (0x10, uae_id >> 8);
- expamem_write (0x14, uae_id & 0xff);
+ expamem_write (0x10, mid >> 8);
+ expamem_write (0x14, mid & 0xff);
expamem_write (0x18, 0x00); /* ser.no. Byte 0 */
expamem_write (0x1c, 0x00); /* ser.no. Byte 1 */
return 0;
}
+void expamem_next(void)
+{
+ expamem_init_clear();
+ map_banks (&expamem_bank, 0xE8, 1, 0);
+ ++ecard;
+ if (ecard < MAX_EXPANSION_BOARDS)
+ (*card_init[ecard]) ();
+ else
+ expamem_init_clear2 ();
+}
+
+static void expamem_init_cdtv (void)
+{
+ cdtv_init();
+}
+static void expamem_init_a2091 (void)
+{
+ a2091_init();
+}
+
void expamem_reset (void)
{
int do_mount = 1;
allocate_expamem ();
- if (currprefs.cs_cdtvcd)
- cdtv_init ();
-
/* check if Kickstart version is below 1.3 */
if (! ersatzkickfile && kickstart_version
&& (/* Kickstart 1.0 & 1.1! */
card_init[cardno] = expamem_init_z3fastmem;
card_map[cardno++] = expamem_map_z3fastmem;
}
+#ifdef CDTV
+ if (currprefs.cs_cdtvcd) {
+ card_init[cardno] = expamem_init_cdtv;
+ card_map[cardno++] = NULL;
+ }
+#endif
+#ifdef A2091
+ if (currprefs.cs_a2091) {
+ card_init[cardno] = expamem_init_a2091;
+ card_map[cardno++] = NULL;
+ }
+#endif
#ifdef PICASSO96
if (gfxmemory != NULL) {
card_init[cardno] = expamem_init_gfxcard;
card_map[cardno++] = expamem_map_catweasel;
}
#endif
+
if (cardno > 0 && cardno < MAX_EXPANSION_BOARDS) {
card_init[cardno] = expamem_init_last;
card_map[cardno++] = expamem_map_clear;
#include "filesys.h"
#include "savestate.h"
#include "gui.h"
+#include "a2091.h"
+#include "ncr_scsi.h"
/*
D80000 to D8FFFF 64 KB SPARE chip select
DB0000 to DBFFFF 64 KB Not used(reserved for external IDE)
* DC0000 to DCFFFF 64 KB Real Time Clock(RTC)
DD0000 to DDFFFF 64 KB A3000 DMA controller
+DD0000 to DD1FFF A4000 DMAC
+DD2000 to DDFFFF A4000 IDE
DE0000 to DEFFFF 64 KB Motherboard resources
*/
+#define NCR_OFFSET 0x40
+
/* Gayle definitions from Linux drivers */
/* PCMCIA stuff */
dummy_lgeti, dummy_wgeti, ABFLAG_IO
};
+static int isa4000(uaecptr addr)
+{
+ if (currprefs.cs_mbdmac != 2)
+ return 0;
+ if ((addr & 0xffff) >= (GAYLE_BASE_4000 & 0xffff))
+ return 0;
+ return 1;
+}
+
static uae_u32 REGPARAM2 gayle_lget (uaecptr addr)
{
uae_u32 v;
{
int ide_reg;
uae_u16 v;
-
#ifdef JIT
special_mem |= S_READ;
#endif
+ if (isa4000(addr)) {
+ addr -= NCR_OFFSET;
+ return (ncr_bget(addr) << 8) | ncr_bget(addr + 1);
+ }
ide_reg = get_ide_reg(addr);
if (ide_reg == IDE_DATA)
return ide_get_data();
#ifdef JIT
special_mem |= S_READ;
#endif
+ if (isa4000(addr)) {
+ addr -= NCR_OFFSET;
+ return ncr_bget(addr);
+ }
return gayle_read (addr);
}
gayle_wput (addr, value >> 16);
gayle_wput (addr + 2, value & 0xffff);
}
-
static void REGPARAM2 gayle_wput (uaecptr addr, uae_u32 value)
{
int ide_reg;
-
#ifdef JIT
special_mem |= S_WRITE;
#endif
+ if (isa4000(addr)) {
+ addr -= NCR_OFFSET;
+ ncr_bput(addr, value >> 8);
+ ncr_bput(addr + 1, value);
+ return;
+ }
ide_reg = get_ide_reg(addr);
if (ide_reg == IDE_DATA) {
ide_put_data(value);
#ifdef JIT
special_mem |= S_WRITE;
#endif
+ if (isa4000(addr)) {
+ addr -= NCR_OFFSET;
+ ncr_bput(addr, value);
+ return;
+ }
gayle_write (addr, value);
}
dummy_lgeti, dummy_wgeti, ABFLAG_IO
};
-/* CNTR bits. */
-#define CNTR_TCEN (1<<5)
-#define CNTR_PREST (1<<4)
-#define CNTR_PDMD (1<<3)
-#define CNTR_INTEN (1<<2)
-#define CNTR_DDIR (1<<1)
-#define CNTR_IO_DX (1<<0)
-/* ISTR bits. */
-#define ISTR_INTX (1<<8)
-#define ISTR_INT_F (1<<7)
-#define ISTR_INTS (1<<6)
-#define ISTR_E_INT (1<<5)
-#define ISTR_INT_P (1<<4)
-#define ISTR_UE_INT (1<<3)
-#define ISTR_OE_INT (1<<2)
-#define ISTR_FF_FLG (1<<1)
-#define ISTR_FE_FLG (1<<0)
-
-static uae_u32 dmac_wtc, dmac_cntr, dmac_acr, dmac_istr, dmac_dawr, dmac_dma;
-static uae_u8 sasr, scmd;
-static int wdcmd_active;
-
-static void wd_cmd(uae_u8 data)
-{
- switch (sasr)
- {
- case 0x15:
- write_log("DESTINATION ID: %02.2X\n", data);
- break;
- case 0x18:
- write_log("COMMAND: %02.2X\n", data);
- wdcmd_active = 10;
- break;
- case 0x19:
- write_log("DATA: %02.2X\n", data);
- break;
- default:
- write_log("unsupported WD33C33A register %02.2X\n", sasr);
- break;
- }
-}
-
-void mbdmac_hsync(void)
+void gayle_hsync(void)
{
int i;
ide_interrupt_do(ide);
}
}
-
- if (wdcmd_active == 0)
- return;
- wdcmd_active--;
- if (wdcmd_active > 0)
- return;
- if (!(dmac_cntr & CNTR_INTEN)) {
- wdcmd_active = 1;
- return;
- }
- dmac_istr |= ISTR_INT_P | ISTR_E_INT | ISTR_INTS;
}
-static void dmac_start_dma(void)
-{
- dmac_istr |= ISTR_E_INT;
-}
-static void dmac_stop_dma(void)
-{
- dmac_dma = 0;
-}
-static void dmac_cint(void)
-{
- dmac_istr = 0;
-}
-static void dmacreg_write(uae_u32 *reg, int addr, uae_u32 val, int size)
-{
- addr = (size - 1) - addr;
- (*reg) &= ~(0xff << (addr * 8));
- (*reg) |= (val & 0xff) << (addr * 8);
-}
-static uae_u32 dmacreg_read(uae_u32 val, int addr, int size)
-{
- addr = (size - 1) - addr;
- return (val >> (addr * 8)) & 0xff;
-}
-
-static void mbdmac_write (uae_u32 addr, uae_u32 val)
-{
- if (GAYLE_LOG)
- write_log ("DMAC_WRITE %08.8X=%02.2X PC=%08.8X\n", addr, val & 0xff, M68K_GETPC);
- addr &= 0xffff;
- switch (addr)
- {
- case 0x02:
- case 0x03:
- dmacreg_write(&dmac_dawr, addr - 0x02, val, 2);
- break;
- case 0x04:
- case 0x05:
- case 0x06:
- case 0x07:
- dmacreg_write(&dmac_wtc, addr - 0x04, val, 4);
- break;
- case 0x0a:
- case 0x0b:
- dmacreg_write(&dmac_cntr, addr - 0x0a, val, 2);
- break;
- case 0x0c:
- case 0x0d:
- case 0x0e:
- case 0x0f:
- dmacreg_write(&dmac_acr, addr - 0x0c, val, 4);
- break;
- case 0x12:
- case 0x13:
- if (!dmac_dma) {
- dmac_dma = 1;
- dmac_start_dma();
- }
- break;
- case 0x16:
- case 0x17:
- /* FLUSH */
- break;
- case 0x1a:
- case 0x1b:
- dmac_cint();
- break;
- case 0x1e:
- case 0x1f:
- /* ISTR */
- break;
- case 0x3e:
- case 0x3f:
- dmac_dma = 0;
- dmac_stop_dma();
- break;
- case 0x49:
- sasr = val;
- break;
- case 0x43:
- wd_cmd(val);
- break;
- }
-}
-
-static uae_u32 mbdmac_read (uae_u32 addr)
-{
- uae_u32 vaddr = addr;
- uae_u32 v = 0xffffffff;
- addr &= 0xffff;
- switch (addr)
- {
- case 0x02:
- case 0x03:
- v = dmacreg_read(dmac_dawr, addr - 0x02, 2);
- break;
- case 0x04:
- case 0x05:
- case 0x06:
- case 0x07:
- v = dmacreg_read(dmac_wtc, addr - 0x04, 4);
- break;
- case 0x0a:
- case 0x0b:
- v = dmacreg_read(dmac_cntr, addr - 0x0a, 2);
- break;
- case 0x0c:
- case 0x0d:
- case 0x0e:
- case 0x0f:
- v = dmacreg_read(dmac_acr, addr - 0x0c, 4);
- break;
- case 0x12:
- case 0x13:
- if (dmac_dma) {
- dmac_dma = 1;
- dmac_start_dma();
- }
- v = 0;
- break;
- case 0x1a:
- case 0x1b:
- dmac_cint();
- v = 0;
- break;;
- case 0x1e:
- case 0x1f:
- v = dmacreg_read(dmac_istr, addr - 0x1e, 2);
- break;
- case 0x3e:
- case 0x3f:
- dmac_dma = 0;
- dmac_stop_dma();
- v = 0;
- break;
- case 0x49:
- v = sasr;
- break;
- case 0x43:
- v = scmd;
- break;
- }
- if (GAYLE_LOG)
- write_log ("DMAC_READ %08.8X=%02.2X PC=%X\n", vaddr, v & 0xff, M68K_GETPC);
- return v;
-}
-
-static uae_u32 REGPARAM3 mbdmac_lget (uaecptr) REGPARAM;
-static uae_u32 REGPARAM3 mbdmac_wget (uaecptr) REGPARAM;
-static uae_u32 REGPARAM3 mbdmac_bget (uaecptr) REGPARAM;
-static void REGPARAM3 mbdmac_lput (uaecptr, uae_u32) REGPARAM;
-static void REGPARAM3 mbdmac_wput (uaecptr, uae_u32) REGPARAM;
-static void REGPARAM3 mbdmac_bput (uaecptr, uae_u32) REGPARAM;
-
-static uae_u32 REGPARAM2 mbdmac_lget (uaecptr addr)
-{
-#ifdef JIT
- special_mem |= S_READ;
-#endif
- return (mbdmac_wget (addr) << 16) | mbdmac_wget (addr + 2);
-}
-static uae_u32 REGPARAM2 mbdmac_wget (uaecptr addr)
-{
-#ifdef JIT
- special_mem |= S_READ;
-#endif
- return (mbdmac_bget (addr) << 8) | mbdmac_bget(addr + 1);;
-}
-static uae_u32 REGPARAM2 mbdmac_bget (uaecptr addr)
-{
-#ifdef JIT
- special_mem |= S_READ;
-#endif
- return mbdmac_read (addr);
-}
-
-static void REGPARAM2 mbdmac_lput (uaecptr addr, uae_u32 value)
-{
-#ifdef JIT
- special_mem |= S_WRITE;
-#endif
- mbdmac_wput (addr, value >> 16);
- mbdmac_wput (addr + 2, value & 0xffff);
-}
-
-static void REGPARAM2 mbdmac_wput (uaecptr addr, uae_u32 value)
-{
-#ifdef JIT
- special_mem |= S_WRITE;
-#endif
- mbdmac_bput (addr, value);
- mbdmac_bput (addr, value + 1);
-}
-
-static void REGPARAM2 mbdmac_bput (uaecptr addr, uae_u32 value)
-{
-#ifdef JIT
- special_mem |= S_WRITE;
-#endif
- mbdmac_write (addr, value);
-}
-
-addrbank mbdmac_bank = {
- mbdmac_lget, mbdmac_wget, mbdmac_bget,
- mbdmac_lput, mbdmac_wput, mbdmac_bput,
- default_xlate, default_check, NULL, "A3000 DMAC",
- dummy_lgeti, dummy_wgeti, ABFLAG_IO
-};
-
static uae_u32 gayle_attr_read(uaecptr addr)
{
uae_u8 v = 0;
--- /dev/null
+#ifdef A2091
+
+extern addrbank dmaca2091_bank;
+
+extern void a2091_init (void);
+extern void a2091_free (void);
+extern void a2091_reset (void);
+
+extern void rethink_a2091 (void);
+
+#endif
extern void gayle_reset(int);
-extern void mbdmac_hsync(void);
+extern void gayle_hsync(void);
extern int gayle_add_ide_unit(int ch, char *path, int blocksize, int readonly,
char *devname, int sectors, int surfaces, int reserved,
int bootpri, char *filesys);
extern addrbank gayle_attr_bank;
extern addrbank mbres_bank;
extern addrbank akiko_bank;
-extern addrbank mbdmac_bank;
+extern addrbank mbdmac_a3000_bank;
extern addrbank cardmem_bank;
extern void rtarea_init (void);
extern void rtarea_setup (void);
extern void expamem_init (void);
extern void expamem_reset (void);
+extern void expamem_next (void);
extern uae_u32 gfxmem_start;
extern uae_u8 *gfxmemory;
--- /dev/null
+void ncr_bput(uacptr, uae_u32);
+uae_u32 ncr_bget(uaecptr);
int cs_agnusrev;
int cs_deniserev;
int cs_mbdmac;
+ int cs_a2091;
int cs_df0idhw;
char df[4][MAX_DPATH];
#include "savestate.h"
#include "filesys.h"
#include "parallel.h"
+#include "a2091.h"
#ifdef USE_SDL
#include "SDL.h"
#ifdef CDTV
cdtv_free ();
#endif
+#ifdef A2091
+ a2091_free ();
+#endif
#ifdef CD32
akiko_free ();
#endif
int i, j;
uaecptr a2 = a - 32;
uaecptr a3 = m68k_getpc(®s) - 32;
- write_log ("Your Amiga program just did something terribly stupid %p PC=%p\n", a, M68K_GETPC);
+ write_log ("Your Amiga program just did something terribly stupid %08.8X PC=%08.8X\n", a, M68K_GETPC);
m68k_dumpstate (0, 0);
for (i = 0; i < 10; i++) {
write_log ("%08.8X ", i >= 5 ? a3 : a2);
if (currprefs.cs_ramseyrev < 0)
changed_prefs.cs_ramseyrev = currprefs.cs_ramseyrev = 0x0f;
changed_prefs.cs_fatgaryrev = currprefs.cs_fatgaryrev = 0;
- changed_prefs.cs_mbdmac = currprefs.cs_mbdmac = 0;
+ changed_prefs.cs_mbdmac = currprefs.cs_mbdmac = 2;
}
}
}
map_banks (&mbres_bank, 0xDE, 1, 0);
if (currprefs.cs_cd32c2p || currprefs.cs_cd32cd || currprefs.cs_cd32nvram)
map_banks (&akiko_bank, AKIKO_BASE >> 16, 1, 0);
- if (currprefs.cs_mbdmac >= 0 && currprefs.cs_ide <= 0)
- map_banks (&mbdmac_bank, 0xDD, 1, 0);
+ if (currprefs.cs_mbdmac == 1)
+ map_banks (&mbdmac_a3000_bank, 0xDD, 1, 0);
if (a3000lmemory != 0)
map_banks (&a3000lmem_bank, a3000lmem_start >> 16, allocated_a3000lmem >> 16, 0);
if (a3000hmemory != 0)
--- /dev/null
+ /*
+ * UAE - The Un*x Amiga Emulator
+ *
+ * A4000T NCR 53C710 SCSI (nothing done yet)
+ *
+ * (c) 2007 Toni Wilen
+ */
+
+#define NCR_LOG 0
+
+#include "sysconfig.h"
+#include "sysdeps.h"
+
+#include "options.h"
+
+#include "memory.h"
+#include "custom.h"
+#include "newcpu.h"
+#include "ncr_scsi.h"
+
+#define NCR "NCR53C710"
+#define NCR_REGS 0x40
+
+static uae_u8 ncrregs[NCR_REGS];
+
+void ncr_bput(uaecptr addr, uae_u32 val)
+{
+ addr &= 0xffff;
+ if (addr >= NCR_REGS)
+ return;
+ write_log("%s write %04.4X = %02.2X\n", NCR, addr, val & 0xff);
+ ncrregs[addr] = val;
+}
+
+uae_u32 ncr_bget(uaecptr addr)
+{
+ uae_u32 v;
+
+ addr &= 0xffff;
+ if (addr >= NCR_REGS)
+ return 0;
+ v = ncrregs[addr];
+ write_log("%s read %04.4X\n", NCR, addr);
+ return v;
+}
if (regs.s && regs.m) regs.msp = m68k_areg(®s, 7);
if (regs.s && regs.m == 0) regs.isp = m68k_areg(®s, 7);
j = 2;
- f_out(f, " USP %08.8X ISP %08.8X ", regs.usp, regs.isp);
+ f_out(f, "USP %08.8X ISP %08.8X ", regs.usp, regs.isp);
for (i = 0; m2cregs[i].regno>= 0; i++) {
if (!movec_illg(m2cregs[i].regno)) {
if (j > 0 && (j % 4) == 0)
f_out(f, "\n");
- f_out (f, "%s %08.8X ", m2cregs[i].regname, val_move2c(m2cregs[i].regno));
+ f_out (f, "%-4s %08.8X ", m2cregs[i].regname, val_move2c(m2cregs[i].regno));
j++;
}
}
char *pname[] = { "OUT1", "OUT2", "MEM1", "MEM2", "DASM1", "DASM2", "BRKPTS", "MISC", "CUSTOM" };
static int pstatuscolor[MAXPAGES];
+static int dbgwnd_minx = 800, dbgwnd_miny = 600;
+
static void OutputCurrHistNode(HWND hWnd)
{
int txtlen;
static LRESULT CALLBACK ListboxProc(HWND hWnd, UINT message, WPARAM wParam, LPARAM lParam)
{
WNDPROC oldproc;
- HWND hinput;
-
+ HWND hinput, hsbar;
+ RECT rc, r;
+ int i, itemheight, count, height, bottom, width, id;
+ PAINTSTRUCT ps;
+ DRAWITEMSTRUCT dis;
+ HFONT oldfont, font;
+ HDC hdc, compdc;
+ HBITMAP compbmp, oldbmp;
+
switch (message) {
case WM_CHAR:
hinput = GetDlgItem(hDbgWnd, IDC_DBG_INPUT);
SetFocus(hinput);
SendMessage(hinput, WM_CHAR, wParam, lParam);
return TRUE;
+ case WM_ERASEBKGND:
+ return TRUE;
+ case WM_SETFOCUS:
+ return TRUE;
+ case WM_PAINT:
+ hdc = BeginPaint(hWnd, &ps);
+ GetClientRect(hWnd, &rc);
+ height = rc.bottom - rc.top;
+ width = rc.right - rc.left;
+ bottom = rc.bottom;
+ itemheight = SendMessage(hWnd, LB_GETITEMHEIGHT, 0, 0);
+ rc.bottom = itemheight;
+ count = SendMessage(hWnd, LB_GETCOUNT, 0, 0);
+ compdc = CreateCompatibleDC(hdc);
+ compbmp = CreateCompatibleBitmap(hdc, width, height);
+ oldbmp = SelectObject(compdc, compbmp);
+ font = (HFONT)SendMessage(hWnd, WM_GETFONT, 0, 0);
+ oldfont = SelectObject(compdc, font);
+ id = GetDlgCtrlID(hWnd);
+ dis.CtlType = ODT_LISTBOX;
+ dis.CtlID = id;
+ dis.itemAction = 0;
+ dis.itemState = 0;
+ dis.hwndItem = hWnd;
+ dis.hDC = compdc;
+ for (i = 0; i < count && rc.top < height; i++) {
+ dis.itemID = i;
+ dis.rcItem = rc;
+ dis.itemData = SendMessage(hWnd, LB_GETITEMDATA, i, 0);
+ SendMessage(hDbgWnd, WM_DRAWITEM, id, (LPARAM)&dis);
+ rc.top += itemheight;
+ rc.bottom += itemheight;
+ }
+ rc.bottom = bottom;
+ if (!IsWindowEnabled(hWnd))
+ FillRect(compdc, &rc, GetSysColorBrush(COLOR_3DFACE));
+ else
+ FillRect(compdc, &rc, GetSysColorBrush(COLOR_WINDOW));
+ GetWindowRect(hWnd, &rc);
+ hsbar = GetDlgItem(hDbgWnd, IDC_DBG_STATUS);
+ GetWindowRect(hsbar, &r);
+ if (rc.top < r.top) { // not below status bar
+ if (rc.bottom > r.top) // partly visible
+ height -= rc.bottom - r.top;
+ BitBlt(hdc, 0, 0, width, height, compdc, 0, 0, SRCCOPY);
+ }
+ SelectObject(compdc, oldfont);
+ SelectObject(compdc, oldbmp);
+ DeleteObject(compbmp);
+ DeleteDC(compdc);
+ EndPaint(hWnd, &ps);
+ return TRUE;
}
oldproc = (WNDPROC)GetWindowLongPtr(hWnd, GWL_USERDATA);
return CallWindowProc(oldproc, hWnd, message, wParam, lParam);
static BOOL CALLBACK InitChildWindows(HWND hWnd, LPARAM lParam)
{
- int id, enable = TRUE;
+ int i, id, enable = TRUE, items = 0;
WNDPROC newproc = NULL, oldproc;
char classname[CLASSNAMELENGTH];
+ WINDOWINFO pwi;
+ RECT *r;
id = GetDlgCtrlID(hWnd);
switch (id) {
newproc = ListboxProc;
enable = currprefs.cpu_model < 68020 ? FALSE : TRUE;
break;
+ case IDC_DBG_MISCCPU:
+ if (currprefs.cpu_model == 68000) {
+ items = 4;
+ enable = FALSE;
+ }
+ else {
+ for (i = 0; m2cregs[i].regno>= 0; i++) {
+ if (!movec_illg(m2cregs[i].regno))
+ items++;
+ }
+ }
+ pwi.cbSize = sizeof pwi;
+ GetWindowInfo(hWnd, &pwi);
+ r = &pwi.rcClient;
+ r->bottom = r->top + items * GetTextSize(hWnd, NULL, FALSE);
+ AdjustWindowRectEx(r, pwi.dwStyle, FALSE, pwi.dwExStyle);
+ SetWindowPos(hWnd, 0, 0, 0, r->right - r->left, r->bottom - r->top, SWP_NOMOVE | SWP_NOZORDER);
+ newproc = ListboxProc;
+ break;
default:
if (GetClassName(hWnd, classname, CLASSNAMELENGTH)) {
if (!strcmp(classname, "ListBox"))
LONG x, y, w, h;
DWORD regkeytype;
DWORD regkeysize = sizeof(LONG);
+ RECT rw;
+ GetWindowRect(hDlg, &rw);
+ dbgwnd_minx = rw.right - rw.left;
+ dbgwnd_miny = rw.bottom - rw.top;
GetClientRect(hDlg, &dlgRect);
if (hWinUAEKey) {
newpos = 1;
SetWindowPos(hDlg, 0, x, y, w, h, SWP_NOOWNERZORDER | SWP_NOREDRAW | SWP_NOACTIVATE | SWP_DEFERERASE);
}
SendMessage(hDlg, WM_SETICON, ICON_SMALL, (LPARAM)LoadIcon (GetModuleHandle(NULL), MAKEINTRESOURCE(IDI_APPICON)));
- EnumChildWindows(hDlg, InitChildWindows, 0);
- currpage = -1;
- firsthist = lasthist = currhist = NULL;
- histcount = 0;
- inputfinished = 0;
+ EnumChildWindows(hDlg, InitChildWindows, 0);
+ currpage = -1;
+ firsthist = lasthist = currhist = NULL;
+ histcount = 0;
+ inputfinished = 0;
AdjustDialog(hDlg);
- return TRUE;
+ return TRUE;
}
case WM_CLOSE:
DestroyWindow(hDlg);
case WM_GETMINMAXINFO:
{
MINMAXINFO *mmi = (MINMAXINFO*)lParam;
- mmi->ptMinTrackSize.x = 640;
- mmi->ptMinTrackSize.y = 480;
+ mmi->ptMinTrackSize.x = dbgwnd_minx;
+ mmi->ptMinTrackSize.y = dbgwnd_miny;
return TRUE;
}
case WM_EXITSIZEMOVE:
#define IDC_AVIOUTPUT_AUDIO 1614
#define IDC_INPUTCOPYFROM 1614
#define IDC_AVIOUTPUT_VIDEO_CODEC 1615
-#define IDC_OPENGLENABLE 1615
#define IDC_INPUTDEVICEDISABLE 1615
#define IDC_AVIOUTPUT_ACTIVATED 1615
#define IDC_FILTERENABLE 1615
#define IDC_AVIOUTPUT_AUDIO_CODEC 1616
-#define IDC_OPENGLHZ 1616
#define IDC_INPUTAMIGACNT 1616
#define IDC_FILTERHZ 1616
#define IDC_SAMPLERIPPER_ACTIVATED 1616
#define IDC_AVIOUTPUT_BORDER_TRIM 1617
-#define IDC_OPENGLVZ 1617
#define IDC_FILTERVZ 1617
#define IDC_INPREC_RECORD 1617
#define IDC_AVIOUTPUT_AUDIO_STATIC 1618
-#define IDC_OPENGLHO 1618
#define IDC_FILTERHO 1618
#define IDC_AVIOUTPUT_VIDEO_STATIC 1619
-#define IDC_OPENGLVO 1619
#define IDC_FILTERVO 1619
#define IDC_AVIOUTPUT_8BIT 1620
-#define IDC_OPENGLHZV 1620
#define IDC_INPREC_PLAY 1620
#define IDC_AVIOUTPUT_24BIT 1621
-#define IDC_OPENGLVZV 1621
#define IDC_AVIOUTPUT_WIDTH 1622
-#define IDC_OPENGLHOV 1622
#define IDC_AVIOUTPUT_HEIGHT 1623
-#define IDC_OPENGLVOV 1623
#define IDC_AVIOUTPUT_FRAME 1624
-#define IDC_OPENGLSL 1624
-#define IDC_FILTERSL 1624
#define IDC_FILTERXL 1624
-#define IDC_OPENGLSLR 1625
#define IDC_FILTERSLR 1625
-#define IDC_OPENGLSLV 1626
#define IDC_FILTERHZMULT 1626
-#define IDC_OPENGLBITS 1627
-#define IDC_OPENGLMODE 1627
#define IDC_FILTERMODE 1627
-#define IDC_OPENGLFILTER 1628
#define IDC_FILTERFILTER 1628
-#define IDC_OPENGLDEFAULT 1629
#define IDC_FILTERDEFAULT 1629
-#define IDC_INPUTDEADZONE 1630
-#define IDC_OPENGLSL2 1630
-#define IDC_FILTERSL2 1630
#define IDC_FILTERXTRA 1630
+#define IDC_INPUTDEADZONE 1630
#define IDC_INPUTCOPY 1631
-#define IDC_OPENGLSL2V 1631
#define IDC_FILTERPRESETS 1631
#define IDC_SCREENSHOT 1632
#define IDC_INPUTSWAP 1632
#define IDC_FILTERPRESETDELETE 1634
#define IDC_HARDDRIVE 1635
#define IDC_INACTIVE_PRI 1635
-#define IDC_FILTERSLR3 1635
#define IDC_FILTERVZMULT 1635
#define IDC_SOUNDPRIMARY 1636
#define IDC_MINIMIZED_PRI 1636
#define IDC_DF1WPQ 1686
#define IDC_EJECT1Q 1687
#define IDC_DF1TEXTQ 1688
-#define IDC_FILTERSL2V 1691
-#define IDC_FILTERSLV 1692
#define IDC_FILTERXLV 1692
#define IDC_FILTERVOV 1693
#define IDC_FILTERHOV 1694
#define IDC_CS_AGNUSREV2 1738
#define IDC_CS_DENISEREV 1738
#define IDC_DBG_OUTPUT1 1739
+#define IDC_CS_DMAC2 1739
#define IDC_DBG_HELP 1740
#define IDC_DBG_INPUT 1741
#define IDC_DBG_DREG 1742
#define IDC_DBG_CCR 1744
#define IDC_DBG_AMEM 1745
#define IDC_DBG_SP_VBR 1746
-#define IDC_DBG_MISC 1747
+#define IDC_DBG_MMISC 1747
#define IDC_DBG_PC 1748
#define IDC_DBG_PREFETCH 1749
#define IDC_DBG_FPREG 1750
#define IDC_DBG_MEMTOPC 1759
#define IDC_DBG_MEMUPFAST 1760
#define IDC_DA_RESET 1761
+#define IDC_DBG_STATUS 1762
+#define IDC_DBG_BRKPTS 1763
+#define IDC_DBG_MCUSTOM 1764
+#define IDC_DBG_MISC 1765
+#define IDC_DBG_CUSTOM 1766
+#define IDC_DBG_MISCCPU 1767
+#define IDC_CS_A2091 1768
#define ID__FLOPPYDRIVES 40004
#define ID_FLOPPYDRIVES_DF0 40005
#define ID_ST_CONFIGURATION 40010
#define ID_DBG_PAGE4 40023
#define ID_DBG_PAGE5 40024
#define ID_DBG_PAGE6 40025
+#define ID_DBG_PAGE7 40026
+#define ID_DBG_PAGE8 40027
+#define ID_DBG_PAGE9 40028
// Next default values for new objects
//
#define _APS_NO_MFC 1
#define _APS_3D_CONTROLS 1
#define _APS_NEXT_RESOURCE_VALUE 253
-#define _APS_NEXT_COMMAND_VALUE 40026
-#define _APS_NEXT_CONTROL_VALUE 1761
+#define _APS_NEXT_COMMAND_VALUE 40029
+#define _APS_NEXT_CONTROL_VALUE 1769
#define _APS_NEXT_SYMED_VALUE 101
#endif
#endif
#define IDC_DBG_MISC 1765
#define IDC_DBG_CUSTOM 1766
#define IDC_DBG_MISCCPU 1767
+#define IDC_CS_A2091 1768
+#define IDC_CS_DMAC2 1769
#define ID__FLOPPYDRIVES 40004
#define ID_FLOPPYDRIVES_DF0 40005
#define _APS_3D_CONTROLS 1
#define _APS_NEXT_RESOURCE_VALUE 253
#define _APS_NEXT_COMMAND_VALUE 40029
-#define _APS_NEXT_CONTROL_VALUE 1768
+#define _APS_NEXT_CONTROL_VALUE 1770
#define _APS_NEXT_SYMED_VALUE 101
#endif
#endif
VK_RIGHT, IDC_DBG_MEMDOWNFAST, VIRTKEY, ALT, NOINVERT
VK_UP, IDC_DBG_MEMUP, VIRTKEY, ALT, NOINVERT
VK_LEFT, IDC_DBG_MEMUPFAST, VIRTKEY, ALT, NOINVERT
- "h", IDC_DBG_HELP, VIRTKEY, ALT, NOINVERT
- "p", IDC_DBG_MEMTOPC, VIRTKEY, ALT, NOINVERT
+ "H", IDC_DBG_HELP, VIRTKEY, ALT, NOINVERT
+ "P", IDC_DBG_MEMTOPC, VIRTKEY, ALT, NOINVERT
END
CONTROL "Vertical Sync",IDC_CS_CIAA_TOD1,"Button",BS_AUTORADIOBUTTON | WS_GROUP | WS_TABSTOP,25,81,63,10
CONTROL "Power Supply 50Hz",IDC_CS_CIAA_TOD2,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,95,81,85,10
CONTROL "Power Supply 60Hz",IDC_CS_CIAA_TOD3,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,192,81,88,10
- CONTROL "Boot ROM Mirror",IDC_CS_KSMIRROR,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,17,128,80,10
- CONTROL "A1000 Boot RAM/ROM",IDC_CS_A1000RAM,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,100,128,88,10
- CONTROL "CD32 CD",IDC_CS_CD32CD,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,17,141,76,10
- CONTROL "CD32 C2P",IDC_CS_CD32C2P,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,100,141,87,10
- CONTROL "CD32 NVRAM",IDC_CS_CD32NVRAM,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,193,141,84,10
- CONTROL "CDTV CD",IDC_CS_CDTVCD,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,17,154,47,10
- CONTROL "CDTV SRAM",IDC_CS_CDTVRAM,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,100,153,87,10
- CONTROL "CDTV SRAM Expansion",IDC_CS_CDTVRAMEXP,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,193,153,90,10
- CONTROL "A600/A1200 IDE",IDC_CS_IDE1,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,17,166,79,10
- CONTROL "A4000 IDE",IDC_CS_IDE2,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,100,166,88,10
- CONTROL "Ramsey revision:",IDC_CS_RAMSEY,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,17,201,71,10
- EDITTEXT IDC_CS_RAMSEYREV,94,199,45,13,ES_AUTOHSCROLL
- CONTROL "Fat Gary revision:",IDC_CS_FATGARY,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,17,214,71,10
- EDITTEXT IDC_CS_FATGARYREV,94,213,45,13,ES_AUTOHSCROLL
- CONTROL "Motherboard Super DMAC",IDC_CS_DMAC,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,17,227,118,10
+ CONTROL "Boot ROM Mirror",IDC_CS_KSMIRROR,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,17,108,80,10
+ CONTROL "A1000 Boot RAM/ROM",IDC_CS_A1000RAM,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,100,108,88,10
+ CONTROL "CD32 CD",IDC_CS_CD32CD,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,17,121,76,10
+ CONTROL "CD32 C2P",IDC_CS_CD32C2P,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,100,121,87,10
+ CONTROL "CD32 NVRAM",IDC_CS_CD32NVRAM,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,193,121,84,10
+ CONTROL "CDTV CD",IDC_CS_CDTVCD,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,17,134,47,10
+ CONTROL "CDTV SRAM",IDC_CS_CDTVRAM,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,100,133,87,10
+ CONTROL "CDTV SRAM Expansion",IDC_CS_CDTVRAMEXP,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,193,133,90,10
+ CONTROL "A600/A1200 IDE",IDC_CS_IDE1,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,17,146,79,10
+ CONTROL "A4000/A4000T IDE",IDC_CS_IDE2,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,100,146,88,10
+ CONTROL "Ramsey revision:",IDC_CS_RAMSEY,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,17,211,71,10
+ EDITTEXT IDC_CS_RAMSEYREV,94,209,45,13,ES_AUTOHSCROLL
+ CONTROL "Fat Gary revision:",IDC_CS_FATGARY,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,17,224,71,10
+ EDITTEXT IDC_CS_FATGARYREV,94,223,45,13,ES_AUTOHSCROLL
+ CONTROL "A3000 SCSI",IDC_CS_DMAC,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,100,175,76,10
CONTROL "Compatible Settings",IDC_CS_COMPATIBLE,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,17,21,234,10
- CONTROL "DF0: ID Hardware",IDC_CS_DF0IDHW,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,193,128,92,10
- CONTROL "Agnus/Alice revision:",IDC_CS_AGNUS,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,150,201,81,10
- EDITTEXT IDC_CS_AGNUSREV,235,199,45,13,ES_AUTOHSCROLL
- CONTROL "Denise/Lisa revision:",IDC_CS_DENISE,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,150,217,81,10
- EDITTEXT IDC_CS_DENISEREV,235,216,45,13,ES_AUTOHSCROLL
+ CONTROL "DF0: ID Hardware",IDC_CS_DF0IDHW,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,193,108,92,10
+ CONTROL "Agnus/Alice revision:",IDC_CS_AGNUS,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,150,211,81,10
+ EDITTEXT IDC_CS_AGNUSREV,235,209,45,13,ES_AUTOHSCROLL
+ CONTROL "Denise/Lisa revision:",IDC_CS_DENISE,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,150,227,81,10
+ EDITTEXT IDC_CS_DENISEREV,235,226,45,13,ES_AUTOHSCROLL
+ CONTROL "A590/A2091 SCSI",IDC_CS_A2091,"Button",BS_AUTOCHECKBOX | WS_DISABLED | WS_TABSTOP,17,175,76,10
+ CONTROL "A4000T SCSI",IDC_CS_DMAC2,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,193,175,88,10
+ LTEXT "SCSI not yet implemented.",IDC_STATIC,25,161,224,8,SS_CENTERIMAGE
END
IDD_AVIOUTPUT DIALOGEX 0, 0, 288, 203
FONT 8, "MS Sans Serif", 0, 0, 0x0
BEGIN
PUSHBUTTON "Cancel",IDCANCEL,88,40,50,14
- CONTROL "",IDC_PROGRESSBAR,"msctls_progress32",WS_BORDER | 0x1,7,19,215,14
+ CONTROL "",IDC_PROGRESSBAR,"msctls_progress32",PBS_SMOOTH | WS_BORDER,7,19,215,14
CTEXT "x",IDC_PROGRESSBAR_TEXT,23,5,187,10,SS_CENTERIMAGE | WS_TABSTOP
END
CTEXT "Custom input event",IDC_STRINGBOX_TEXT,23,5,187,10,SS_CENTERIMAGE | WS_TABSTOP
END
-IDD_DEBUGGER DIALOGEX 0, 0, 454, 311
+IDD_DEBUGGER DIALOGEX 0, 0, 454, 368
STYLE DS_LOCALEDIT | DS_SETFONT | DS_MODALFRAME | DS_3DLOOK | WS_POPUP | WS_CAPTION | WS_THICKFRAME
EXSTYLE WS_EX_CONTROLPARENT
CAPTION "WinUAE Debugger"
FONT 8, "Courier New", 0, 0, 0x0
BEGIN
- EDITTEXT IDC_DBG_OUTPUT1,1,79,370,205,ES_MULTILINE | ES_AUTOVSCROLL | ES_READONLY | ES_WANTRETURN | WS_VSCROLL | NOT WS_TABSTOP
- EDITTEXT IDC_DBG_OUTPUT2,1,79,370,205,ES_MULTILINE | ES_AUTOVSCROLL | ES_READONLY | ES_WANTRETURN | WS_VSCROLL | NOT WS_TABSTOP
- LISTBOX IDC_DBG_MEM,1,92,370,192,LBS_OWNERDRAWFIXED | LBS_HASSTRINGS | LBS_NOINTEGRALHEIGHT
- LISTBOX IDC_DBG_DASM,1,92,370,192,LBS_OWNERDRAWFIXED | LBS_HASSTRINGS | LBS_NOINTEGRALHEIGHT
+ EDITTEXT IDC_DBG_OUTPUT1,1,79,370,262,ES_MULTILINE | ES_AUTOVSCROLL | ES_READONLY | ES_WANTRETURN | WS_VSCROLL | NOT WS_TABSTOP
+ EDITTEXT IDC_DBG_OUTPUT2,1,79,370,262,ES_MULTILINE | ES_AUTOVSCROLL | ES_READONLY | ES_WANTRETURN | WS_VSCROLL | NOT WS_TABSTOP
+ LISTBOX IDC_DBG_MEM,1,92,370,249,LBS_OWNERDRAWFIXED | LBS_HASSTRINGS | LBS_NOINTEGRALHEIGHT
+ LISTBOX IDC_DBG_DASM,1,92,370,249,LBS_OWNERDRAWFIXED | LBS_HASSTRINGS | LBS_NOINTEGRALHEIGHT
EDITTEXT IDC_DBG_MEMINPUT,1,79,36,12,ES_AUTOHSCROLL | ES_WANTRETURN
- EDITTEXT IDC_DBG_INPUT,1,285,354,12,ES_AUTOHSCROLL | ES_WANTRETURN
- PUSHBUTTON "?",IDC_DBG_HELP,356,285,15,12,NOT WS_TABSTOP
+ EDITTEXT IDC_DBG_INPUT,1,342,354,12,ES_AUTOHSCROLL | ES_WANTRETURN
+ PUSHBUTTON "?",IDC_DBG_HELP,356,342,15,12,NOT WS_TABSTOP
PUSHBUTTON "Set to PC",IDC_DBG_MEMTOPC,38,79,45,12,NOT WS_TABSTOP
LISTBOX IDC_DBG_DREG,1,1,52,66,LBS_OWNERDRAWFIXED | LBS_HASSTRINGS | LBS_NOINTEGRALHEIGHT
LISTBOX IDC_DBG_AREG,54,1,52,66,LBS_OWNERDRAWFIXED | LBS_HASSTRINGS | LBS_NOINTEGRALHEIGHT
LISTBOX IDC_DBG_PREFETCH,54,68,283,10,LBS_OWNERDRAWFIXED | LBS_HASSTRINGS | LBS_NOINTEGRALHEIGHT
LISTBOX IDC_DBG_FPREG,372,218,81,66,LBS_OWNERDRAWFIXED | LBS_HASSTRINGS | LBS_NOINTEGRALHEIGHT
LISTBOX IDC_DBG_FPSR,372,285,81,34,LBS_OWNERDRAWFIXED | LBS_HASSTRINGS | LBS_NOINTEGRALHEIGHT
- LISTBOX IDC_DBG_MISCCPU,372,319,81,34,LBS_OWNERDRAWFIXED | LBS_HASSTRINGS | LBS_NOINTEGRALHEIGHT
- CONTROL "",IDC_DBG_STATUS,"msctls_statusbar32",CCS_BOTTOM | SBARS_SIZEGRIP,0,298,453,12
- LISTBOX IDC_DBG_BRKPTS,1,79,370,205,LBS_OWNERDRAWFIXED | LBS_HASSTRINGS | LBS_NOINTEGRALHEIGHT | LBS_DISABLENOSCROLL | WS_VSCROLL
+ LISTBOX IDC_DBG_MISCCPU,372,320,81,34,LBS_OWNERDRAWFIXED | LBS_HASSTRINGS | LBS_NOINTEGRALHEIGHT
+ CONTROL "",IDC_DBG_STATUS,"msctls_statusbar32",CCS_BOTTOM | SBARS_SIZEGRIP,0,355,453,12
+ LISTBOX IDC_DBG_BRKPTS,1,79,370,262,LBS_OWNERDRAWFIXED | LBS_HASSTRINGS | LBS_NOINTEGRALHEIGHT | LBS_DISABLENOSCROLL | WS_VSCROLL
LISTBOX IDC_DBG_MCUSTOM,372,79,81,138,LBS_OWNERDRAWFIXED | LBS_HASSTRINGS | LBS_NOINTEGRALHEIGHT
- LISTBOX IDC_DBG_MISC,1,79,370,205,LBS_OWNERDRAWFIXED | LBS_HASSTRINGS | LBS_NOINTEGRALHEIGHT | LBS_DISABLENOSCROLL | WS_VSCROLL
- LISTBOX IDC_DBG_CUSTOM,1,79,370,205,LBS_OWNERDRAWFIXED | LBS_HASSTRINGS | LBS_NOINTEGRALHEIGHT | LBS_DISABLENOSCROLL | WS_VSCROLL
+ LISTBOX IDC_DBG_MISC,1,79,370,262,LBS_OWNERDRAWFIXED | LBS_HASSTRINGS | LBS_NOINTEGRALHEIGHT | LBS_DISABLENOSCROLL | WS_VSCROLL
+ LISTBOX IDC_DBG_CUSTOM,1,79,370,262,LBS_OWNERDRAWFIXED | LBS_HASSTRINGS | LBS_NOINTEGRALHEIGHT | LBS_DISABLENOSCROLL | WS_VSCROLL
END
static int serial_period_hsyncs, serial_period_hsync_counter;
static int ninebit;
int serdev;
+int seriallog;
void serial_open(void);
void serial_close(void);
if (!(w & 0x3ff)) {
#if SERIALDEBUG > 1
- write_log ("SERIAL: zero serial word written?! PC=%x\n", m68k_getpc());
+ write_log ("SERIAL: zero serial word written?! PC=%x\n", M68K_GETPC);
#endif
return;
}
}
#endif
+ if (seriallog)
+ console_out("%c", dochar (w));
+
if (serper == 372) {
extern int enforcermode;
if (enforcermode & 2) {
checksend (1);
#if SERIALDEBUG > 2
- write_log ("SERIAL: wrote 0x%04x (%c) PC=%x\n", w, dochar (w), m68k_getpc());
+ write_log ("SERIAL: wrote 0x%04x (%c) PC=%x\n", w, dochar (w), M68K_GETPC);
#endif
return;
#define ARCHIVEACCESS /* ArchiveAccess decompression library */
#define LOGITECHLCD /* Logitech G15 LCD */
#define SAVESTATE /* State file support */
+#define A2091 /* A590/A2091 SCSI */
#else
#define GETBDM(x) (((x) - ((x / 10000) * 10000)) / 100)
#define GETBDD(x) ((x) % 100)
-#define WINUAEBETA 10
+#define WINUAEBETA 11
#define WINUAEPUBLICBETA 1
-#define WINUAEDATE MAKEBD(2007, 5, 1)
+#define WINUAEDATE MAKEBD(2007, 5, 6)
//#define WINUAEEXTRA ""
#define IHF_WINDOWHIDDEN 6
fs_warning = IDS_UNSUPPORTEDSCREENMODE_1;
} else if (colortype == RGBFB_CLUT && !(currentmode->flags & DM_OVERLAY)) {
fs_warning = IDS_UNSUPPORTEDSCREENMODE_2;
- } else if (currentmode->native_width >= GetSystemMetrics(SM_CXVIRTUALSCREEN) ||
- currentmode->native_height >= GetSystemMetrics(SM_CYVIRTUALSCREEN)) {
+ } else if (currentmode->current_width >= GetSystemMetrics(SM_CXVIRTUALSCREEN) ||
+ currentmode->current_height >= GetSystemMetrics(SM_CYVIRTUALSCREEN)) {
if (!console_logging)
fs_warning = IDS_UNSUPPORTEDSCREENMODE_3;
#ifdef PICASSO96
CheckDlgButton (hDlg, IDC_CS_FATGARY, workprefs.cs_fatgaryrev >= 0);
CheckDlgButton (hDlg, IDC_CS_AGNUS, workprefs.cs_agnusrev >= 0);
CheckDlgButton (hDlg, IDC_CS_DENISE, workprefs.cs_deniserev >= 0);
- CheckDlgButton (hDlg, IDC_CS_DMAC, workprefs.cs_mbdmac >= 0);
+ CheckDlgButton (hDlg, IDC_CS_DMAC, workprefs.cs_mbdmac == 1);
+ CheckDlgButton (hDlg, IDC_CS_DMAC2, workprefs.cs_mbdmac == 2);
+ CheckDlgButton (hDlg, IDC_CS_A2091, workprefs.cs_a2091 > 0);
CheckDlgButton (hDlg, IDC_CS_IDE1, workprefs.cs_ide > 0 && (workprefs.cs_ide & 1));
CheckDlgButton (hDlg, IDC_CS_IDE2, workprefs.cs_ide > 0 && (workprefs.cs_ide & 2));
txt[0] = 0;
workprefs.cs_a1000ram = IsDlgButtonChecked (hDlg, IDC_CS_A1000RAM);
workprefs.cs_ramseyrev = IsDlgButtonChecked (hDlg, IDC_CS_RAMSEY) ? 0x0f : -1;
workprefs.cs_fatgaryrev = IsDlgButtonChecked (hDlg, IDC_CS_FATGARY) ? 0x00 : -1;
- workprefs.cs_mbdmac = IsDlgButtonChecked (hDlg, IDC_CS_DMAC) ? 0x00 : -1;
+ workprefs.cs_mbdmac = IsDlgButtonChecked (hDlg, IDC_CS_DMAC) ? 1 : 0;
+ if (workprefs.cs_mbdmac == 0)
+ workprefs.cs_mbdmac = IsDlgButtonChecked (hDlg, IDC_CS_DMAC2) ? 2 : 0;
+ workprefs.cs_a2091 = IsDlgButtonChecked (hDlg, IDC_CS_A2091) ? 1 : 0;
workprefs.cs_ide = IsDlgButtonChecked (hDlg, IDC_CS_IDE1) ? 1 : (IsDlgButtonChecked (hDlg, IDC_CS_IDE2) ? 2 : 0);
workprefs.cs_ciaatod = IsDlgButtonChecked (hDlg, IDC_CS_CIAA_TOD1) ? 0
: (IsDlgButtonChecked (hDlg, IDC_CS_CIAA_TOD2) ? 1 : 2);
ew (hDlg, IDC_CS_IDE1, e);
ew (hDlg, IDC_CS_IDE2, e);
ew (hDlg, IDC_CS_DMAC, e);
+ ew (hDlg, IDC_CS_DMAC2, e);
+#if WINUAEBETA > 0
+ ew (hDlg, IDC_CS_A2091, e);
+#endif
ew (hDlg, IDC_CS_CD32CD, e);
ew (hDlg, IDC_CS_CD32NVRAM, e);
ew (hDlg, IDC_CS_CD32C2P, e);
Name="common"
Filter="cpp;c;cxx;rc;def;r;odl;idl;hpj;bat"
>
+ <File
+ RelativePath="..\..\a2091.c"
+ >
+ </File>
<File
RelativePath="..\..\akiko.c"
>
RelativePath="..\..\native2amiga.c"
>
</File>
+ <File
+ RelativePath="..\..\ncr_scsi.c"
+ >
+ </File>
<File
RelativePath="..\..\newcpu.c"
>
+Beta 11:
+
+- fixed randomly lost CDTV CD transfer finished interrupt in
+ CE-mode
+- fixed windowed mode size check
+- added some preliminary SCSI hardware emulation stuff
+ - A3000, minimal support, KS driver detects SCSI controller
+ with no SCSI devices connected. (SuperDMAC + WD33C93)
+ - A590/A2091, (DMAC + WD33C93), minimal support, boot ROM
+ (tested with rev7) detects controller with no SCSI devices.
+ (check log if for some weird reason you want to test it..)
+ - A4000T NCR53C710, nothing implemented yet (no datasheet)
+- CDTV and A590/A2091 autoconfig chained with UAE autoconfig
+ devices (fast ram, HD etc works in CDTV mode)
+- more GUI debugger updates
+
Beta 10:
- CDTV CDROM command 0x09 (play audio cd in lsn mode) fixed, parameters
projects / francis / winuae.git / commitdiff