flags |= 0x400;
}
}
- out("\tmmufixup[%d].reg = %s | 0x%x;\n", mmufixupcnt, reg, flags);
- out("\tmmufixup[%d].value = m68k_areg(regs, %s);\n", mmufixupcnt, reg);
+ out("mmufixup[%d].reg = %s | 0x%x;\n", mmufixupcnt, reg, flags);
+ out("mmufixup[%d].value = m68k_areg(regs, %s);\n", mmufixupcnt, reg);
mmufixupstate |= 1 << mmufixupcnt;
mmufixupcnt++;
}
static void clearmmufixup(int cnt, int noclear)
{
if (mmufixupstate & (1 << cnt)) {
- out("\tmmufixup[%d].reg = -1;\n", cnt);
+ out("mmufixup[%d].reg = -1;\n", cnt);
if (!noclear)
mmufixupstate &= ~(1 << cnt);
}
#if 0
if (cycles > 0) {
if (s == NULL)
- out("\t%s(%d);\n", do_cycles, cycles);
+ out("%s(%d);\n", do_cycles, cycles);
else
- out("\t%s(%d); /* %s */\n", do_cycles, cycles, s);
+ out("%s(%d); /* %s */\n", do_cycles, cycles, s);
}
#endif
count_cycles += cycles;
{
if (!isprefetch020() || no_prefetch_ce020)
return;
- out("\tregs.irc = %s(%d);\n", prefetch_opcode, m68k_pc_offset);
+ out("regs.irc = %s(%d);\n", prefetch_opcode, m68k_pc_offset);
}
static void get_prefetch_020_continue(void)
{
return;
if (using_ce020) {
if (using_ce020 > 1)
- out("\tcontinue_ce030_prefetch();\n");
+ out("continue_ce030_prefetch();\n");
else
- out("\tcontinue_ce020_prefetch();\n");
+ out("continue_ce020_prefetch();\n");
} else {
if (using_prefetch_020 > 1)
- out("\tcontinue_030_prefetch();\n");
+ out("continue_030_prefetch();\n");
else
- out("\tcontinue_020_prefetch();\n");
+ out("continue_020_prefetch();\n");
}
}
total_ce020 -= 2;
#if 0
if (iswrite) {
- out("\t/* C - %d = %d */\n", memory_cycle_cnt, total_ce020 - memory_cycle_cnt);
+ out("/* C - %d = %d */\n", memory_cycle_cnt, total_ce020 - memory_cycle_cnt);
total_ce020 -= memory_cycle_cnt;
} else {
- out("\t/* C = %d */\n", total_ce020);
+ out("/* C = %d */\n", total_ce020);
}
#endif
if (0 && total_ce020 <= 0) {
- out("\t/* C was zero */\n");
+ out("/* C was zero */\n");
total_ce020 = 1;
}
if (!did_prefetch)
if (total_ce020 > 0)
addcycles_ce020 (total_ce020);
- //out("\tregs.irc = %s;\n", prefetch_opcode);
+ //out("regs.irc = %s;\n", prefetch_opcode);
if (0 && total_ce020 >= 2) {
- out("\top_cycles = get_cycles() - op_cycles;\n");
- out("\top_cycles /= cpucycleunit;\n");
- out("\tif (op_cycles < %d) {\n", total_ce020);
- out("\t\tdo_cycles_ce020((%d) - op_cycles);\n", total_ce020);
- out("\t}\n");
+ out("op_cycles = get_cycles() - op_cycles;\n");
+ out("op_cycles /= cpucycleunit;\n");
+ out("if (op_cycles < %d) {\n", total_ce020);
+ out("do_cycles_ce020((%d) - op_cycles);\n", total_ce020);
+ out("}\n");
}
#if 0
if (tail_ce020 > 0) {
- out("\tregs.ce020_tail = %d * cpucycleunit;\n", tail_ce020);
- out("\tregs.ce020_tail_cycles = get_cycles() + regs.ce020_tail;\n");
+ out("regs.ce020_tail = %d * cpucycleunit;\n", tail_ce020);
+ out("regs.ce020_tail_cycles = get_cycles() + regs.ce020_tail;\n");
} else {
- out("\tregs.ce020_tail = 0;\n");
+ out("regs.ce020_tail = 0;\n");
}
#endif
tail_ce020_done = true;
if (using_ce || using_ce020) {
#if 0
if (tail_ce020 == 0)
- out("\tregs.ce020memcycles -= 2 * cpucycleunit; /* T=0 */ \n");
+ out("regs.ce020memcycles -= 2 * cpucycleunit; /* T=0 */ \n");
else if (tail_ce020 == 1)
- out("\tregs.ce020memcycles -= 1 * cpucycleunit; /* T=1 */ \n");
+ out("regs.ce020memcycles -= 1 * cpucycleunit; /* T=1 */ \n");
else if (tail_ce020 == 2)
- out("\tregs.ce020memcycles -= 0 * cpucycleunit; /* T=2 */\n");
+ out("regs.ce020memcycles -= 0 * cpucycleunit; /* T=2 */\n");
#endif
out("%sreturn;\n", s);
return;
return;
if (!head && !tail && !cycles)
return;
- out("\t/* %s H:%d,T:%d,C:%d */\n", name, head, tail, cycles);
+ out("/* %s H:%d,T:%d,C:%d */\n", name, head, tail, cycles);
}
static void addcycles_ce020 (const char *name, int head, int tail, int cycles, int ophead)
{
if (!isce020())
return;
if (!head && !tail && !cycles && !ophead) {
- out("\t/* OP zero */\n");
+ out("/* OP zero */\n");
return;
}
count_cycles += cycles;
if (!ophead) {
addcycles_ce020 (name, head, tail, cycles);
} else if (ophead > 0) {
- out("\t/* %s H:%d-,T:%d,C:%d */\n", name, head, tail, cycles);
+ out("/* %s H:%d-,T:%d,C:%d */\n", name, head, tail, cycles);
} else {
- out("\t/* %s H:%d+,T:%d,C:%d */\n", name, head, tail, cycles);
+ out("/* %s H:%d+,T:%d,C:%d */\n", name, head, tail, cycles);
}
}
static void addcycles000_onlyce (int cycles)
{
if (using_ce) {
- out("\t%s(%d);\n", do_cycles, cycles);
+ out("%s(%d);\n", do_cycles, cycles);
}
}
static void addcycles000 (int cycles)
{
if (using_ce) {
- out("\t%s(%d);\n", do_cycles, cycles);
+ out("%s(%d);\n", do_cycles, cycles);
}
count_cycles += cycles;
}
{
if (abs(movem) != 3)
return;
- out("\tif (mmu040_movem) {\n");
- out("\t\tsrca = mmu040_movem_ea;\n");
- out("\t} else\n");
+ out("if (mmu040_movem) {\n");
+ out("srca = mmu040_movem_ea;\n");
+ out("} else\n");
start_brace ();
}
return;
if (bus_error_text[0]) {
- out("\tif(hardware_bus_error) {\n");
+ out("if(hardware_bus_error) {\n");
if (bus_error_code[0])
out("%s", bus_error_code);
out("%s", bus_error_text);
- write_return_cycles("\t\t", 0);
- out("\t}\n");
+ write_return_cycles("", 0);
+ out("}\n");
}
bus_error_code[0] = 0;
bus_error_specials = 0;
} else {
opcode = "opcode";
}
- sprintf(bus_error_text, "\t\texception2_fetch(%s, %d);\n", opcode, offset);
+ sprintf(bus_error_text, "exception2_fetch(%s, %d);\n", opcode, offset);
}
static void check_prefetch_bus_error(int offset, int secondprefetchmode)
int r = m68k_pc_offset;
m68k_pc_offset += 4;
- out("\t%s %s;\n", type, name);
+ out("%s %s;\n", type, name);
add_mmu040_movem (movem);
if (using_ce020) {
if (flags & GF_NOREFILL)
- out("\t%s = %s(%d);\n", name, prefetch_long, r);
+ out("%s = %s(%d);\n", name, prefetch_long, r);
else
- out("\t%s = %s(%d);\n", name, prefetch_long, r);
+ out("%s = %s(%d);\n", name, prefetch_long, r);
count_read += 2;
} else if (using_ce) {
/* we must do this because execution order of (something | something2) is not defined */
if (flags & GF_NOREFILL) {
- out("\t%s = %s(%d) << 16;\n", name, prefetch_word, r + 2);
+ out("%s = %s(%d) << 16;\n", name, prefetch_word, r + 2);
count_read++;
- out("\t%s |= regs.irc;\n", name);
+ out("%s |= regs.irc;\n", name);
} else {
- out("\t%s = %s(%d) << 16;\n", name, prefetch_word, r + 2);
+ out("%s = %s(%d) << 16;\n", name, prefetch_word, r + 2);
count_read++;
check_bus_error_ins(r + 2);
do_instruction_buserror();
strcpy(bus_error_code, bus_error_code2);
bus_error_code2[0] = 0;
- out("\t%s |= %s(%d);\n", name, prefetch_word, r + 4);
+ out("%s |= %s(%d);\n", name, prefetch_word, r + 4);
count_read++;
check_bus_error_ins(r + 4);
}
} else {
if (using_prefetch) {
if (flags & GF_NOREFILL) {
- out("\t%s = %s(%d) << 16;\n", name, prefetch_word, r + 2);
+ out("%s = %s(%d) << 16;\n", name, prefetch_word, r + 2);
count_read++;
insn_n_cycles += 4;
check_bus_error_ins(r + 2);
- out("\t%s |= regs.irc;\n", name);
+ out("%s |= regs.irc;\n", name);
} else {
- out("\t%s = %s(%d) << 16;\n", name, prefetch_word, r + 2);
+ out("%s = %s(%d) << 16;\n", name, prefetch_word, r + 2);
count_read++;
insn_n_cycles += 4;
check_bus_error_ins(r + 2);
do_instruction_buserror();
strcpy(bus_error_code, bus_error_code2);
bus_error_code2[0] = 0;
- out("\t%s |= %s(%d);\n", name, prefetch_word, r + 4);
+ out("%s |= %s(%d);\n", name, prefetch_word, r + 4);
count_read++;
check_bus_error_ins(r + 4);
}
} else {
insn_n_cycles += 8;
- out("\t%s = %s(%d);\n", name, prefetch_long, r);
+ out("%s = %s(%d);\n", name, prefetch_long, r);
}
}
}
static void makefromsr(void)
{
- out("\tMakeFromSR();\n");
+ out("MakeFromSR();\n");
if (using_ce || isce020())
- out("\tregs.ipl_pin = intlev();\n");
+ out("regs.ipl_pin = intlev();\n");
}
static void makefromsr_t0(void)
{
if (using_prefetch || using_ce) {
- out("\tMakeFromSR();\n");
+ out("MakeFromSR();\n");
} else {
- out("\tMakeFromSR_T0();\n");
+ out("MakeFromSR_T0();\n");
}
if (using_ce || isce020())
- out("\tregs.ipl_pin = intlev();\n");
+ out("regs.ipl_pin = intlev();\n");
}
static void check_ipl (void)
if (ipl_fetched)
return;
if (using_ce || isce020())
- out("\tipl_fetch();\n");
+ out("ipl_fetch();\n");
ipl_fetched = 1;
}
if (ipl_fetched != 1)
return;
if (using_ce)
- out("\tipl_fetch();\n");
+ out("ipl_fetch();\n");
}
static void irc2ir (bool dozero)
if (ir2irc)
return;
ir2irc = 1;
- out("\tregs.ir = regs.irc;\n");
+ out("regs.ir = regs.irc;\n");
if (dozero)
- out("\tregs.irc = 0;\n");
+ out("regs.irc = 0;\n");
check_ipl ();
}
static void irc2ir (void)
static void copy_opcode(void)
{
- out("\topcode = regs.ir;\n");
+ out("opcode = regs.ir;\n");
}
static void fill_prefetch_bcc(void)
if (using_bus_error) {
copy_opcode();
if (cpu_level == 0) {
- out("\tif(regs.t1) opcode |= 0x10000;\n");
+ out("if(regs.t1) opcode |= 0x10000;\n");
}
}
- out("\t%s(%d);\n", prefetch_word, m68k_pc_offset + 2);
+ out("%s(%d);\n", prefetch_word, m68k_pc_offset + 2);
count_read++;
insn_n_cycles += 4;
check_prefetch_bus_error(m68k_pc_offset + 2, 0);
static void fill_prefetch_1 (int o)
{
if (using_prefetch) {
- out("\t%s(%d);\n", prefetch_word, o);
+ out("%s(%d);\n", prefetch_word, o);
if (!loopmode || using_ce) {
count_read++;
insn_n_cycles += 4;
} else {
- addcycles000_nonce("\t", 4);
+ addcycles000_nonce("", 4);
}
check_prefetch_bus_error(o, 0);
did_prefetch = 1;
static void fill_prefetch_1_empty(int o)
{
if (using_prefetch) {
- out("\t%s(%d);\n", prefetch_word, o);
+ out("%s(%d);\n", prefetch_word, o);
count_read++;
insn_n_cycles += 4;
check_prefetch_bus_error(o ? -2 : -1, 0);
total_ce020 -= 4;
returntail (false);
if (cpu_level >= 3)
- out("\tfill_prefetch_030();\n");
+ out("fill_prefetch_030();\n");
else if (cpu_level == 2)
- out("\tfill_prefetch_020();\n");
+ out("fill_prefetch_020();\n");
}
}
copy_opcode();
if (cpu_level == 0) {
if (beopcode == 2)
- out("\tif(regs.t1) opcode |= 0x10000;\n");
+ out("if(regs.t1) opcode |= 0x10000;\n");
if (beopcode == 3)
- out("\tif(t1) opcode |= 0x10000;\n");
+ out("if(t1) opcode |= 0x10000;\n");
}
fill_prefetch_1(2);
} else {
total_ce020 -= 4;
returntail (false);
if (cpu_level >= 3)
- out("\tfill_prefetch_030_ntx();\n");
+ out("fill_prefetch_030_ntx();\n");
else if (cpu_level == 2)
- out("\tfill_prefetch_020_ntx();\n");
+ out("fill_prefetch_020_ntx();\n");
}
}
static void check_trace(void)
{
if (!using_prefetch && !using_ce)
- out("\tif(regs.t0) check_t0_trace();\n");
+ out("if(regs.t0) check_t0_trace();\n");
}
static void trace_t0_68040_only(void)
if (beopcode) {
copy_opcode();
if (beopcode > 1 && cpu_level == 0) {
- out("\tif(regs.t1) opcode |= 0x10000;\n");
+ out("if(regs.t1) opcode |= 0x10000;\n");
}
fill_prefetch_1(2);
} else {
total_ce020 -= 4;
returntail (false);
if (cpu_level >= 3)
- out("\tfill_prefetch_030();\n");
+ out("fill_prefetch_030();\n");
else if (cpu_level == 2)
- out("\tfill_prefetch_020();\n");
+ out("fill_prefetch_020();\n");
} else if (!using_prefetch_020 && cpu_level >= 2) {
check_trace();
}
if (!using_prefetch)
return;
- out("\t%s(%d);\n", prefetch_word, 0);
+ out("%s(%d);\n", prefetch_word, 0);
count_read++;
insn_n_cycles += 2;
check_prefetch_bus_error(-1, -1);
copy_opcode();
if (cpu_level == 0) {
if (g_instr->mnemo == i_RTE) {
- out("\tif(oldt1) opcode |= 0x10000;\n");
+ out("if(oldt1) opcode |= 0x10000;\n");
} else {
- out("\tif(regs.t1) opcode |= 0x10000;\n");
+ out("if(regs.t1) opcode |= 0x10000;\n");
}
}
}
- out("\t%s(%d);\n", prefetch_word, 2);
+ out("%s(%d);\n", prefetch_word, 2);
count_read++;
insn_n_cycles += 2;
check_prefetch_bus_error(-2, -1);
{
if (!using_prefetch_020) {
if (!using_prefetch && !using_ce)
- out("\tif(regs.t0) check_t0_trace();\n");
+ out("if(regs.t0) check_t0_trace();\n");
return;
}
fill_prefetch_full(0);
{
if (!using_prefetch)
return;
- out("\t%s(0);\n", prefetch_word);
+ out("%s(0);\n", prefetch_word);
count_read++;
insn_n_cycles += 4;
check_prefetch_bus_error(0, 0);
loopmode_set = 0;
loopmodeextra = 0;
if (loopmode) {
- out("\tint loop_mode = regs.loop_mode;\n");
+ out("int loop_mode = regs.loop_mode;\n");
}
}
static void loopmode_stop(void)
{
if (loopmode) {
- out("\tregs.loop_mode = loop_mode;\n");
+ out("regs.loop_mode = loop_mode;\n");
}
}
static void loopmode_begin(void)
{
if (loopmode) {
- out("\tif(!loop_mode) {\n");
+ out("if(!loop_mode) {\n");
}
}
static void loopmode_access(void)
{
if (loopmode && loopmode_set) {
loopmode_set = 0;
- out("\tif(loop_mode & 0xfffe) {\n");
+ out("if(loop_mode & 0xfffe) {\n");
if (using_ce) {
- out("\t\t%s(loop_mode & 0xfffe);\n", do_cycles);
+ out("%s(loop_mode & 0xfffe);\n", do_cycles);
} else {
- addcycles000_nonces("\t\t", "loop_mode & 0xfffe");
+ addcycles000_nonces("", "loop_mode & 0xfffe");
}
// CLR.L adds 2 extra cycles when loop exits
if (g_instr->mnemo == i_CLR && g_instr->size == sz_long) {
- out("\t\tloop_mode &= 0xffff0000;\n");
- out("\t\tloop_mode |= 1;\n");
+ out("loop_mode &= 0xffff0000;\n");
+ out("loop_mode |= 1;\n");
} else {
- out("\t\tloop_mode = 1;\n");
+ out("loop_mode = 1;\n");
}
- out("\t}\n");
+ out("}\n");
}
}
}
if (cycs > 0 || ecycs > 0) {
- out("\t} else {\n");
- out("\t\tloop_mode = 0;\n");
+ out("} else {\n");
+ out("loop_mode = 0;\n");
if (cycs > 0) {
- out("\t\tloop_mode |= %d;\n", cycs);
+ out("loop_mode |= %d;\n", cycs);
}
if (ecycs > 0) {
- out("\t\tloop_mode |= %d << 16;\n", ecycs);
+ out("loop_mode |= %d << 16;\n", ecycs);
}
}
- out("\t}\n");
+ out("}\n");
loopmode_set = 1;
}
}
va_end(parms);
}
if (cpu_level == 0) {
- out("\topcode |= 0x20000;\n");
+ out("opcode |= 0x20000;\n");
}
}
fill_prefetch_1(m68k_pc_offset + 2);
if (using_bus_error) {
copy_opcode();
if (cpu_level == 0) {
- strcat(bus_error_code, "\t\tif (regs.t1) opcode |= 0x10000;\n");
+ strcat(bus_error_code, "if (regs.t1) opcode |= 0x10000;\n");
}
}
fill_prefetch_1(m68k_pc_offset + 2);
irc2ir();
if (using_bus_error) {
if (cond)
- out("\t%s\n\t", cond);
+ out("%s\n", cond);
copy_opcode();
bus_error_code[0] = 0;
if (format) {
loopmode_begin();
irc2ir();
if (cpu_level == 0) {
- out("\topcode |= 0x20000;\n");
+ out("opcode |= 0x20000;\n");
}
bus_error_code[0] = 0;
if (format) {
irc2ir();
if (using_bus_error) {
if (cpu_level == 0) {
- out("\topcode |= 0x20000;\n");
+ out("opcode |= 0x20000;\n");
}
}
fill_prefetch_1(m68k_pc_offset + 2);
}
// if (using_prefetch_020) {
- // out("\t%s(%d);\n", prefetch_word, m68k_pc_offset);
+ // out("%s(%d);\n", prefetch_word, m68k_pc_offset);
// did_prefetch = 1;
// }
}
va_end (parms);
if (using_mmu)
- out("\tm68k_setpci(%s);\n", buffer);
+ out("m68k_setpci(%s);\n", buffer);
else if (using_prefetch || using_prefetch_020 || using_test)
- out("\tm68k_setpci_j(%s);\n", buffer);
+ out("m68k_setpci_j(%s);\n", buffer);
else
- out("\tm68k_setpc_j(%s);\n", buffer);
+ out("m68k_setpc_j(%s);\n", buffer);
}
static void incpc (const char *format, ...)
va_end (parms);
if (using_mmu || using_prefetch || using_prefetch_020 || using_test)
- out("\tm68k_incpci(%s);\n", buffer);
+ out("m68k_incpci(%s);\n", buffer);
else
- out("\tm68k_incpc(%s);\n", buffer);
+ out("m68k_incpc(%s);\n", buffer);
}
static void dummy_prefetch(const char *newpc, const char *oldpc)
{
if (using_prefetch && cpu_level == 1) {
if (!newpc && !oldpc) {
- out("\t\t%s((m68k_getpci() & 1) ? -1 : 0);\n", prefetch_word);
+ out("%s((m68k_getpci() & 1) ? -1 : 0);\n", prefetch_word);
} else {
if (newpc) {
if (!oldpc)
- out("\t\tuaecptr d_oldpc = m68k_getpci();\n");
+ out("uaecptr d_oldpc = m68k_getpci();\n");
setpc("%s & ~1", newpc);
}
- out("\t\t%s(0);\n", prefetch_word);
+ out("%s(0);\n", prefetch_word);
if (oldpc) {
setpc(oldpc);
} else if (newpc) {
{
int i;
for (i = 0; i <= n; i++)
- out("\t");
+ out("");
out("COPY_CARRY();\n");
}
case flag_av:
case flag_sv:
start_brace();
- out("\t" BOOL_TYPE " flgs = %s < 0;\n", sstr);
- out("\t" BOOL_TYPE " flgo = %s < 0;\n", dstr);
- out("\t" BOOL_TYPE " flgn = %s < 0;\n", vstr);
+ out("" BOOL_TYPE " flgs = %s < 0;\n", sstr);
+ out("" BOOL_TYPE " flgo = %s < 0;\n", dstr);
+ out("" BOOL_TYPE " flgn = %s < 0;\n", vstr);
break;
}
switch (type) {
case flag_logical:
- out("\tCLEAR_CZNV();\n");
- out("\tSET_ZFLG(%s == 0);\n", vstr);
- out("\tSET_NFLG(%s < 0);\n", vstr);
+ out("CLEAR_CZNV();\n");
+ out("SET_ZFLG(%s == 0);\n", vstr);
+ out("SET_NFLG(%s < 0);\n", vstr);
break;
case flag_logical_noclobber:
- out("\tSET_ZFLG(%s == 0);\n", vstr);
- out("\tSET_NFLG(%s < 0);\n", vstr);
+ out("SET_ZFLG(%s == 0);\n", vstr);
+ out("SET_NFLG(%s < 0);\n", vstr);
break;
case flag_av:
- out("\tSET_VFLG((flgs ^ flgn) & (flgo ^ flgn));\n");
+ out("SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));\n");
break;
case flag_sv:
- out("\tSET_VFLG((flgs ^ flgo) & (flgn ^ flgo));\n");
+ out("SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));\n");
break;
case flag_z:
- out("\tSET_ZFLG(GET_ZFLG () & (%s == 0));\n", vstr);
+ out("SET_ZFLG(GET_ZFLG () & (%s == 0));\n", vstr);
break;
case flag_zn:
- out("\tSET_ZFLG(GET_ZFLG () & (%s == 0));\n", vstr);
- out("\tSET_NFLG(%s < 0);\n", vstr);
+ out("SET_ZFLG(GET_ZFLG () & (%s == 0));\n", vstr);
+ out("SET_NFLG(%s < 0);\n", vstr);
break;
case flag_add:
- out("\tSET_ZFLG(%s == 0);\n", vstr);
- out("\tSET_VFLG((flgs ^ flgn) & (flgo ^ flgn));\n");
- out("\tSET_CFLG(%s < %s);\n", undstr, usstr);
+ out("SET_ZFLG(%s == 0);\n", vstr);
+ out("SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));\n");
+ out("SET_CFLG(%s < %s);\n", undstr, usstr);
duplicate_carry(0);
- out("\tSET_NFLG(flgn != 0);\n");
+ out("SET_NFLG(flgn != 0);\n");
break;
case flag_sub:
- out("\tSET_ZFLG(%s == 0);\n", vstr);
- out("\tSET_VFLG((flgs ^ flgo) & (flgn ^ flgo));\n");
- out("\tSET_CFLG(%s > %s);\n", usstr, udstr);
+ out("SET_ZFLG(%s == 0);\n", vstr);
+ out("SET_VFLG((flgs ^ flgo) & (flgn ^ flgo));\n");
+ out("SET_CFLG(%s > %s);\n", usstr, udstr);
duplicate_carry(0);
- out("\tSET_NFLG(flgn != 0);\n");
+ out("SET_NFLG(flgn != 0);\n");
break;
case flag_addx:
- out("\tSET_VFLG((flgs ^ flgn) & (flgo ^ flgn));\n"); /* minterm SON: 0x42 */
- out("\tSET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));\n"); /* minterm SON: 0xD4 */
+ out("SET_VFLG((flgs ^ flgn) & (flgo ^ flgn));\n"); /* minterm SON: 0x42 */
+ out("SET_CFLG(flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));\n"); /* minterm SON: 0xD4 */
duplicate_carry(0);
break;
case flag_subx:
- out("\tSET_VFLG((flgs ^ flgo) & (flgo ^ flgn));\n"); /* minterm SON: 0x24 */
- out("\tSET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));\n"); /* minterm SON: 0xB2 */
+ out("SET_VFLG((flgs ^ flgo) & (flgo ^ flgn));\n"); /* minterm SON: 0x24 */
+ out("SET_CFLG(flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));\n"); /* minterm SON: 0xB2 */
duplicate_carry(0);
break;
case flag_cmp:
- out("\tSET_ZFLG(%s == 0);\n", vstr);
- out("\tSET_VFLG((flgs != flgo) && (flgn != flgo));\n");
- out("\tSET_CFLG(%s > %s);\n", usstr, udstr);
- out("\tSET_NFLG(flgn != 0);\n");
+ out("SET_ZFLG(%s == 0);\n", vstr);
+ out("SET_VFLG((flgs != flgo) && (flgn != flgo));\n");
+ out("SET_CFLG(%s > %s);\n", usstr, udstr);
+ out("SET_NFLG(flgn != 0);\n");
break;
}
}
case flag_add:
case flag_sub:
start_brace();
- out("\tuae_u32 %s;\n", value);
+ out("uae_u32 %s;\n", value);
break;
default:
/* At least some of those casts are fairly important! */
switch (type) {
case flag_logical_noclobber:
- out("\t{uae_u32 oldcznv = GET_CZNV & ~(FLAGVAL_Z | FLAGVAL_N);\n");
+ out("{uae_u32 oldcznv = GET_CZNV & ~(FLAGVAL_Z | FLAGVAL_N);\n");
if (strcmp(value, "0") == 0) {
- out("\tSET_CZNV(olcznv | FLAGVAL_Z);\n");
+ out("SET_CZNV(olcznv | FLAGVAL_Z);\n");
} else {
switch (size) {
- case sz_byte: out("\toptflag_testb(regs, (uae_s8)(%s));\n", value); break;
- case sz_word: out("\toptflag_testw(regs, (uae_s16)(%s));\n", value); break;
- case sz_long: out("\toptflag_testl(regs, (uae_s32)(%s));\n", value); break;
+ case sz_byte: out("optflag_testb(regs, (uae_s8)(%s));\n", value); break;
+ case sz_word: out("optflag_testw(regs, (uae_s16)(%s));\n", value); break;
+ case sz_long: out("optflag_testl(regs, (uae_s32)(%s));\n", value); break;
default: term();
}
- out("\tIOR_CZNV(oldcznv);\n");
+ out("IOR_CZNV(oldcznv);\n");
}
- out("\t}\n");
+ out("}\n");
return;
case flag_logical:
if (strcmp(value, "0") == 0) {
- out("\tSET_CZNV(FLAGVAL_Z);\n");
+ out("SET_CZNV(FLAGVAL_Z);\n");
} else {
switch (size) {
- case sz_byte: out("\toptflag_testb(regs, (uae_s8)(%s));\n", value); break;
- case sz_word: out("\toptflag_testw(regs, (uae_s16)(%s));\n", value); break;
- case sz_long: out("\toptflag_testl(regs, (uae_s32)(%s));\n", value); break;
+ case sz_byte: out("optflag_testb(regs, (uae_s8)(%s));\n", value); break;
+ case sz_word: out("optflag_testw(regs, (uae_s16)(%s));\n", value); break;
+ case sz_long: out("optflag_testl(regs, (uae_s32)(%s));\n", value); break;
default: term();
}
}
case flag_add:
switch (size) {
- case sz_byte: out("\toptflag_addb(regs, %s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
- case sz_word: out("\toptflag_addw(regs, %s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
- case sz_long: out("\toptflag_addl(regs, %s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
+ case sz_byte: out("optflag_addb(regs, %s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
+ case sz_word: out("optflag_addw(regs, %s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
+ case sz_long: out("optflag_addl(regs, %s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
default: term();
}
return;
case flag_sub:
switch (size) {
- case sz_byte: out("\toptflag_subb(regs, %s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
- case sz_word: out("\toptflag_subw(regs, %s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
- case sz_long: out("\toptflag_subl(regs, %s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
+ case sz_byte: out("optflag_subb(regs, %s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
+ case sz_word: out("optflag_subw(regs, %s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
+ case sz_long: out("optflag_subl(regs, %s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
default: term();
}
return;
case flag_cmp:
switch (size) {
- case sz_byte: out("\toptflag_cmpb(regs, (uae_s8)(%s), (uae_s8)(%s));\n", src, dst); break;
- case sz_word: out("\toptflag_cmpw(regs, (uae_s16)(%s), (uae_s16)(%s));\n", src, dst); break;
- case sz_long: out("\toptflag_cmpl(regs, (uae_s32)(%s), (uae_s32)(%s));\n", src, dst); break;
+ case sz_byte: out("optflag_cmpb(regs, (uae_s8)(%s), (uae_s8)(%s));\n", src, dst); break;
+ case sz_word: out("optflag_cmpw(regs, (uae_s16)(%s), (uae_s16)(%s));\n", src, dst); break;
+ case sz_long: out("optflag_cmpl(regs, (uae_s32)(%s), (uae_s32)(%s));\n", src, dst); break;
default: term();
}
return;
if (dmode == Apdi) {
if (cpu_level == 0) {
- out("\t\tif (regs.t1) opcode |= 0x10000;\n"); // I/N set
+ out("if (regs.t1) opcode |= 0x10000;\n"); // I/N set
}
} else if (dmode == Aipi) {
// move.b x,(an)+: an is not increased
- out("\t\tm68k_areg(regs, dstreg) -= areg_byteinc[dstreg];\n");
+ out("m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];\n");
}
} else if (size == sz_word) {
if (dmode == Apdi) {
if (cpu_level == 0) {
- out("\t\tif (regs.t1) opcode |= 0x10000;\n"); // I/N set
+ out("if (regs.t1) opcode |= 0x10000;\n"); // I/N set
}
} else if (dmode == Aipi) {
// move.w x,(an)+: an is not increased
- out("\t\tm68k_areg(regs, dstreg) -= 2;\n");
+ out("m68k_areg(regs, dstreg) -= 2;\n");
}
} else if (size == sz_long && ((offset == 0 && dmode != Apdi) || (offset == 2 && dmode == Apdi))) {
if (set_low_word == 1) {
// Low word: Z and N
- out("\t\tccr_68000_long_move_ae_LZN(src);\n");
+ out("ccr_68000_long_move_ae_LZN(src);\n");
} else if (set_high_word == 3) {
// High word: N only, clear Z if non-zero
- out("\t\tSET_NFLG(src < 0);\n");
- out("\t\tif((src & 0xffff0000)) SET_ZFLG(0);\n");
+ out("SET_NFLG(src < 0);\n");
+ out("if((src & 0xffff0000)) SET_ZFLG(0);\n");
} else if (set_high_word) {
// High word: N set/reset and Z clear.
- out("\t\tccr_68000_long_move_ae_HNZ(src);\n");
+ out("ccr_68000_long_move_ae_HNZ(src);\n");
} else if (set_ccr) {
// Set normally.
- out("\t\tccr_68000_long_move_ae_normal(src);\n");
+ out("ccr_68000_long_move_ae_normal(src);\n");
}
if (dmode == Aipi) {
- out("\t\tm68k_areg(regs, dstreg) -= 4;\n");
+ out("m68k_areg(regs, dstreg) -= 4;\n");
} else if (dmode == Apdi) {
- out("\t\tm68k_areg(regs, dstreg) += 4;\n");
+ out("m68k_areg(regs, dstreg) += 4;\n");
}
} else if (size == sz_long) {
if (set_low_word == 1) {
// Low word: Z and N
- out("\t\tccr_68000_long_move_ae_LZN(src);\n");
+ out("ccr_68000_long_move_ae_LZN(src);\n");
} else if (set_ccr) {
// Set normally.
- out("\t\tccr_68000_long_move_ae_normal(src);\n");
+ out("ccr_68000_long_move_ae_normal(src);\n");
}
if (dmode == Aipi) {
- out("\t\tm68k_areg(regs, dstreg) -= 4;\n");
+ out("m68k_areg(regs, dstreg) -= 4;\n");
} else if (dmode == Apdi) {
- out("\t\tm68k_areg(regs, dstreg) += 4;\n");
+ out("m68k_areg(regs, dstreg) += 4;\n");
}
}
case -1:
if (g_instr->mnemo == i_CMPM && bus_error_reg_add > 0) {
// CMPM.B (an)+,(an)+: first increased normally, second not increased
- out("\t\tm68k_areg(regs, %s) += areg_byteinc[%s] + %d;\n", bus_error_reg, bus_error_reg, offset);
+ out("m68k_areg(regs, %s) += areg_byteinc[%s] + %d;\n", bus_error_reg, bus_error_reg, offset);
}
break;
case 2:
;
} else if (g_instr->mnemo == i_RTE) {
// stack is decreased first
- out("\t\tm68k_areg(regs, %s) += %d;\n", bus_error_reg, cpu_level == 0 ? 14 : 58);
+ out("m68k_areg(regs, %s) += %d;\n", bus_error_reg, cpu_level == 0 ? 14 : 58);
} else {
- out("\t\tm68k_areg(regs, %s) += 2 + %d;\n", bus_error_reg, offset);
+ out("m68k_areg(regs, %s) += 2 + %d;\n", bus_error_reg, offset);
}
break;
case 3:
case -3:
if (g_instr->mnemo == i_CMPM && bus_error_reg_add > 0) {
// CMPM.L (an)+,(an)+: first increased normally, second not increased
- out("\t\tm68k_areg(regs, %s) += 2 + %d;\n", bus_error_reg, offset);
+ out("m68k_areg(regs, %s) += 2 + %d;\n", bus_error_reg, offset);
}
break;
case 4:
offset += 2;
} else if (g_instr->mnemo == i_RTR) {
if (offset) {
- out("\t\tm68k_areg(regs, %s) += 4;\n", bus_error_reg);
- out("\t\tregs.sr &= 0xFF00; sr &= 0xFF;\n");
- out("\t\tregs.sr |= sr;\n");
- out("\t\tMakeFromSR();\n");
+ out("m68k_areg(regs, %s) += 4;\n", bus_error_reg);
+ out("regs.sr &= 0xFF00; sr &= 0xFF;\n");
+ out("regs.sr |= sr;\n");
+ out("MakeFromSR();\n");
} else {
- out("\t\tm68k_areg(regs, %s) -= 2;\n", bus_error_reg);
+ out("m68k_areg(regs, %s) -= 2;\n", bus_error_reg);
}
} else if (g_instr->mnemo == i_RTE) {
// stack is decreased first
- out("\t\tm68k_areg(regs, %s) += %d - 2;\n", bus_error_reg, cpu_level == 0 ? 14 : 58);
+ out("m68k_areg(regs, %s) += %d - 2;\n", bus_error_reg, cpu_level == 0 ? 14 : 58);
if (offset) {
- out("\t\tregs.sr = sr;\n");
- out("\t\tMakeFromSR();\n");
+ out("regs.sr = sr;\n");
+ out("MakeFromSR();\n");
}
} else if (cpu_level == 1) {
// -(an).l where first word causes bus error: An is not modified
// -(an).l where second word causes bus error: An is modified
if (g_instr->size != sz_long || (g_instr->size == sz_long && offset)) {
- out("\t\tm68k_areg(regs, %s) = %sa;\n", bus_error_reg, name);
+ out("m68k_areg(regs, %s) = %sa;\n", bus_error_reg, name);
}
} else {
- out("\t\tm68k_areg(regs, %s) = %sa;\n", bus_error_reg, name);
+ out("m68k_areg(regs, %s) = %sa;\n", bus_error_reg, name);
}
break;
}
if ((!using_prefetch && !using_ce) || cpu_level >= 2) {
fc &= 7;
- out("\tif(hardware_bus_error) {\n");
+ out("if(hardware_bus_error) {\n");
if (write) {
- out("\t\texception2_write(opcode, %sa + %d, %d, %s, %d);\n",
+ out("exception2_write(opcode, %sa + %d, %d, %s, %d);\n",
name, offset, size, writevar,
(!write && (g_instr->smode == PC16 || g_instr->smode == PC8r)) ||
(write && (g_instr->dmode == PC16 || g_instr->dmode == PC8r)) ? 2 : fc);
} else {
- out("\t\texception2_read(opcode, %sa + %d, %d, %d);\n",
+ out("exception2_read(opcode, %sa + %d, %d, %d);\n",
name, offset, size,
(!write && (g_instr->smode == PC16 || g_instr->smode == PC8r)) ||
(write && (g_instr->dmode == PC16 || g_instr->dmode == PC8r)) ? 2 : fc);
}
- write_return_cycles("\t\t", 0);
- out("\t}\n");
+ write_return_cycles("", 0);
+ out("}\n");
return;
}
uae_u32 extra = fc & 0xffff0000;
fc &= 0xffff;
- out("\tif(hardware_bus_error) {\n");
+ out("if(hardware_bus_error) {\n");
int setapdiback = 0;
if (fc == 2) {
- out("\t\texception2_fetch(opcode, %d);\n", offset);
+ out("exception2_fetch(opcode, %d);\n", offset);
} else {
if ((mnemo == i_ADDX || mnemo == i_SUBX) && g_instr->size == sz_long && g_instr->dmode == Apdi && write && offset) {
out(
- "\t\tint bflgs = ((uae_s16)(src)) < 0;\n"
- "\t\tint bflgo = ((uae_s16)(dst)) < 0;\n"
- "\t\tint bflgn = ((uae_s16)(newv)) < 0;\n");
+ "int bflgs = ((uae_s16)(src)) < 0;\n"
+ "int bflgo = ((uae_s16)(dst)) < 0;\n"
+ "int bflgn = ((uae_s16)(newv)) < 0;\n");
if (mnemo == i_ADDX) {
out(
- "\t\tSET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));\n"
- "\t\tSET_CFLG(bflgs ^ ((bflgs ^ bflgo) & (bflgo ^ bflgn)));\n");
+ "SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));\n"
+ "SET_CFLG(bflgs ^ ((bflgs ^ bflgo) & (bflgo ^ bflgn)));\n");
} else {
out(
- "\t\tSET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));\n"
- "\t\tSET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));\n");
+ "SET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));\n"
+ "SET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));\n");
}
out(
- "\t\tCOPY_CARRY();\n"
- "\t\tSET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));\n"
- "\t\tSET_NFLG(((uae_s16)(newv)) < 0);\n");
+ "COPY_CARRY();\n"
+ "SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));\n"
+ "SET_NFLG(((uae_s16)(newv)) < 0);\n");
}
if (mnemo == i_LINK) {
// a7 -> a0 copy done before A7 address error check
if (write) {
- out("\t\tm68k_areg(regs, 7) += 4;\n");
+ out("m68k_areg(regs, 7) += 4;\n");
}
- out("\t\tm68k_areg(regs, srcreg) = olda;\n");
+ out("m68k_areg(regs, srcreg) = olda;\n");
}
if (mnemo == i_PEA && write && offset && g_instr->smode != absw && g_instr->smode != absl) {
if (cpu_level == 0) {
- out("\t\tif (regs.t1) opcode |= 0x10000;\n"); // I/N set
+ out("if (regs.t1) opcode |= 0x10000;\n"); // I/N set
}
}
if (cpu_level == 1) {
// 68010 bus/address error HB bit
if (extra) {
- out("\t\topcode |= 0x%x;\n", extra);
+ out("opcode |= 0x%x;\n", extra);
}
// upper byte of SSW is zero -flag.
if (g_instr->mnemo == i_MVSR2 && !write) {
- out("\t\topcode |= 0x20000;\n");
+ out("opcode |= 0x20000;\n");
}
// read bus error, -(an).w/.l: pre-decrement is done first.
if (!write && g_instr->smode == Apdi && g_instr->size == sz_long) {
- //out("\t\tm68k_areg(regs, %s) = %sa;\n", bus_error_reg, name);
+ //out("m68k_areg(regs, %s) = %sa;\n", bus_error_reg, name);
}
}
mnemo != i_LINK &&
mnemo != i_MVMEL && mnemo != i_MVMLE &&
mnemo != i_MVPRM && mnemo != i_MVPMR) {
- out("\t\tif (regs.t1) opcode |= 0x10000;\n"); // I/N set
+ out("if (regs.t1) opcode |= 0x10000;\n"); // I/N set
}
//if (cpu_level == 0 && write) {
- // out("\t\topcode = regs.irc;\n");
+ // out("opcode = regs.irc;\n");
//}
if (write) {
- out("\t\texception2_write(opcode, %sa + %d, %d, %s, %d);\n",
+ out("exception2_write(opcode, %sa + %d, %d, %s, %d);\n",
name, offset, size, writevar,
(!write && (g_instr->smode == PC16 || g_instr->smode == PC8r)) ||
(write && (g_instr->dmode == PC16 || g_instr->dmode == PC8r)) ? 2 : fc);
} else {
- out("\t\texception2_read(opcode, %sa + %d, %d, %d);\n",
+ out("exception2_read(opcode, %sa + %d, %d, %d);\n",
name, offset, size,
(!write && (g_instr->smode == PC16 || g_instr->smode == PC8r)) ||
(write && (g_instr->dmode == PC16 || g_instr->dmode == PC8r)) ? 2 : fc);
}
}
- write_return_cycles("\t\t", 0);
- out("\t}\n");
+ write_return_cycles("", 0);
+ out("}\n");
}
static void gen_set_fault_pc (bool multi, bool not68030)
int m68k_pc_total_old = m68k_pc_total;
if (using_mmu == 68040) {
sync_m68k_pc();
- out("\tregs.instruction_pc = %s;\n", getpc);
- out("\tmmu_restart = false;\n");
+ out("regs.instruction_pc = %s;\n", getpc);
+ out("mmu_restart = false;\n");
m68k_pc_offset = 0;
clearmmufixup(0, 0);
} else if (using_mmu == 68030) {
if (not68030)
return;
sync_m68k_pc();
- out("\tregs.instruction_pc = %s;\n", getpc);
- out("\tmmu030_state[1] |= MMU030_STATEFLAG1_LASTWRITE;\n");
+ out("regs.instruction_pc = %s;\n", getpc);
+ out("mmu030_state[1] |= MMU030_STATEFLAG1_LASTWRITE;\n");
m68k_pc_offset = 0;
}
if (multi)
return;
if (h < 0)
return;
- //out("\tdo_sync_tail(%d);\n", h);
- //out("\tdo_head_cycles_ce020(%d);\n", h);
+ //out("do_sync_tail(%d);\n", h);
+ //out("do_head_cycles_ce020(%d);\n", h);
head_ce020_cycs_done = true;
tail_ce020 = -1;
}
//c = 0;
#if 0
if (tail_ce020 == 1)
- out("\tregs.ce020memcycles -= 1 * cpucycleunit; /* T=1 */ \n");
+ out("regs.ce020memcycles -= 1 * cpucycleunit; /* T=1 */ \n");
else if (tail_ce020 == 2)
- out("\tregs.ce020memcycles -= 2 * cpucycleunit; /* T=2 */\n");
+ out("regs.ce020memcycles -= 2 * cpucycleunit; /* T=2 */\n");
#endif
if (1 && !subhead && (h > 0 || t > 0 || c > 0) && got_ea_ce020 && !(flags & GF_LRMW)) {
if (!did_prefetch) {
#if 0
if (1) {
if (h > 0) {
- out("\tlimit_cycles_ce020(%d);\n", h);
+ out("limit_cycles_ce020(%d);\n", h);
} else {
- out("\tlimit_all_cycles_ce020();\n");
+ out("limit_all_cycles_ce020();\n");
}
}
#endif
if (tail_ce020 >= 0 && h >= 0 && head_in_ea_ce020 == 0) {
int largest = tail_ce020 > h ? tail_ce020: h;
if (tail_ce020 != h) {
- //out("\tdo_cycles_ce020(%d - %d);\n", tail_ce020 > h ? tail_ce020 : h, tail_ce020 > h ? h : tail_ce020);
- //out("\tdo_cycles_ce020(%d - %d);\n", tail_ce020 > h ? tail_ce020 : h, tail_ce020 > h ? h : tail_ce020);
+ //out("do_cycles_ce020(%d - %d);\n", tail_ce020 > h ? tail_ce020 : h, tail_ce020 > h ? h : tail_ce020);
+ //out("do_cycles_ce020(%d - %d);\n", tail_ce020 > h ? tail_ce020 : h, tail_ce020 > h ? h : tail_ce020);
if (h) {
- out("\tregs.ce020memcycles -= %d * cpucycleunit;\n", h);
- out("\tif (regs.ce020memcycles < 0) {\n");
- //out("\t\tx_do_cycles(-regs.ce020memcycles);\n");
- out("\t\tregs.ce020memcycles = 0;\n");
- out("\t}\n");
+ out("regs.ce020memcycles -= %d * cpucycleunit;\n", h);
+ out("if (regs.ce020memcycles < 0) {\n");
+ //out("x_do_cycles(-regs.ce020memcycles);\n");
+ out("regs.ce020memcycles = 0;\n");
+ out("}\n");
} else {
- out("\tregs.ce020memcycles = 0;\n");
+ out("regs.ce020memcycles = 0;\n");
}
- //out("\tregs.ce020memcycles = 0;\n");
+ //out("regs.ce020memcycles = 0;\n");
#if 0
if (tail_ce020)
- out("\tregs.ce020_tail = get_cycles() - regs.ce020_tail;\n");
+ out("regs.ce020_tail = get_cycles() - regs.ce020_tail;\n");
else
- out("\tregs.ce020_tail = 0;\n");
- out("\tif (regs.ce020_tail < %d * cpucycleunit)\n", largest);
- out("\t\tx_do_cycles(%d * cpucycleunit - regs.ce020_tail);\n", largest);
+ out("regs.ce020_tail = 0;\n");
+ out("if (regs.ce020_tail < %d * cpucycleunit)\n", largest);
+ out("x_do_cycles(%d * cpucycleunit - regs.ce020_tail);\n", largest);
#endif
} else if (h) {
- out("\t/* ea tail == op head (%d) */\n", h);
+ out("/* ea tail == op head (%d) */\n", h);
- out("\tregs.ce020memcycles -= %d * cpucycleunit;\n", h);
- out("\tif (regs.ce020memcycles < 0) {\n");
- //out("\t\tx_do_cycles(-regs.ce020memcycles);\n");
- out("\t\tregs.ce020memcycles = 0;\n");
- out("\t}\n");
+ out("regs.ce020memcycles -= %d * cpucycleunit;\n", h);
+ out("if (regs.ce020memcycles < 0) {\n");
+ //out("x_do_cycles(-regs.ce020memcycles);\n");
+ out("regs.ce020memcycles = 0;\n");
+ out("}\n");
}
}
#endif
// c = internal cycles needed after head cycles and before tail cycles. Not total cycles.
addcycles_ce020 ("op", h, t, c - h - t, -subhead);
- //out("\tregs.irc = get_word_ce020_prefetch(%d);\n", m68k_pc_offset);
+ //out("regs.irc = get_word_ce020_prefetch(%d);\n", m68k_pc_offset);
#if 0
if (c - h - t > 0) {
- out("\t%s(%d);\n", do_cycles, c - h - t);
+ out("%s(%d);\n", do_cycles, c - h - t);
count_cycles_ce020 += c;
count_cycles += c;
}
#endif
- //out("\tregs.ce020_tail = 0;\n");
+ //out("regs.ce020_tail = 0;\n");
total_ce020 = c;
tail_ce020 = t;
// if (total_ce020 >= 2)
-// out("\tint op_cycles = get_cycles();\n");
+// out("int op_cycles = get_cycles();\n");
}
static void addop_ce020 (struct instr *curi, int subhead, int flags)
c = 0; // HACK
if (!oph) {
- out("\t/* ea H:%d,T:%d,C:%d %s */\n", h, t, c, ea);
+ out("/* ea H:%d,T:%d,C:%d %s */\n", h, t, c, ea);
} else {
if (oph && t)
term ("Both op head and tail can't be non-zero");
if (oph > 0) {
- out("\t/* ea H:%d+%d=%d,T:%d,C:%d %s */\n", h, oph, h + oph, t, c, ea);
+ out("/* ea H:%d+%d=%d,T:%d,C:%d %s */\n", h, oph, h + oph, t, c, ea);
h += oph;
} else {
- out("\t/* ea H:%d-%d=%d,T:%d,C:%d %s */\n", h, -oph, h + oph, t, c, ea);
+ out("/* ea H:%d-%d=%d,T:%d,C:%d %s */\n", h, -oph, h + oph, t, c, ea);
h += oph;
}
}
#if 0
if (h) {
- out("\tlimit_cycles_ce020(%d);\n", h);
+ out("limit_cycles_ce020(%d);\n", h);
} else {
- out("\tlimit_all_cycles_ce020();\n");
+ out("limit_all_cycles_ce020();\n");
}
#endif
if (1 && c > 0) {
- out("\t%s(%d);\n", do_cycles, c);
+ out("%s(%d);\n", do_cycles, c);
count_cycles += c;
}
tail_ce020 = t;
head_in_ea_ce020 = oph;
got_ea_ce020 = true;
// if (t > 0)
-// out("\tregs.ce020_tail = get_cycles() + %d * cpucycleunit;\n", t);
+// out("regs.ce020_tail = get_cycles() + %d * cpucycleunit;\n", t);
}
static void addcycles_ea_ce020 (const char *ea, int h, int t, int c)
{
}
if (dmode == Apdi) {
// partial prefetch already done
- out("\t\tregs.ir = regs.irc;\n");
+ out("regs.ir = regs.irc;\n");
// if trace, I/N is also set
- out("\t\tif(regs.t1) opcode |= 0x10000;\n");
+ out("if(regs.t1) opcode |= 0x10000;\n");
}
if (set_ccr) {
- out("\t\tccr_68000_word_move_ae_normal((uae_s16)(src));\n");
+ out("ccr_68000_word_move_ae_normal((uae_s16)(src));\n");
}
} else {
// Long MOVE is much more complex..
if (set_low_word == 1) {
// Low word: Z and N
- out("\t\tccr_68000_long_move_ae_LZN(src);\n");
+ out("ccr_68000_long_move_ae_LZN(src);\n");
} else if (set_low_word == 2) {
// Low word: N only
- out("\t\tccr_68000_long_move_ae_LN(src);\n");
+ out("ccr_68000_long_move_ae_LN(src);\n");
} else if (set_high_word) {
// High word: N and Z clear.
- out("\t\tccr_68000_long_move_ae_HNZ(src);\n");
+ out("ccr_68000_long_move_ae_HNZ(src);\n");
} else if (set_ccr) {
// Set normally.
- out("\t\tccr_68000_long_move_ae_normal(src);\n");
+ out("ccr_68000_long_move_ae_normal(src);\n");
}
}
}
if (dmode == Apdi) {
dummy_prefetch(NULL, NULL);
} else if (dmode == absl && smode >= Aind && smode < imm) {
- out("\t\tregs.irc = dsta >> 16;\n");
+ out("regs.irc = dsta >> 16;\n");
}
if (set_ccr) {
- out("\t\tccr_68000_word_move_ae_normal((uae_s16)(src));\n");
+ out("ccr_68000_word_move_ae_normal((uae_s16)(src));\n");
}
} else {
// Long MOVE is much more complex..
dummy_prefetch(NULL, NULL);
*setapdi = 0;
} else if (dmode == absl && smode >= Aind && smode < imm) {
- out("\t\tregs.irc = dsta >> 16;\n");
+ out("regs.irc = dsta >> 16;\n");
}
if (set_low_word == 1) {
// Low word: Z and N
- out("\t\tccr_68000_long_move_ae_LZN(src);\n");
+ out("ccr_68000_long_move_ae_LZN(src);\n");
} else if (set_low_word == 2) {
// Low word: N only
- out("\t\tccr_68000_long_move_ae_LN(src);\n");
+ out("ccr_68000_long_move_ae_LN(src);\n");
} else if (set_high_word) {
// High word: N and Z clear.
- out("\t\tccr_68000_long_move_ae_HNZ(src);\n");
+ out("ccr_68000_long_move_ae_HNZ(src);\n");
} else if (set_ccr) {
// Set normally.
- out("\t\tccr_68000_long_move_ae_normal(src);\n");
+ out("ccr_68000_long_move_ae_normal(src);\n");
}
}
}
case sz_byte:
#ifdef USE_DUBIOUS_BIGENDIAN_OPTIMIZATION
/* This causes the target compiler to generate better code on few systems */
- out("\tuae_s8 %s = ((uae_u8*)&m68k_dreg(regs, %s))[3];\n", name, reg);
+ out("uae_s8 %s = ((uae_u8*)&m68k_dreg(regs, %s))[3];\n", name, reg);
#else
- out("\tuae_s8 %s = m68k_dreg(regs, %s);\n", name, reg);
+ out("uae_s8 %s = m68k_dreg(regs, %s);\n", name, reg);
#endif
break;
case sz_word:
#ifdef USE_DUBIOUS_BIGENDIAN_OPTIMIZATION
- out("\tuae_s16 %s = ((uae_s16*)&m68k_dreg(regs, %s))[1];\n", name, reg);
+ out("uae_s16 %s = ((uae_s16*)&m68k_dreg(regs, %s))[1];\n", name, reg);
#else
- out("\tuae_s16 %s = m68k_dreg(regs, %s);\n", name, reg);
+ out("uae_s16 %s = m68k_dreg(regs, %s);\n", name, reg);
#endif
break;
case sz_long:
- out("\tuae_s32 %s = m68k_dreg(regs, %s);\n", name, reg);
+ out("uae_s32 %s = m68k_dreg(regs, %s);\n", name, reg);
break;
default:
term ();
if (getv == 1)
switch (size) {
case sz_word:
- out("\tuae_s16 %s = m68k_areg(regs, %s);\n", name, reg);
+ out("uae_s16 %s = m68k_areg(regs, %s);\n", name, reg);
break;
case sz_long:
- out("\tuae_s32 %s = m68k_areg(regs, %s);\n", name, reg);
+ out("uae_s32 %s = m68k_areg(regs, %s);\n", name, reg);
break;
default:
term ();
addcycles_ce020 (2);
break;
}
- out("\tuaecptr %sa;\n", name);
+ out("uaecptr %sa;\n", name);
add_mmu040_movem (movem);
- out("\t%sa = m68k_areg(regs, %s);\n", name, reg);
+ out("%sa = m68k_areg(regs, %s);\n", name, reg);
if ((flags & GF_NOFETCH) && using_prefetch) {
addcycles000(2);
}
case fetchmode_cea:
break;
}
- out("\tuaecptr %sa;\n", name);
+ out("uaecptr %sa;\n", name);
add_mmu040_movem (movem);
- out("\t%sa = m68k_areg(regs, %s);\n", name, reg);
+ out("%sa = m68k_areg(regs, %s);\n", name, reg);
if ((flags & GF_NOFETCH) && using_prefetch) {
addcycles000(4);
}
addcycles_ce020 (2);
break;
}
- out("\tuaecptr %sa;\n", name);
+ out("uaecptr %sa;\n", name);
add_mmu040_movem (movem);
switch (size) {
case sz_byte:
if (movem)
- out("\t%sa = m68k_areg(regs, %s);\n", name, reg);
+ out("%sa = m68k_areg(regs, %s);\n", name, reg);
else
- out("\t%sa = m68k_areg(regs, %s) - areg_byteinc[%s];\n", name, reg, reg);
+ out("%sa = m68k_areg(regs, %s) - areg_byteinc[%s];\n", name, reg, reg);
break;
case sz_word:
- out("\t%sa = m68k_areg(regs, %s) - %d;\n", name, reg, movem ? 0 : 2);
+ out("%sa = m68k_areg(regs, %s) - %d;\n", name, reg, movem ? 0 : 2);
break;
case sz_long:
- out("\t%sa = m68k_areg(regs, %s) - %d;\n", name, reg, movem ? 0 : 4);
+ out("%sa = m68k_areg(regs, %s) - %d;\n", name, reg, movem ? 0 : 4);
break;
default:
term ();
}
break;
case Ad16: // (d16,An)
- out("\tuaecptr %sa;\n", name);
+ out("uaecptr %sa;\n", name);
add_mmu040_movem (movem);
- out("\t%sa = m68k_areg(regs, %s) + (uae_s32)(uae_s16)%s;\n", name, reg, gen_nextiword (flags));
+ out("%sa = m68k_areg(regs, %s) + (uae_s32)(uae_s16)%s;\n", name, reg, gen_nextiword (flags));
count_read_ea++;
addr = true;
break;
case PC16: // (d16,PC)
- out("\tuaecptr %sa;\n", name);
+ out("uaecptr %sa;\n", name);
add_mmu040_movem (movem);
- out("\t%sa = %s + %d;\n", name, getpc, m68k_pc_offset);
- out("\t%sa += (uae_s32)(uae_s16)%s;\n", name, gen_nextiword (flags));
+ out("%sa = %s + %d;\n", name, getpc, m68k_pc_offset);
+ out("%sa += (uae_s32)(uae_s16)%s;\n", name, gen_nextiword (flags));
addr = true;
break;
case Ad8r: // (d8,An,Xn)
case fetchmode_jea:
break;
}
- out("\tuaecptr %sa;\n", name);
+ out("uaecptr %sa;\n", name);
if (cpu_level > 1) {
if (next_cpu_level < 1)
next_cpu_level = 1;
start_brace ();
/* This would ordinarily be done in gen_nextiword, which we bypass. */
insn_n_cycles += 4;
- out("\t%sa = %s(m68k_areg(regs, %s), %d);\n", name, disp020, reg, disp020cnt++);
+ out("%sa = %s(m68k_areg(regs, %s), %d);\n", name, disp020, reg, disp020cnt++);
} else {
if (!(flags & GF_AD8R) && !(flags & GF_NOFETCH) && !(flags & GF_CLR68010)) {
addcycles000 (2);
count_cycles_ea += 2;
}
if ((flags & GF_NOREFILL) && using_prefetch) {
- out("\t%sa = %s(m68k_areg(regs, %s), regs.irc);\n", name, disp000, reg);
+ out("%sa = %s(m68k_areg(regs, %s), regs.irc);\n", name, disp000, reg);
} else {
- out("\t%sa = %s(m68k_areg(regs, %s), %s);\n", name, disp000, reg, gen_nextiword (flags));
+ out("%sa = %s(m68k_areg(regs, %s), %s);\n", name, disp000, reg, gen_nextiword (flags));
}
count_read_ea++;
}
case fetchmode_jea:
break;
}
- out("\tuaecptr tmppc;\n");
- out("\tuaecptr %sa;\n", name);
+ out("uaecptr tmppc;\n");
+ out("uaecptr %sa;\n", name);
if (cpu_level > 1) {
if (next_cpu_level < 1)
next_cpu_level = 1;
start_brace ();
/* This would ordinarily be done in gen_nextiword, which we bypass. */
insn_n_cycles += 4;
- out("\ttmppc = %s;\n", getpc);
- out("\t%sa = %s(tmppc, %d);\n", name, disp020, disp020cnt++);
+ out("tmppc = %s;\n", getpc);
+ out("%sa = %s(tmppc, %d);\n", name, disp020, disp020cnt++);
} else {
- out("\ttmppc = %s + %d;\n", getpc, m68k_pc_offset);
+ out("tmppc = %s + %d;\n", getpc, m68k_pc_offset);
if (!(flags & GF_PC8R)) {
addcycles000 (2);
insn_n_cycles += 2;
count_cycles_ea += 2;
}
if ((flags & GF_NOREFILL) && using_prefetch) {
- out("\t%sa = %s(tmppc, regs.irc);\n", name, disp000);
+ out("%sa = %s(tmppc, regs.irc);\n", name, disp000);
} else {
- out("\t%sa = %s(tmppc, %s);\n", name, disp000, gen_nextiword (flags));
+ out("%sa = %s(tmppc, %s);\n", name, disp000, gen_nextiword (flags));
}
}
if ((flags & GF_NOFETCH) && using_prefetch) {
addr = true;
break;
case absw:
- out("\tuaecptr %sa;\n", name);
+ out("uaecptr %sa;\n", name);
add_mmu040_movem (movem);
- out("\t%sa = (uae_s32)(uae_s16)%s;\n", name, gen_nextiword (flags));
+ out("%sa = (uae_s32)(uae_s16)%s;\n", name, gen_nextiword (flags));
pc_68000_offset_fetch += 2;
addr = true;
break;
insn_n_cycles020++;
switch (size) {
case sz_byte:
- out("\tuae_s8 %s = %s;\n", name, gen_nextibyte (flags));
+ out("uae_s8 %s = %s;\n", name, gen_nextibyte (flags));
count_read_ea++;
break;
case sz_word:
- out("\tuae_s16 %s = %s;\n", name, gen_nextiword (flags));
+ out("uae_s16 %s = %s;\n", name, gen_nextiword (flags));
count_read_ea++;
break;
case sz_long:
case imm0:
if (getv != 1)
term ();
- out("\tuae_s8 %s = %s;\n", name, gen_nextibyte (flags));
+ out("uae_s8 %s = %s;\n", name, gen_nextibyte (flags));
count_read_ea++;
do_instruction_buserror();
maybeaddop_ce020 (flags);
case imm1:
if (getv != 1)
term ();
- out("\tuae_s16 %s = %s;\n", name, gen_nextiword (flags));
+ out("uae_s16 %s = %s;\n", name, gen_nextiword (flags));
count_read_ea++;
do_instruction_buserror();
maybeaddop_ce020 (flags);
case immi:
if (getv != 1)
term ();
- out("\tuae_u32 %s = %s;\n", name, reg);
+ out("uae_u32 %s = %s;\n", name, reg);
maybeaddop_ce020 (flags);
syncmovepc (getv, flags);
strcpy(g_srcname, name);
return;
case am_unknown:
// reg = internal variable
- out("\tuae_u32 %sa = %s;\n", name, reg);
+ out("uae_u32 %sa = %s;\n", name, reg);
addr = true;
break;
default:
next_level_000();
- out("\tif (%sa & 1) {\n", name);
+ out("if (%sa & 1) {\n", name);
if (cpu_level == 1) {
int bus_error_reg_add_old = bus_error_reg_add;
// 68010 does dummy access
if (getv != 2) {
if ((flags & GF_REVERSE) && size == sz_long) {
- out("\t\tuae_s16 d_%s = %s((%sa + 2) & ~1);\n", name, srcw, name);
+ out("uae_s16 d_%s = %s((%sa + 2) & ~1);\n", name, srcw, name);
} else {
- out("\t\tuae_s16 d_%s = %s(%sa & ~1);\n", name, srcw, name);
+ out("uae_s16 d_%s = %s(%sa & ~1);\n", name, srcw, name);
}
}
if (abs(bus_error_reg_add) == 4)
}
// x,-(an): an is modified (MOVE to CCR counts as word sized)
if (mode == Apdi && (g_instr->size == sz_word || g_instr->size == i_MV2SR) && g_instr->mnemo != i_CLR) {
- out("\t\tm68k_areg(regs, %s) = %sa;\n", reg, name);
+ out("m68k_areg(regs, %s) = %sa;\n", reg, name);
}
bus_error_reg_add = bus_error_reg_add_old;
}
if (g_instr->mnemo == i_ADDX || g_instr->mnemo == i_SUBX) {
// ADDX/SUBX special case
if (g_instr->size == sz_word) {
- out("\t\tm68k_areg(regs, %s) = %sa;\n", reg, name);
+ out("m68k_areg(regs, %s) = %sa;\n", reg, name);
}
} else if (mode == Apdi && g_instr->mnemo != i_LINK) {
// 68000 decrements register first, then checks for address error
// Change it to read because it does dummy read first.
exp3rw = 0;
if (cpu_level == 1) {
- out("\t\topcode |= 0x20000;\n"); // upper byte of SSW is zero -flag.
+ out("opcode |= 0x20000;\n"); // upper byte of SSW is zero -flag.
}
} else if (g_instr->mnemo == i_LINK) {
// a7 -> a0 copy done before A7 address error check
- out("\tm68k_areg(regs, srcreg) = olda;\n");
+ out("m68k_areg(regs, srcreg) = olda;\n");
setapdiback = 0;
}
if (setapdiback) {
- out("\t\tm68k_areg(regs, %s) = %sa;\n", reg, name);
+ out("m68k_areg(regs, %s) = %sa;\n", reg, name);
}
// MOVE.L EA,-(An) causing address error: stacked value is original An - 2, not An - 4.
if ((flags & (GF_REVERSE | GF_REVERSE2)) && size == sz_long && mode == Apdi)
- out("\t\t%sa += %d;\n", name, flags & GF_REVERSE2 ? -2 : 2);
+ out("%sa += %d;\n", name, flags & GF_REVERSE2 ? -2 : 2);
if (exp3rw) {
const char *shift = (size == sz_long && !(flags & GF_REVERSE)) ? " >> 16" : "";
- out("\t\texception3_write(opcode, %sa, %d, %s%s, %d);\n",
+ out("exception3_write(opcode, %sa, %d, %s%s, %d);\n",
name, size, g_srcname, shift,
// PC-relative: FC=2
(getv == 1 && (g_instr->smode == PC16 || g_instr->smode == PC8r) ? 2 : 1) | fcmodeflags);
} else {
- out("\t\texception3_read(opcode, %sa, %d, %d);\n",
+ out("exception3_read(opcode, %sa, %d, %d);\n",
name, size,
// PC-relative: FC=2
(getv == 1 && (g_instr->smode == PC16 || g_instr->smode == PC8r) ? 2 : 1) | fcmodeflags);
}
- write_return_cycles_noadd("\t\t", 0);
- out("\t}\n");
+ write_return_cycles_noadd("", 0);
+ out("}\n");
}
if (flags & GF_PREFETCH)
if (using_mmu) {
if (flags & GF_FC) {
switch (size) {
- case sz_byte: insn_n_cycles += 4; out("\tuae_s8 %s = sfc%s_get_byte%s(%sa);\n", name, mmu_postfix, xfc_postfix, name); break;
- case sz_word: insn_n_cycles += 4; out("\tuae_s16 %s = sfc%s_get_word%s(%sa);\n", name, mmu_postfix, xfc_postfix, name); break;
- case sz_long: insn_n_cycles += 8; out("\tuae_s32 %s = sfc%s_get_long%s(%sa);\n", name, mmu_postfix, xfc_postfix, name); break;
+ case sz_byte: insn_n_cycles += 4; out("uae_s8 %s = sfc%s_get_byte%s(%sa);\n", name, mmu_postfix, xfc_postfix, name); break;
+ case sz_word: insn_n_cycles += 4; out("uae_s16 %s = sfc%s_get_word%s(%sa);\n", name, mmu_postfix, xfc_postfix, name); break;
+ case sz_long: insn_n_cycles += 8; out("uae_s32 %s = sfc%s_get_long%s(%sa);\n", name, mmu_postfix, xfc_postfix, name); break;
default: term ();
}
} else {
switch (size) {
- case sz_byte: insn_n_cycles += 4; out("\tuae_s8 %s = %s(%sa);\n", name, (flags & GF_LRMW) ? srcblrmw : (rmw ? srcbrmw : srcb), name); break;
- case sz_word: insn_n_cycles += 4; out("\tuae_s16 %s = %s(%sa);\n", name, (flags & GF_LRMW) ? srcwlrmw : (rmw ? srcwrmw : srcw), name); break;
- case sz_long: insn_n_cycles += 8; out("\tuae_s32 %s = %s(%sa);\n", name, (flags & GF_LRMW) ? srcllrmw : (rmw ? srclrmw : srcl), name); break;
+ case sz_byte: insn_n_cycles += 4; out("uae_s8 %s = %s(%sa);\n", name, (flags & GF_LRMW) ? srcblrmw : (rmw ? srcbrmw : srcb), name); break;
+ case sz_word: insn_n_cycles += 4; out("uae_s16 %s = %s(%sa);\n", name, (flags & GF_LRMW) ? srcwlrmw : (rmw ? srcwrmw : srcw), name); break;
+ case sz_long: insn_n_cycles += 8; out("uae_s32 %s = %s(%sa);\n", name, (flags & GF_LRMW) ? srcllrmw : (rmw ? srclrmw : srcl), name); break;
default: term ();
}
}
switch (size) {
case sz_byte:
insn_n_cycles += 4;
- out("\tuae_s8 %s = %s(%sa);\n", name, srcbx, name);
+ out("uae_s8 %s = %s(%sa);\n", name, srcbx, name);
count_read++;
check_bus_error(name, 0, 0, 0, NULL, 1);
break;
case sz_word:
insn_n_cycles += 4;
- out("\tuae_s16 %s = %s(%sa);\n", name, srcwx, name);
+ out("uae_s16 %s = %s(%sa);\n", name, srcwx, name);
count_read++;
check_bus_error(name, 0, 0, 1, NULL, 1);
break;
case sz_long:
insn_n_cycles += 8;
- out("\tuae_s32 %s = %s(%sa);\n", name, srclx, name);
+ out("uae_s32 %s = %s(%sa);\n", name, srclx, name);
count_read += 2;
check_bus_error(name, 0, 0, 2, NULL, 1);
break;
case sz_byte:
{
insn_n_cycles += 4;
- out("\tuae_s8 %s = %s(%sa);\n", name, srcbx, name);
+ out("uae_s8 %s = %s(%sa);\n", name, srcbx, name);
count_read++;
check_bus_error(name, 0, 0, 0, NULL, 1);
break;
case sz_word:
{
insn_n_cycles += 4;
- out("\tuae_s16 %s = %s(%sa);\n", name, srcwx, name);
+ out("uae_s16 %s = %s(%sa);\n", name, srcwx, name);
count_read++;
check_bus_error(name, 0, 0, 1, NULL, 1);
break;
{
insn_n_cycles += 8;
if ((flags & GF_REVERSE) && mode == Apdi) {
- out("\tuae_s32 %s = %s(%sa + 2);\n", name, srcwx, name);
+ out("uae_s32 %s = %s(%sa + 2);\n", name, srcwx, name);
count_read++;
check_bus_error(name, 0, 0, 1, NULL, 1);
- out("\t%s |= %s(%sa) << 16; \n", name, srcwx, name);
+ out("%s |= %s(%sa) << 16; \n", name, srcwx, name);
count_read++;
check_bus_error(name, -2, 0, 1, NULL, 1);
} else {
- out("\tuae_s32 %s = %s(%sa) << 16;\n", name, srcwx, name);
+ out("uae_s32 %s = %s(%sa) << 16;\n", name, srcwx, name);
count_read++;
check_bus_error(name, 0, 0, 1, NULL, 1);
- out("\t%s |= %s(%sa + 2); \n", name, srcwx, name);
+ out("%s |= %s(%sa + 2); \n", name, srcwx, name);
count_read++;
check_bus_error(name, 2, 0, 1, NULL, 1);
}
switch (size) {
case sz_byte:
insn_n_cycles += 4;
- out("\tuae_s8 %s = %s(%sa);\n", name, srcbx, name);
+ out("uae_s8 %s = %s(%sa);\n", name, srcbx, name);
count_read++;
check_bus_error(name, 0, 0, 0, NULL, 1);
break;
case sz_word:
insn_n_cycles += 4;
- out("\tuae_s16 %s = %s(%sa);\n", name, srcwx, name);
+ out("uae_s16 %s = %s(%sa);\n", name, srcwx, name);
count_read++;
check_bus_error(name, 0, 0, 1, NULL, 1);
break;
case sz_long:
insn_n_cycles += 8;
- out("\tuae_s32 %s = %s(%sa);\n", name, srclx, name);
+ out("uae_s32 %s = %s(%sa);\n", name, srclx, name);
count_read += 2;
check_bus_error(name, 0, 0, 2, NULL, 1);
break;
case Aipi:
switch (size) {
case sz_byte:
- out("\tm68k_areg(regs, %s) += areg_byteinc[%s];\n", reg, reg);
+ out("m68k_areg(regs, %s) += areg_byteinc[%s];\n", reg, reg);
break;
case sz_word:
- out("\tm68k_areg(regs, %s) += 2;\n", reg);
+ out("m68k_areg(regs, %s) += 2;\n", reg);
break;
case sz_long:
- out("\tm68k_areg(regs, %s) += 4;\n", reg);
+ out("m68k_areg(regs, %s) += 4;\n", reg);
break;
default:
term();
}
break;
case Apdi:
- out("\tm68k_areg(regs, %s) = %sa;\n", reg, name);
+ out("m68k_areg(regs, %s) = %sa;\n", reg, name);
break;
default:
break;
subhead = gence020cycles_jea (curi, smode);
break;
default:
- out("\t/* No EA */\n");
+ out("/* No EA */\n");
break;
}
}
case Dreg:
switch (size) {
case sz_byte:
- out("\tm68k_dreg(regs, %s) = (m68k_dreg(regs, %s) & ~0xff) | ((%s) & 0xff);\n", reg, reg, from);
+ out("m68k_dreg(regs, %s) = (m68k_dreg(regs, %s) & ~0xff) | ((%s) & 0xff);\n", reg, reg, from);
break;
case sz_word:
- out("\tm68k_dreg(regs, %s) = (m68k_dreg(regs, %s) & ~0xffff) | ((%s) & 0xffff);\n", reg, reg, from);
+ out("m68k_dreg(regs, %s) = (m68k_dreg(regs, %s) & ~0xffff) | ((%s) & 0xffff);\n", reg, reg, from);
break;
case sz_long:
- out("\tm68k_dreg(regs, %s) = (%s);\n", reg, from);
+ out("m68k_dreg(regs, %s) = (%s);\n", reg, from);
break;
default:
term ();
case Areg:
switch (size) {
case sz_word:
- out("\tm68k_areg(regs, %s) = (uae_s32)(uae_s16)(%s);\n", reg, from);
+ out("m68k_areg(regs, %s) = (uae_s32)(uae_s16)(%s);\n", reg, from);
break;
case sz_long:
- out("\tm68k_areg(regs, %s) = (%s);\n", reg, from);
+ out("m68k_areg(regs, %s) = (%s);\n", reg, from);
break;
default:
term ();
case sz_byte:
insn_n_cycles += 4;
if (flags & GF_FC)
- out("\tdfc%s_put_byte%s(%sa, %s);\n", mmu_postfix, xfc_postfix, to, from);
+ out("dfc%s_put_byte%s(%sa, %s);\n", mmu_postfix, xfc_postfix, to, from);
else
- out("\t%s(%sa, %s);\n", (flags & GF_LRMW) ? dstblrmw : (candormw ? dstbrmw : dstb), to, from);
+ out("%s(%sa, %s);\n", (flags & GF_LRMW) ? dstblrmw : (candormw ? dstbrmw : dstb), to, from);
break;
case sz_word:
insn_n_cycles += 4;
if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
term ();
if (flags & GF_FC)
- out("\tdfc%s_put_word%s(%sa, %s);\n", mmu_postfix, xfc_postfix, to, from);
+ out("dfc%s_put_word%s(%sa, %s);\n", mmu_postfix, xfc_postfix, to, from);
else
- out("\t%s(%sa, %s);\n", (flags & GF_LRMW) ? dstwlrmw : (candormw ? dstwrmw : dstw), to, from);
+ out("%s(%sa, %s);\n", (flags & GF_LRMW) ? dstwlrmw : (candormw ? dstwrmw : dstw), to, from);
break;
case sz_long:
insn_n_cycles += 8;
if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
term ();
if (flags & GF_FC)
- out("\tdfc%s_put_long%s(%sa, %s);\n", mmu_postfix, xfc_postfix, to, from);
+ out("dfc%s_put_long%s(%sa, %s);\n", mmu_postfix, xfc_postfix, to, from);
else
- out("\t%s(%sa, %s);\n", (flags & GF_LRMW) ? dstllrmw : (candormw ? dstlrmw : dstl), to, from);
+ out("%s(%sa, %s);\n", (flags & GF_LRMW) ? dstllrmw : (candormw ? dstlrmw : dstl), to, from);
break;
default:
term ();
} else if (using_ce020 || using_prefetch_020) {
switch (size) {
case sz_byte:
- out("\t%s(%sa, %s);\n", dstbx, to, from);
+ out("%s(%sa, %s);\n", dstbx, to, from);
count_write++;
check_bus_error(to, 0, 1, 0, from, 1);
break;
case sz_word:
if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
term ();
- out("\t%s(%sa, %s);\n", dstwx, to, from);
+ out("%s(%sa, %s);\n", dstwx, to, from);
count_write++;
check_bus_error(to, 0, 1, 1, from, 1);
break;
case sz_long:
if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
term ();
- out("\t%s(%sa, %s);\n", dstlx, to, from);
+ out("%s(%sa, %s);\n", dstlx, to, from);
count_write += 2;
check_bus_error(to, 0, 1, 2, from, 1);
break;
switch (size) {
case sz_byte:
check_ipl_again();
- out("\tx_put_byte(%sa, %s);\n", to, from);
+ out("x_put_byte(%sa, %s);\n", to, from);
count_write++;
check_bus_error(to, 0, 1, 0, from, 1);
break;
if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
term ();
check_ipl_again();
- out("\tx_put_word(%sa, %s);\n", to, from);
+ out("x_put_word(%sa, %s);\n", to, from);
count_write++;
check_bus_error(to, 0, 1, 1, from, 1);
break;
if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
term ();
if (store_dir) {
- out("\t%s(%sa + 2, %s);\n", dstwx, to, from);
+ out("%s(%sa + 2, %s);\n", dstwx, to, from);
count_write++;
check_bus_error(to, 2, 1, 1, from, 1);
check_ipl_again();
if (store_dir > 1) {
fill_prefetch_next_after(0, NULL);
}
- out("\t%s(%sa, %s >> 16);\n", dstwx, to, from);
+ out("%s(%sa, %s >> 16);\n", dstwx, to, from);
sprintf(tmp, "%s >> 16", from);
count_write++;
check_bus_error(to, 0, 1, 1, tmp, 1);
} else {
- out("\t%s(%sa, %s >> 16);\n", dstwx, to, from);
+ out("%s(%sa, %s >> 16);\n", dstwx, to, from);
sprintf(tmp, "%s >> 16", from);
count_write++;
check_bus_error(to, 0, 1, 1, tmp, 1);
if (flags & GF_SECONDWORDSETFLAGS) {
genflags(flag_logical, g_instr->size, "src", "", "");
}
- out("\t%s(%sa + 2, %s);\n", dstwx, to, from);
+ out("%s(%sa + 2, %s);\n", dstwx, to, from);
count_write++;
check_bus_error(to, 2, 1, 1, from, 1);
}
switch (size) {
case sz_byte:
insn_n_cycles += 4;
- out("\t%s(%sa, %s);\n", dstbx, to, from);
+ out("%s(%sa, %s);\n", dstbx, to, from);
count_write++;
check_bus_error(to, 0, 1, 0, from, 1);
break;
insn_n_cycles += 4;
if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
term ();
- out("\t%s(%sa, %s);\n", dstwx, to, from);
+ out("%s(%sa, %s);\n", dstwx, to, from);
count_write++;
check_bus_error(to, 0, 1, 1, from, 1);
break;
if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
term ();
if (store_dir) {
- out("\t%s(%sa + 2, %s);\n", dstwx, to, from);
+ out("%s(%sa + 2, %s);\n", dstwx, to, from);
count_write++;
check_bus_error(to, 2, 1, 1, from, 1);
if (flags & GF_SECONDWORDSETFLAGS) {
if (store_dir > 1) {
fill_prefetch_next_after(0, NULL);
}
- out("\t%s(%sa, %s >> 16); \n", dstwx, to, from);
+ out("%s(%sa, %s >> 16); \n", dstwx, to, from);
sprintf(tmp, "%s >> 16", from);
count_write++;
check_bus_error(to, 0, 1, 1, tmp, 1);
} else {
- out("\t%s(%sa, %s >> 16);\n", dstwx, to, from);
+ out("%s(%sa, %s >> 16);\n", dstwx, to, from);
sprintf(tmp, "%s >> 16", from);
count_write++;
check_bus_error(to, 0, 1, 1, tmp, 1);
if (flags & GF_SECONDWORDSETFLAGS) {
genflags(flag_logical, g_instr->size, "src", "", "");
}
- out("\t%s(%sa + 2, %s); \n", dstwx, to, from);
+ out("%s(%sa + 2, %s); \n", dstwx, to, from);
count_write++;
check_bus_error(to, 2, 1, 1, from, 1);
}
switch (size) {
case sz_byte:
insn_n_cycles += 4;
- out("\t%s(%sa, %s);\n", dstbx, to, from);
+ out("%s(%sa, %s);\n", dstbx, to, from);
count_write++;
check_bus_error(to, 0, 1, 0, from, 1);
break;
insn_n_cycles += 4;
if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
term ();
- out("\t%s(%sa, %s);\n", dstwx, to, from);
+ out("%s(%sa, %s);\n", dstwx, to, from);
count_write++;
check_bus_error(to, 0, 1, 1, from, 1);
break;
insn_n_cycles += 8;
if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
term ();
- out("\t%s(%sa, %s);\n", dstlx, to, from);
+ out("%s(%sa, %s);\n", dstlx, to, from);
count_write += 2;
check_bus_error(to, 0, 1, 2, from, 1);
break;
}
if (!put) {
- out("\tuae_u32 tmp[16];\n");
- out("\tint tmpreg[16];\n");
- out("\tint idx = 0;\n");
+ out("uae_u32 tmp[16];\n");
+ out("int tmpreg[16];\n");
+ out("int idx = 0;\n");
for (int i = 0; i < 2; i++) {
char reg;
if (i == dphase)
reg = 'd';
else
reg = 'a';
- out("\twhile (%cmask) {\n", reg);
+ out("while (%cmask) {\n", reg);
if (apdi)
- out("\t\tsrca -= %d;\n", size);
- out("\t\ttmpreg[idx] = %s[%cmask] + %d;\n", index, reg, i == dphase ? 0 : 8);
- out("\t\ttmp[idx++] = %s;\n", code);
+ out("srca -= %d;\n", size);
+ out("tmpreg[idx] = %s[%cmask] + %d;\n", index, reg, i == dphase ? 0 : 8);
+ out("tmp[idx++] = %s;\n", code);
if (!apdi)
- out("\t\tsrca += %d;\n", size);
- out("\t\t%cmask = movem_next[%cmask];\n", reg, reg);
- out("\t}\n");
+ out("srca += %d;\n", size);
+ out("%cmask = movem_next[%cmask];\n", reg, reg);
+ out("}\n");
}
if (aipi || apdi)
- out("\tm68k_areg(regs, dstreg) = srca;\n");
- out("\twhile (--idx >= 0) {\n");
- out("\t\tregs.regs[tmpreg[idx]] = tmp[idx];\n");
- out("\t}\n");
+ out("m68k_areg(regs, dstreg) = srca;\n");
+ out("while (--idx >= 0) {\n");
+ out("regs.regs[tmpreg[idx]] = tmp[idx];\n");
+ out("}\n");
} else {
for (int i = 0; i < 2; i++) {
char reg;
reg = 'd';
else
reg = 'a';
- out("\twhile (%cmask) {\n", reg);
+ out("while (%cmask) {\n", reg);
if (apdi)
- out("\t\tsrca -= %d;\n", size);
+ out("srca -= %d;\n", size);
if (put) {
- out("\t\t%s, m68k_%creg (regs, %s[%cmask]));\n", code, reg, index, reg);
+ out("%s, m68k_%creg (regs, %s[%cmask]));\n", code, reg, index, reg);
} else {
- out("\t\tm68k_%creg (regs, %s[%cmask]) = %s;\n", reg, index, reg, code);
+ out("m68k_%creg (regs, %s[%cmask]) = %s;\n", reg, index, reg, code);
}
if (!apdi)
- out("\t\tsrca += %d;\n", size);
- out("\t\t%cmask = movem_next[%cmask];\n", reg, reg);
- out("\t}\n");
+ out("srca += %d;\n", size);
+ out("%cmask = movem_next[%cmask];\n", reg, reg);
+ out("}\n");
}
if (aipi || apdi)
- out("\tm68k_areg(regs, dstreg) = srca;\n");
+ out("m68k_areg(regs, dstreg) = srca;\n");
}
}
index = "movem_index1";
}
- out("\tmmu040_movem = 1;\n");
- out("\tmmu040_movem_ea = srca;\n");
+ out("mmu040_movem = 1;\n");
+ out("mmu040_movem_ea = srca;\n");
for (int i = 0; i < 2; i++) {
char reg;
reg = 'd';
else
reg = 'a';
- out("\twhile (%cmask) {\n", reg);
+ out("while (%cmask) {\n", reg);
if (apdi)
- out("\t\tsrca -= %d;\n", size);
+ out("srca -= %d;\n", size);
if (put) {
- out("\t\t%s, m68k_%creg (regs, %s[%cmask]));\n", code, reg, index, reg);
+ out("%s, m68k_%creg (regs, %s[%cmask]));\n", code, reg, index, reg);
} else {
- out("\t\tm68k_%creg (regs, %s[%cmask]) = %s;\n", reg, index, reg, code);
+ out("m68k_%creg (regs, %s[%cmask]) = %s;\n", reg, index, reg, code);
}
if (!apdi)
- out("\t\tsrca += %d;\n", size);
- out("\t\t%cmask = movem_next[%cmask];\n", reg, reg);
- out("\t}\n");
+ out("srca += %d;\n", size);
+ out("%cmask = movem_next[%cmask];\n", reg, reg);
+ out("}\n");
}
if (aipi || apdi)
- out("\tm68k_areg(regs, dstreg) = srca;\n");
- out("\tmmu040_movem = 0;\n");
+ out("m68k_areg(regs, dstreg) = srca;\n");
+ out("mmu040_movem = 0;\n");
}
/* 68030 MMU does not restore register state if it bus faults.
index = "movem_index1";
}
if (put && MMU68030_LAST_WRITE) {
- out("\tint prefetch = 0;\n");
+ out("int prefetch = 0;\n");
}
- out("\tmmu030_state[1] |= MMU030_STATEFLAG1_MOVEM1;\n");
- out("\tint movem_cnt = 0;\n");
+ out("mmu030_state[1] |= MMU030_STATEFLAG1_MOVEM1;\n");
+ out("int movem_cnt = 0;\n");
if (!put) {
- out("\tuae_u32 val;\n");
+ out("uae_u32 val;\n");
// Store original EA because MOVEM from memory may modify same register
- out("\tsrca = state_store_mmu030(srca);\n");
+ out("srca = state_store_mmu030(srca);\n");
}
for (int i = 0; i < 2; i++) {
char reg;
reg = 'd';
else
reg = 'a';
- out("\twhile (%cmask) {\n", reg);
- out("\t\tuae_u16 nextmask = movem_next[%cmask];\n", reg);
+ out("while (%cmask) {\n", reg);
+ out("uae_u16 nextmask = movem_next[%cmask];\n", reg);
if (apdi)
- out("\t\tsrca -= %d;\n", size);
- out("\t\tif (mmu030_state[0] == movem_cnt) {\n");
- out("\t\t\tif (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {\n");
- out("\t\t\t\tmmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;\n");
+ out("srca -= %d;\n", size);
+ out("if (mmu030_state[0] == movem_cnt) {\n");
+ out("if (mmu030_state[1] & MMU030_STATEFLAG1_MOVEM2) {\n");
+ out("mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM2;\n");
if (!put)
- out("\t\t\t\tval = %smmu030_data_buffer_out;\n", size == 2 ? "(uae_s32)(uae_s16)" : "");
- out("\t\t\t} else {\n");
+ out("val = %smmu030_data_buffer_out;\n", size == 2 ? "(uae_s32)(uae_s16)" : "");
+ out("} else {\n");
if (put) {
- out("\t\t\t\tmmu030_data_buffer_out = m68k_%creg(regs, %s[%cmask]);\n", reg, index, reg);
+ out("mmu030_data_buffer_out = m68k_%creg(regs, %s[%cmask]);\n", reg, index, reg);
if (MMU68030_LAST_WRITE) {
// last write?
if (dphase == i)
- out("\t\t\t\tif(!amask && !nextmask) {\n");
+ out("if(!amask && !nextmask) {\n");
else
- out("\t\t\t\tif(!dmask && !nextmask) {\n");
+ out("if(!dmask && !nextmask) {\n");
get_prefetch_020();
gen_set_fault_pc(true, false);
- out("\t\t\t\t\tmmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM1;\n");
+ out("mmu030_state[1] &= ~MMU030_STATEFLAG1_MOVEM1;\n");
m68k_pc_offset = old_m68k_pc_offset;
- out("\t\t\t\t\tprefetch = 1;\n");
+ out("prefetch = 1;\n");
if (aipi || apdi)
- out("\tm68k_areg(regs, dstreg) = srca;\n");
- out("\t\t\t\t}\n");
+ out("m68k_areg(regs, dstreg) = srca;\n");
+ out("}\n");
}
- out("\t\t\t\t%s, mmu030_data_buffer_out);\n", code);
+ out("%s, mmu030_data_buffer_out);\n", code);
} else {
- out("\t\t\t\tval = %s;\n", code);
+ out("val = %s;\n", code);
}
- out("\t\t\t}\n");
+ out("}\n");
if (!put) {
- out("\t\t\tm68k_%creg (regs, %s[%cmask]) = val;\n", reg, index, reg);
+ out("m68k_%creg (regs, %s[%cmask]) = val;\n", reg, index, reg);
}
- out("\t\t\tmmu030_state[0]++;\n");
- out("\t\t}\n");
+ out("mmu030_state[0]++;\n");
+ out("}\n");
if (!apdi)
- out("\t\tsrca += %d;\n", size);
- out("\t\tmovem_cnt++;\n");
- out("\t\t%cmask = nextmask;\n", reg);
- out("\t}\n");
+ out("srca += %d;\n", size);
+ out("movem_cnt++;\n");
+ out("%cmask = nextmask;\n", reg);
+ out("}\n");
}
if (aipi || apdi)
- out("\tm68k_areg(regs, dstreg) = srca;\n");
+ out("m68k_areg(regs, dstreg) = srca;\n");
if (put) {
if (MMU68030_LAST_WRITE) {
// if both masks are zero
- out("\tif(prefetch == 0) {\n");
+ out("if(prefetch == 0) {\n");
if (using_prefetch_020) {
get_prefetch_020();
}
sync_m68k_pc();
- out("\t}\n");
+ out("}\n");
m68k_pc_offset = 0;
} else {
if (using_prefetch_020) {
if (write) {
// MOVEM write to memory won't generate address error
// exception if mask is zero and EA is odd.
- out("\tif ((amask || dmask) && (srca & 1)) {\n");
+ out("if ((amask || dmask) && (srca & 1)) {\n");
// MOVE.L EA,-(An) causing address error: stacked value is original An - 2, not An - 4.
if (g_instr->dmode == Apdi) {
- out("\t\tsrca -= 2;\n");
+ out("srca -= 2;\n");
}
- out("\t\tuaecptr srcav = srca;\n");
+ out("uaecptr srcav = srca;\n");
if (cpu_level == 1) {
if (g_instr->dmode == Apdi) {
- out("\t\tif(amask) {\n");
- out("\t\t\tsrcav = m68k_areg(regs, movem_index2[amask]);\n");
- out("\t\t} else if (dmask) {\n");
- out("\t\t\tsrcav = m68k_dreg(regs, movem_index2[dmask]);\n");
- out("\t\t}\n");
+ out("if(amask) {\n");
+ out("srcav = m68k_areg(regs, movem_index2[amask]);\n");
+ out("} else if (dmask) {\n");
+ out("srcav = m68k_dreg(regs, movem_index2[dmask]);\n");
+ out("}\n");
} else {
int shift = g_instr->size == sz_long ? 16 : 0;
- out("\t\tif(dmask) {\n");
- out("\t\t\tsrcav = m68k_dreg(regs, movem_index1[dmask]) >> %d;\n", shift);
- out("\t\t} else if (amask) {\n");
- out("\t\t\tsrcav = m68k_areg(regs, movem_index1[amask]) >> %d;\n", shift);
- out("\t\t}\n");
+ out("if(dmask) {\n");
+ out("srcav = m68k_dreg(regs, movem_index1[dmask]) >> %d;\n", shift);
+ out("} else if (amask) {\n");
+ out("srcav = m68k_areg(regs, movem_index1[amask]) >> %d;\n", shift);
+ out("}\n");
}
if (g_instr->dmode == Aind || g_instr->dmode == Apdi || g_instr->dmode == Aipi) {
- out("\t\tregs.read_buffer = mask;\n");
+ out("regs.read_buffer = mask;\n");
}
}
} else {
// MOVEM from memory will generate address error
// exception if mask is zero and EA is odd.
- out("\tif (srca & 1) {\n");
+ out("if (srca & 1) {\n");
if ((g_instr->dmode == PC16 || g_instr->dmode == PC8r) && cpu_level == 0) {
- out("\t\topcode |= 0x00020000;\n");
+ out("opcode |= 0x00020000;\n");
}
- out("\t\tuaecptr srcav = srca;\n");
+ out("uaecptr srcav = srca;\n");
if (cpu_level == 1) {
- out("\t\tuae_s16 dummy = %s(srca & ~1);\n", srcw);
+ out("uae_s16 dummy = %s(srca & ~1);\n", srcw);
}
}
if (write) {
- out("\t\texception3_write(opcode, srca, %d, srcav, %d);\n",
+ out("exception3_write(opcode, srca, %d, srcav, %d);\n",
g_instr->size,
(g_instr->dmode == PC16 || g_instr->dmode == PC8r) ? 2 : 1);
} else {
- out("\t\texception3_read(opcode, srca, %d, %d);\n",
+ out("exception3_read(opcode, srca, %d, %d);\n",
g_instr->size,
(g_instr->dmode == PC16 || g_instr->dmode == PC8r) ? 2 : 1);
}
- write_return_cycles("\t\t", 0);
- out("\t}\n");
+ write_return_cycles("", 0);
+ out("}\n");
}
}
sprintf(getcode, "(uae_s32)(uae_s16)%s(srca)", srcwd);
}
count_read += table68k[opcode].size == sz_long ? 2 : 1;
- out("\tuae_u16 mask = %s;\n", gen_nextiword (0));
- out("\tuae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
+ out("uae_u16 mask = %s;\n", gen_nextiword (0));
+ out("uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
genamode (NULL, table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, mmu040_special_movem (opcode) ? -3 : -1, GF_MOVE);
movem_ex3(0);
addcycles_ce020 (8 - 2);
} else if (using_mmu == 68040) {
movem_mmu040 (getcode, size, false, table68k[opcode].dmode == Aipi, false, opcode);
} else {
- out("\twhile (dmask) {\n");
- out("\t\tm68k_dreg(regs, movem_index1[dmask]) = %s;\n", getcode);
+ out("while (dmask) {\n");
+ out("m68k_dreg(regs, movem_index1[dmask]) = %s;\n", getcode);
check_bus_error("src", 0, 0, table68k[opcode].size, NULL, 1);
- out("\t\tsrca += %d;\n", size);
- out("\t\tdmask = movem_next[dmask];\n");
- out("\t}\n");
- out("\twhile (amask) {\n");
- out("\t\tm68k_areg(regs, movem_index1[amask]) = %s;\n", getcode);
+ out("srca += %d;\n", size);
+ out("dmask = movem_next[dmask];\n");
+ out("}\n");
+ out("while (amask) {\n");
+ out("m68k_areg(regs, movem_index1[amask]) = %s;\n", getcode);
check_bus_error("src", 0, 0, table68k[opcode].size, NULL, 1);
- out("\t\tsrca += %d;\n", size);
- out("\t\tamask = movem_next[amask];\n");
- out("\t}\n");
+ out("srca += %d;\n", size);
+ out("amask = movem_next[amask];\n");
+ out("}\n");
if (table68k[opcode].dmode == Aipi) {
- out("\tm68k_areg(regs, dstreg) = srca;\n");
+ out("m68k_areg(regs, dstreg) = srca;\n");
count_read++;
}
}
static void genmovemel_ce (uae_u16 opcode)
{
int size = table68k[opcode].size == sz_long ? 4 : 2;
- out("\tuae_u16 mask = %s;\n", gen_nextiword (0));
+ out("uae_u16 mask = %s;\n", gen_nextiword (0));
check_prefetch_buserror(m68k_pc_offset);
- out("\tuae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
+ out("uae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
if (table68k[opcode].dmode == Ad8r || table68k[opcode].dmode == PC8r)
addcycles000(2);
genamode(NULL, table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, -1, GF_AA | GF_MOVE);
movem_ex3(0);
start_brace();
if (table68k[opcode].size == sz_long) {
- out("\twhile (dmask) {\n");
- out("\t\tuae_u32 v = (%s(srca) << 16) | (m68k_dreg(regs, movem_index1[dmask]) & 0xffff);\n", srcw);
- addcycles000_nonce("\t\t", 4);
+ out("while (dmask) {\n");
+ out("uae_u32 v = (%s(srca) << 16) | (m68k_dreg(regs, movem_index1[dmask]) & 0xffff);\n", srcw);
+ addcycles000_nonce("", 4);
check_bus_error("src", 0, 0, 1, NULL, 1);
- out("\t\tm68k_dreg(regs, movem_index1[dmask]) = v;\n");
- out("\t\tv &= 0xffff0000;\n");
- out("\t\tv |= %s(srca + 2); \n", srcw);
- addcycles000_nonce("\t\t", 4);
+ out("m68k_dreg(regs, movem_index1[dmask]) = v;\n");
+ out("v &= 0xffff0000;\n");
+ out("v |= %s(srca + 2); \n", srcw);
+ addcycles000_nonce("", 4);
check_bus_error("src", 2, 0, 1, NULL, 1);
- out("\t\tm68k_dreg(regs, movem_index1[dmask]) = v;\n");
- out("\t\tsrca += %d;\n", size);
- out("\t\tdmask = movem_next[dmask];\n");
- out("\t}\n");
- out("\twhile (amask) {\n");
- out("\t\tuae_u32 v = (%s(srca) << 16) | (m68k_areg(regs, movem_index1[amask]) & 0xffff);\n", srcw);
- addcycles000_nonce("\t\t", 4);
+ out("m68k_dreg(regs, movem_index1[dmask]) = v;\n");
+ out("srca += %d;\n", size);
+ out("dmask = movem_next[dmask];\n");
+ out("}\n");
+ out("while (amask) {\n");
+ out("uae_u32 v = (%s(srca) << 16) | (m68k_areg(regs, movem_index1[amask]) & 0xffff);\n", srcw);
+ addcycles000_nonce("", 4);
check_bus_error("src", 0, 0, 1, NULL, 1);
- out("\t\tm68k_areg(regs, movem_index1[amask]) = v;\n");
- out("\t\tv &= 0xffff0000;\n");
- out("\t\tv |= %s(srca + 2);\n", srcw);
- addcycles000_nonce("\t\t", 4);
+ out("m68k_areg(regs, movem_index1[amask]) = v;\n");
+ out("v &= 0xffff0000;\n");
+ out("v |= %s(srca + 2);\n", srcw);
+ addcycles000_nonce("", 4);
check_bus_error("src", 2, 0, 1, NULL, 1);
- out("\t\tm68k_areg(regs, movem_index1[amask]) = v;\n");
- out("\t\tsrca += %d;\n", size);
- out("\t\tamask = movem_next[amask];\n");
- out("\t}\n");
+ out("m68k_areg(regs, movem_index1[amask]) = v;\n");
+ out("srca += %d;\n", size);
+ out("amask = movem_next[amask];\n");
+ out("}\n");
} else {
- out("\twhile (dmask) {\n");
- out("\t\tuae_u32 v = (uae_s32)(uae_s16)%s(srca);\n", srcw);
- addcycles000_nonce("\t\t", 4);
+ out("while (dmask) {\n");
+ out("uae_u32 v = (uae_s32)(uae_s16)%s(srca);\n", srcw);
+ addcycles000_nonce("", 4);
check_bus_error("src", 0, 0, 1, NULL, 1);
- out("\t\tm68k_dreg(regs, movem_index1[dmask]) = v;\n");
- out("\t\tsrca += %d;\n", size);
- out("\t\tdmask = movem_next[dmask];\n");
- out("\t}\n");
- out("\twhile (amask) {\n");
- out("\t\tuae_u32 v = (uae_s32)(uae_s16)%s(srca);\n", srcw);
- addcycles000_nonce("\t\t", 4);
+ out("m68k_dreg(regs, movem_index1[dmask]) = v;\n");
+ out("srca += %d;\n", size);
+ out("dmask = movem_next[dmask];\n");
+ out("}\n");
+ out("while (amask) {\n");
+ out("uae_u32 v = (uae_s32)(uae_s16)%s(srca);\n", srcw);
+ addcycles000_nonce("", 4);
check_bus_error("src", 0, 0, 1, NULL, 1);
- out("\t\tm68k_areg(regs, movem_index1[amask]) = v;\n");
- out("\t\tsrca += %d;\n", size);
- out("\t\tamask = movem_next[amask];\n");
- out("\t}\n");
+ out("m68k_areg(regs, movem_index1[amask]) = v;\n");
+ out("srca += %d;\n", size);
+ out("amask = movem_next[amask];\n");
+ out("}\n");
}
- out("\t%s(srca);\n", srcw); // and final extra word fetch that goes nowhere..
+ out("%s(srca);\n", srcw); // and final extra word fetch that goes nowhere..
check_bus_error("src", 0, 0, 1, NULL, 1);
count_read++;
if (table68k[opcode].dmode == Aipi)
- out("\tm68k_areg(regs, dstreg) = srca;\n");
+ out("m68k_areg(regs, dstreg) = srca;\n");
count_ncycles++;
fill_prefetch_next_t();
}
}
count_write += table68k[opcode].size == sz_long ? 2 : 1;
- out("\tuae_u16 mask = %s;\n", gen_nextiword (0));
+ out("uae_u16 mask = %s;\n", gen_nextiword (0));
genamode (NULL, table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, mmu040_special_movem (opcode) ? 3 : 1, GF_MOVE);
addcycles_ce020 (4 - 2);
start_brace ();
if (using_mmu >= 68030) {
if (table68k[opcode].dmode == Apdi)
- out("\tuae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;\n");
+ out("uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;\n");
else
- out("\tuae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
+ out("uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
if (using_mmu == 68030) {
movem_mmu030(putcode, size, true, false, table68k[opcode].dmode == Apdi);
count_ncycles++;
}
} else {
if (table68k[opcode].dmode == Apdi) {
- out("\tuae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;\n");
+ out("uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;\n");
movem_ex3(1);
if (!using_mmu)
- out("\tint type = get_cpu_model () >= 68020;\n");
- out("\twhile (amask) {\n");
- out("\t\tsrca -= %d;\n", size);
+ out("int type = get_cpu_model () >= 68020;\n");
+ out("while (amask) {\n");
+ out("srca -= %d;\n", size);
- out("\t\tif (!type || movem_index2[amask] != dstreg) {\n");
- out("\t\t\t%s, m68k_areg(regs, movem_index2[amask]));\n", putcode);
+ out("if (!type || movem_index2[amask] != dstreg) {\n");
+ out("%s, m68k_areg(regs, movem_index2[amask]));\n", putcode);
check_bus_error("src", 0, 1, table68k[opcode].size, "m68k_areg(regs, movem_index2[amask])", 1);
- out("\t\t} else {\n");
- out("\t\t\t%s, m68k_areg(regs, movem_index2[amask]) - %d);\n", putcode, size);
+ out("} else {\n");
+ out("%s, m68k_areg(regs, movem_index2[amask]) - %d);\n", putcode, size);
if (size == 4) {
check_bus_error("src", 0, 1, table68k[opcode].size, "m68k_areg(regs, movem_index2[amask]) - 4", 1);
} else {
check_bus_error("src", 0, 1, table68k[opcode].size, "m68k_areg(regs, movem_index2[amask]) - 2", 1);
}
- out("\t\t}\n");
- out("\t\tamask = movem_next[amask];\n");
- out("\t}\n");
- out("\twhile (dmask) {\n");
- out("\t\tsrca -= %d;\n", size);
- out("\t\t%s, m68k_dreg(regs, movem_index2[dmask]));\n", putcode);
+ out("}\n");
+ out("amask = movem_next[amask];\n");
+ out("}\n");
+ out("while (dmask) {\n");
+ out("srca -= %d;\n", size);
+ out("%s, m68k_dreg(regs, movem_index2[dmask]));\n", putcode);
check_bus_error("src", 0, 1, table68k[opcode].size, "m68k_dreg(regs, movem_index2[dmask])", 1);
- out("\t\tdmask = movem_next[dmask];\n");
- out("\t}\n");
- out("\tm68k_areg(regs, dstreg) = srca;\n");
+ out("dmask = movem_next[dmask];\n");
+ out("}\n");
+ out("m68k_areg(regs, dstreg) = srca;\n");
} else {
- out("\tuae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
- out("\twhile (dmask) {\n");
- out("\t\t%s, m68k_dreg(regs, movem_index1[dmask]));\n", putcode);
+ out("uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
+ out("while (dmask) {\n");
+ out("%s, m68k_dreg(regs, movem_index1[dmask]));\n", putcode);
check_bus_error("src", 0, 1, table68k[opcode].size, "m68k_dreg(regs, movem_index1[dmask])", 1);
- out("\t\tsrca += %d;\n", size);
- out("\t\tdmask = movem_next[dmask];\n");
- out("\t}\n");
- out("\twhile (amask) {\n");
- out("\t\t%s, m68k_areg(regs, movem_index1[amask]));\n", putcode);
+ out("srca += %d;\n", size);
+ out("dmask = movem_next[dmask];\n");
+ out("}\n");
+ out("while (amask) {\n");
+ out("%s, m68k_areg(regs, movem_index1[amask]));\n", putcode);
check_bus_error("src", 0, 1, table68k[opcode].size, "m68k_areg(regs, movem_index1[amask])", 1);
- out("\t\tsrca += %d;\n", size);
- out("\t\tamask = movem_next[amask];\n");
- out("\t}\n");
+ out("srca += %d;\n", size);
+ out("amask = movem_next[amask];\n");
+ out("}\n");
}
}
count_ncycles++;
{
int size = table68k[opcode].size == sz_long ? 4 : 2;
- out("\tuae_u16 mask = %s;\n", gen_nextiword (0));
+ out("uae_u16 mask = %s;\n", gen_nextiword (0));
check_prefetch_buserror(m68k_pc_offset);
if (table68k[opcode].dmode == Ad8r || table68k[opcode].dmode == PC8r)
addcycles000 (2);
start_brace ();
if (table68k[opcode].size == sz_long) {
if (table68k[opcode].dmode == Apdi) {
- out("\tuae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;\n");
+ out("uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;\n");
movem_ex3(1);
- out("\twhile (amask) {\n");
- out("\t\t%s(srca - 2, m68k_areg(regs, movem_index2[amask]));\n", dstw);
- addcycles000_nonce("\t\t", 4);
+ out("while (amask) {\n");
+ out("%s(srca - 2, m68k_areg(regs, movem_index2[amask]));\n", dstw);
+ addcycles000_nonce("", 4);
check_bus_error("src", -2, 1, 1, "m68k_areg(regs, movem_index2[amask])", 1);
- out("\t\t%s(srca - 4, m68k_areg(regs, movem_index2[amask]) >> 16);\n", dstw);
- addcycles000_nonce("\t\t", 4);
+ out("%s(srca - 4, m68k_areg(regs, movem_index2[amask]) >> 16);\n", dstw);
+ addcycles000_nonce("", 4);
check_bus_error("src", -4, 1, 1, "m68k_areg(regs, movem_index2[amask]) >> 16", 1);
- out("\t\tsrca -= %d;\n", size);
- out("\t\tamask = movem_next[amask];\n");
- out("\t}\n");
- out("\twhile (dmask) {\n");
- out("\t\t%s(srca - 2, m68k_dreg(regs, movem_index2[dmask]));\n", dstw);
- addcycles000_nonce("\t\t", 4);
+ out("srca -= %d;\n", size);
+ out("amask = movem_next[amask];\n");
+ out("}\n");
+ out("while (dmask) {\n");
+ out("%s(srca - 2, m68k_dreg(regs, movem_index2[dmask]));\n", dstw);
+ addcycles000_nonce("", 4);
check_bus_error("src", -2, 1, 1, "m68k_dreg(regs, movem_index2[dmask])", 1);
- out("\t\t%s(srca - 4, m68k_dreg(regs, movem_index2[dmask]) >> 16);\n", dstw);
- addcycles000_nonce("\t\t", 4);
+ out("%s(srca - 4, m68k_dreg(regs, movem_index2[dmask]) >> 16);\n", dstw);
+ addcycles000_nonce("", 4);
check_bus_error("src", -4, 1, 1, "m68k_dreg(regs, movem_index2[dmask]) >> 16", 1);
- out("\t\tsrca -= %d;\n", size);
- out("\t\tdmask = movem_next[dmask];\n");
- out("\t}\n");
- out("\tm68k_areg(regs, dstreg) = srca;\n");
+ out("srca -= %d;\n", size);
+ out("dmask = movem_next[dmask];\n");
+ out("}\n");
+ out("m68k_areg(regs, dstreg) = srca;\n");
} else {
- out("\tuae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
+ out("uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
movem_ex3(1);
- out("\twhile (dmask) {\n");
- out("\t\t%s(srca, m68k_dreg(regs, movem_index1[dmask]) >> 16);\n", dstw);
- addcycles000_nonce("\t\t", 4);
+ out("while (dmask) {\n");
+ out("%s(srca, m68k_dreg(regs, movem_index1[dmask]) >> 16);\n", dstw);
+ addcycles000_nonce("", 4);
check_bus_error("src", 0, 1, 1, "m68k_dreg(regs, movem_index1[dmask]) >> 16", 1);
- out("\t\t%s(srca + 2, m68k_dreg(regs, movem_index1[dmask]));\n", dstw);
- addcycles000_nonce("\t\t", 4);
+ out("%s(srca + 2, m68k_dreg(regs, movem_index1[dmask]));\n", dstw);
+ addcycles000_nonce("", 4);
check_bus_error("src", 2, 1, 1, "m68k_dreg(regs, movem_index1[dmask])", 1);
- out("\t\tsrca += %d;\n", size);
- out("\t\tdmask = movem_next[dmask];\n");
- out("\t}\n");
- out("\twhile (amask) {\n");
- out("\t\t%s(srca, m68k_areg(regs, movem_index1[amask]) >> 16);\n", dstw);
- addcycles000_nonce("\t\t", 4);
+ out("srca += %d;\n", size);
+ out("dmask = movem_next[dmask];\n");
+ out("}\n");
+ out("while (amask) {\n");
+ out("%s(srca, m68k_areg(regs, movem_index1[amask]) >> 16);\n", dstw);
+ addcycles000_nonce("", 4);
check_bus_error("src", 0, 1, 1, "m68k_areg(regs, movem_index1[amask]) >> 16", 1);
- out("\t\t%s(srca + 2, m68k_areg(regs, movem_index1[amask]));\n", dstw);
- addcycles000_nonce("\t\t", 4);
+ out("%s(srca + 2, m68k_areg(regs, movem_index1[amask]));\n", dstw);
+ addcycles000_nonce("", 4);
check_bus_error("src", 2, 1, 1, "m68k_areg(regs, movem_index1[amask])", 1);
- out("\t\tsrca += %d;\n", size);
- out("\t\tamask = movem_next[amask];\n");
- out("\t}\n");
+ out("srca += %d;\n", size);
+ out("amask = movem_next[amask];\n");
+ out("}\n");
}
} else {
if (table68k[opcode].dmode == Apdi) {
- out("\tuae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;\n");
+ out("uae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;\n");
movem_ex3(1);
- out("\twhile (amask) {\n");
- out("\t\tsrca -= %d;\n", size);
- out("\t\t%s(srca, m68k_areg(regs, movem_index2[amask]));\n", dstw);
- addcycles000_nonce("\t\t", 4);
+ out("while (amask) {\n");
+ out("srca -= %d;\n", size);
+ out("%s(srca, m68k_areg(regs, movem_index2[amask]));\n", dstw);
+ addcycles000_nonce("", 4);
check_bus_error("src", 0, 1, 1, "m68k_areg(regs, movem_index2[amask])", 1);
- out("\tamask = movem_next[amask];\n");
- out("\t}\n");
- out("\twhile (dmask) {\n");
- out("\t\tsrca -= %d;\n", size);
- out("\t\t%s(srca, m68k_dreg(regs, movem_index2[dmask]));\n", dstw);
- addcycles000_nonce("\t\t", 4);
+ out("amask = movem_next[amask];\n");
+ out("}\n");
+ out("while (dmask) {\n");
+ out("srca -= %d;\n", size);
+ out("%s(srca, m68k_dreg(regs, movem_index2[dmask]));\n", dstw);
+ addcycles000_nonce("", 4);
check_bus_error("src", 0, 1, 1, "m68k_dreg(regs, movem_index2[dmask])", 1);
- out("\t\tdmask = movem_next[dmask];\n");
- out("\t}\n");
- out("\tm68k_areg(regs, dstreg) = srca;\n");
+ out("dmask = movem_next[dmask];\n");
+ out("}\n");
+ out("m68k_areg(regs, dstreg) = srca;\n");
} else {
- out("\tuae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
+ out("uae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
movem_ex3(1);
- out("\twhile (dmask) {\n");
- out("\t\t%s(srca, m68k_dreg(regs, movem_index1[dmask]));\n", dstw);
- addcycles000_nonce("\t\t", 4);
+ out("while (dmask) {\n");
+ out("%s(srca, m68k_dreg(regs, movem_index1[dmask]));\n", dstw);
+ addcycles000_nonce("", 4);
check_bus_error("src", 0, 1, 1, "m68k_dreg(regs, movem_index1[dmask])", 1);
- out("\t\tsrca += %d;\n", size);
- out("\t\tdmask = movem_next[dmask];\n");
- out("\t}\n");
- out("\twhile (amask) {\n");
- out("\t\t%s(srca, m68k_areg(regs, movem_index1[amask]));\n", dstw);
- addcycles000_nonce("\t\t", 4);
+ out("srca += %d;\n", size);
+ out("dmask = movem_next[dmask];\n");
+ out("}\n");
+ out("while (amask) {\n");
+ out("%s(srca, m68k_areg(regs, movem_index1[amask]));\n", dstw);
+ addcycles000_nonce("", 4);
check_bus_error("src", 0, 1, 1, "m68k_areg(regs, movem_index1[amask])", 1);
- out("\t\tsrca += %d;\n", size);
- out("\t\tamask = movem_next[amask];\n");
- out("\t}\n");
+ out("srca += %d;\n", size);
+ out("amask = movem_next[amask];\n");
+ out("}\n");
}
}
count_ncycles++;
/* Could do a modulo operation here... which one is faster? */
switch (size) {
case sz_long:
- out("\tif (%s >= 33) %s -= 33;\n", var, var);
+ out("if (%s >= 33) %s -= 33;\n", var, var);
break;
case sz_word:
- out("\tif (%s >= 34) %s -= 34;\n", var, var);
- out("\tif (%s >= 17) %s -= 17;\n", var, var);
+ out("if (%s >= 34) %s -= 34;\n", var, var);
+ out("if (%s >= 17) %s -= 17;\n", var, var);
break;
case sz_byte:
- out("\tif (%s >= 36) %s -= 36;\n", var, var);
- out("\tif (%s >= 18) %s -= 18;\n", var, var);
- out("\tif (%s >= 9) %s -= 9;\n", var, var);
+ out("if (%s >= 36) %s -= 36;\n", var, var);
+ out("if (%s >= 18) %s -= 18;\n", var, var);
+ out("if (%s >= 9) %s -= 9;\n", var, var);
break;
}
}
if (isreg (dmode)) {
int c = size == sz_long ? 4 : 2;
if (using_ce) {
- out("\t{\n");
- out("\t\tint cycles = %d;\n", c);
- out("\t\tcycles += 2 * ccnt;\n");
- addcycles000_3 ("\t\t");
- out("\t}\n");
+ out("{\n");
+ out("int cycles = %d;\n", c);
+ out("cycles += 2 * ccnt;\n");
+ addcycles000_3 ("");
+ out("}\n");
}
- addcycles000_nonces("\t", "2 * ccnt");
+ addcycles000_nonces("", "2 * ccnt");
count_cycles += c;
count_ncycles++;
}
static void bsetcycles (struct instr *curi)
{
if (curi->size == sz_byte) {
- out("\tsrc &= 7;\n");
+ out("src &= 7;\n");
} else {
- out("\tsrc &= 31;\n");
+ out("src &= 31;\n");
if (isreg (curi->dmode)) {
addcycles000 (2);
if (curi->mnemo != i_BTST) {
if (using_ce)
- out("\tif (src > 15) %s(2);\n", do_cycles);
- addcycles000_nonce("\tif (src > 15) ", 2);
+ out("if (src > 15) %s(2);\n", do_cycles);
+ addcycles000_nonce("if (src > 15) ", 2);
count_ncycles++;
}
}
// do not unnecessarily create useless mmuop030
// functions when CPU is not 68030
if (curi->mnemo == i_MMUOP030 && cpu_level != 3 && !cpu_generic) {
- out("\top_illg(opcode);\n");
+ out("op_illg(opcode);\n");
did_prefetch = -1;
goto end;
}
/* fall through */
case 2: /* priviledged */
out(
- "\tif (!regs.s) {\n"
- "\t\tException(8);\n");
- write_return_cycles("\t\t", -1);
- out("\t}\n");
+ "if (!regs.s) {\n"
+ "Exception(8);\n");
+ write_return_cycles("", -1);
+ out("}\n");
break;
case 3: /* privileged if size == word */
if (curi->size == sz_byte)
break;
out(
- "\tif (!regs.s) {\n"
- "\t\tException(8);\n");
- write_return_cycles("\t\t", -1);
- out("\t}\n");
+ "if (!regs.s) {\n"
+ "Exception(8);\n");
+ write_return_cycles("", -1);
+ out("}\n");
break;
}
switch (curi->mnemo) {
genamodedual(curi,
curi->smode, "srcreg", curi->size, "src", 1, 0,
curi->dmode, "dstreg", curi->size, "dst", 1, GF_RMW);
- out("\tsrc %c= dst;\n", curi->mnemo == i_OR ? '|' : curi->mnemo == i_AND ? '&' : '^');
+ out("src %c= dst;\n", curi->mnemo == i_OR ? '|' : curi->mnemo == i_AND ? '&' : '^');
genflags(flag_logical, curi->size, "src", "", "");
if (curi->size == sz_long) {
if (curi->dmode == Dreg) {
if (cpu_level == 1 && curi->smode == immi) {
c += 2;
}
- fill_prefetch_next_after(1, "\t\tccr_68000_long_move_ae_LZN(src);\n\t\tdreg_68000_long_replace_low(dstreg, src);\n");
+ fill_prefetch_next_after(1, "ccr_68000_long_move_ae_LZN(src);\ndreg_68000_long_replace_low(dstreg, src);\n");
} else {
- fill_prefetch_next_after(1, "\t\tdreg_68000_long_replace_low(dstreg, src);\n");
+ fill_prefetch_next_after(1, "dreg_68000_long_replace_low(dstreg, src);\n");
}
loopmodeextra = 4;
} else {
- fill_prefetch_next_after(0, "\t\tccr_68000_long_move_ae_LZN(src);\n");
+ fill_prefetch_next_after(0, "ccr_68000_long_move_ae_LZN(src);\n");
}
if (c > 0)
addcycles000(c);
case i_ANDSR:
case i_EORSR:
next_level_000();
- out("\tMakeSR();\n");
+ out("MakeSR();\n");
if (cpu_level == 0) {
- out("\tint t1 = regs.t1;\n");
+ out("int t1 = regs.t1;\n");
}
genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, cpu_level == 1 ? GF_NOREFILL : 0);
if (curi->size == sz_byte) {
- out("\tsrc &= 0xFF;\n");
+ out("src &= 0xFF;\n");
if (curi->mnemo == i_ANDSR)
- out("\tsrc |= 0xff00;\n");
+ out("src |= 0xff00;\n");
} else {
check_trace();
}
addcycles000(8);
- out("\tregs.sr %c= src;\n", curi->mnemo == i_ORSR ? '|' : curi->mnemo == i_ANDSR ? '&' : '^');
+ out("regs.sr %c= src;\n", curi->mnemo == i_ORSR ? '|' : curi->mnemo == i_ANDSR ? '&' : '^');
makefromsr_t0();
sync_m68k_pc();
fill_prefetch_full_ntx(3);
c += 2;
}
fill_prefetch_next_after(1,
- "\t\tuae_s16 bnewv = (uae_s16)dst - (uae_s16)src;\n"
- "\t\tint bflgs = ((uae_s16)(src)) < 0;\n"
- "\t\tint bflgo = ((uae_s16)(dst)) < 0;\n"
- "\t\tint bflgn = bnewv < 0;\n"
- "\t\tccr_68000_long_move_ae_LZN(bnewv);\n"
- "\t\tSET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));\n"
- "\t\tSET_XFLG(GET_CFLG());\n"
- "\t\tSET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));\n"
- "\t\tdreg_68000_long_replace_low(dstreg, bnewv);\n");
+ "uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;\n"
+ "int bflgs = ((uae_s16)(src)) < 0;\n"
+ "int bflgo = ((uae_s16)(dst)) < 0;\n"
+ "int bflgn = bnewv < 0;\n"
+ "ccr_68000_long_move_ae_LZN(bnewv);\n"
+ "SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));\n"
+ "SET_XFLG(GET_CFLG());\n"
+ "SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));\n"
+ "dreg_68000_long_replace_low(dstreg, bnewv);\n");
} else {
- fill_prefetch_next_after(1, "\t\tdreg_68000_long_replace_low(dstreg, newv);\n");
+ fill_prefetch_next_after(1, "dreg_68000_long_replace_low(dstreg, newv);\n");
}
loopmodeextra = 4;
} else {
fill_prefetch_next_after(0,
- "\t\tuae_s16 bnewv = (uae_s16)dst - (uae_s16)src;\n"
- "\t\tint bflgs = ((uae_s16)(src)) < 0;\n"
- "\t\tint bflgo = ((uae_s16)(dst)) < 0;\n"
- "\t\tint bflgn = bnewv < 0;\n"
- "\t\tccr_68000_long_move_ae_LZN(bnewv);\n"
- "\t\tSET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));\n"
- "\t\tSET_XFLG(GET_CFLG());\n"
- "\t\tSET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));\n");
+ "uae_s16 bnewv = (uae_s16)dst - (uae_s16)src;\n"
+ "int bflgs = ((uae_s16)(src)) < 0;\n"
+ "int bflgo = ((uae_s16)(dst)) < 0;\n"
+ "int bflgn = bnewv < 0;\n"
+ "ccr_68000_long_move_ae_LZN(bnewv);\n"
+ "SET_CFLG(((uae_u16)(src)) > ((uae_u16)(dst)));\n"
+ "SET_XFLG(GET_CFLG());\n"
+ "SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));\n");
}
if (c > 0)
addcycles000(c);
genamodedual (curi,
curi->smode, "srcreg", curi->size, "src", 1, 0,
curi->dmode, "dstreg", sz_long, "dst", 1, GF_RMW);
- out("\tuae_u32 newv = dst - src;\n");
+ out("uae_u32 newv = dst - src;\n");
if (curi->smode == immi) {
// SUBAQ.x is always 8 cycles
c += 4;
}
loopmodeextra = curi->size == sz_long ? 4 : 2;
}
- fill_prefetch_next_after(0, "\t\tareg_68000_long_replace_low(dstreg, newv);\n");
+ fill_prefetch_next_after(0, "areg_68000_long_replace_low(dstreg, newv);\n");
if (c > 0) {
addcycles000(c);
}
addcycles000 (2);
genamode(curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA | GF_REVERSE);
genamode(curi, curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_AA | GF_REVERSE | GF_RMW | GF_SECONDEA);
- out("\tuae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);\n");
+ out("uae_u32 newv = dst - src - (GET_XFLG() ? 1 : 0);\n");
if (cpu_level >= 2) {
genflags(flag_subx, curi->size, "newv", "src", "dst");
genflags(flag_zn, curi->size, "newv", "", "");
if (curi->size == sz_long) {
// set CCR using only low word if prefetch bus error
fill_prefetch_next_after(1,
- "\t\tint bflgs = ((uae_s16)(src)) < 0;\n"
- "\t\tint bflgo = ((uae_s16)(dst)) < 0;\n"
- "\t\tint bflgn = ((uae_s16)(newv)) < 0;\n"
- "\t\tSET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));\n"
- "\t\tSET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));\n"
- "\t\tSET_XFLG(GET_CFLG());\n"
- "\t\tif (newv & 0xffff) SET_ZFLG(0);\n"
- "\t\tSET_NFLG(newv & 0x8000); \n"
- "\t\tdreg_68000_long_replace_low(dstreg, newv);\n");
+ "int bflgs = ((uae_s16)(src)) < 0;\n"
+ "int bflgo = ((uae_s16)(dst)) < 0;\n"
+ "int bflgn = ((uae_s16)(newv)) < 0;\n"
+ "SET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));\n"
+ "SET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));\n"
+ "SET_XFLG(GET_CFLG());\n"
+ "if (newv & 0xffff) SET_ZFLG(0);\n"
+ "SET_NFLG(newv & 0x8000); \n"
+ "dreg_68000_long_replace_low(dstreg, newv);\n");
} else {
fill_prefetch_next_t();
}
addcycles000 (2);
genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_AA | GF_RMW);
- out("\tuae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG () ? 1 : 0);\n");
- out("\tuae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);\n");
- out("\tuae_u16 newv, tmp_newv;\n");
- out("\tint bcd = 0;\n");
- out("\tnewv = tmp_newv = newv_hi + newv_lo;\n");
- out("\tif (newv_lo & 0xF0) { newv -= 6; bcd = 6; };\n");
- out("\tif ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG () ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }\n");
- out("\tSET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG () ? 1 : 0)) & 0x300) > 0xFF);\n");
+ out("uae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG () ? 1 : 0);\n");
+ out("uae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);\n");
+ out("uae_u16 newv, tmp_newv;\n");
+ out("int bcd = 0;\n");
+ out("newv = tmp_newv = newv_hi + newv_lo;\n");
+ out("if (newv_lo & 0xF0) { newv -= 6; bcd = 6; };\n");
+ out("if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG () ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }\n");
+ out("SET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG () ? 1 : 0)) & 0x300) > 0xFF);\n");
duplicate_carry (0);
/* Manual says bits NV are undefined though a real 68030 doesn't change V and 68040/060 don't change both */
if (cpu_level >= xBCD_KEEPS_N_FLAG) {
if (next_cpu_level < xBCD_KEEPS_V_FLAG)
next_cpu_level = xBCD_KEEPS_V_FLAG - 1;
if (cpu_level >= xBCD_KEEPS_V_FLAG && cpu_level < xBCD_KEEPS_N_FLAG)
- out("\tSET_VFLG(0);\n");
+ out("SET_VFLG(0);\n");
} else {
- out("\tSET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);\n");
+ out("SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);\n");
}
fill_prefetch_next_after(1, NULL);
if (isreg (curi->smode)) {
c += 2;
}
fill_prefetch_next_after(1,
- "\t\tuae_s16 bnewv = (uae_s16)dst + (uae_s16)src;\n"
- "\t\tint bflgs = ((uae_s16)(src)) < 0;\n"
- "\t\tint bflgo = ((uae_s16)(dst)) < 0;\n"
- "\t\tint bflgn = bnewv < 0;\n"
- "\t\tccr_68000_long_move_ae_LZN(bnewv);\n"
- "\t\tSET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));\n"
- "\t\tSET_XFLG(GET_CFLG());\n"
- "\t\tSET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));\n"
- "\t\tdreg_68000_long_replace_low(dstreg, bnewv);\n");
+ "uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;\n"
+ "int bflgs = ((uae_s16)(src)) < 0;\n"
+ "int bflgo = ((uae_s16)(dst)) < 0;\n"
+ "int bflgn = bnewv < 0;\n"
+ "ccr_68000_long_move_ae_LZN(bnewv);\n"
+ "SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));\n"
+ "SET_XFLG(GET_CFLG());\n"
+ "SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));\n"
+ "dreg_68000_long_replace_low(dstreg, bnewv);\n");
} else {
- fill_prefetch_next_after(1, "\t\tdreg_68000_long_replace_low(dstreg, newv);\n");
+ fill_prefetch_next_after(1, "dreg_68000_long_replace_low(dstreg, newv);\n");
}
loopmodeextra = 4;
} else {
fill_prefetch_next_after(0,
- "\t\tuae_s16 bnewv = (uae_s16)dst + (uae_s16)src;\n"
- "\t\tint bflgs = ((uae_s16)(src)) < 0;\n"
- "\t\tint bflgo = ((uae_s16)(dst)) < 0;\n"
- "\t\tint bflgn = bnewv < 0;\n"
- "\t\tccr_68000_long_move_ae_LZN(bnewv);\n"
- "\t\tSET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));\n"
- "\t\tSET_XFLG(GET_CFLG());\n"
- "\t\tSET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));\n");
+ "uae_s16 bnewv = (uae_s16)dst + (uae_s16)src;\n"
+ "int bflgs = ((uae_s16)(src)) < 0;\n"
+ "int bflgo = ((uae_s16)(dst)) < 0;\n"
+ "int bflgn = bnewv < 0;\n"
+ "ccr_68000_long_move_ae_LZN(bnewv);\n"
+ "SET_CFLG(((uae_u16)(~dst)) < ((uae_u16)(src)));\n"
+ "SET_XFLG(GET_CFLG());\n"
+ "SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));\n");
}
if (c > 0)
addcycles000(c);
genamodedual (curi,
curi->smode, "srcreg", curi->size, "src", 1, 0,
curi->dmode, "dstreg", sz_long, "dst", 1, GF_RMW);
- out("\tuae_u32 newv = dst + src;\n");
+ out("uae_u32 newv = dst + src;\n");
if (curi->smode == immi) {
// ADDAQ.x is always 8 cycles
c += 4;
}
loopmodeextra = curi->size == sz_long ? 4 : 2;
}
- fill_prefetch_next_after(1, "\t\tareg_68000_long_replace_low(dstreg, newv);\n");
+ fill_prefetch_next_after(1, "areg_68000_long_replace_low(dstreg, newv);\n");
if (c > 0) {
addcycles000(c);
}
}
genamode(curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA | GF_REVERSE);
genamode(curi, curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_AA | GF_REVERSE | GF_RMW | GF_SECONDEA);
- out("\tuae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);\n");
+ out("uae_u32 newv = dst + src + (GET_XFLG() ? 1 : 0);\n");
if (cpu_level >= 2) {
genflags(flag_addx, curi->size, "newv", "src", "dst");
genflags(flag_zn, curi->size, "newv", "", "");
if (curi->size == sz_long) {
// set CCR using only low word if prefetch bus error
fill_prefetch_next_after(1,
- "\t\tint bflgs = ((uae_s16)(src)) < 0;\n"
- "\t\tint bflgo = ((uae_s16)(dst)) < 0;\n"
- "\t\tint bflgn = ((uae_s16)(newv)) < 0;\n"
- "\t\tSET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));\n"
- "\t\tSET_CFLG(bflgs ^ ((bflgs ^ bflgo) & (bflgo ^ bflgn)));\n"
- "\t\tSET_XFLG(GET_CFLG());\n"
- "\t\tif (newv & 0xffff) SET_ZFLG(0);\n"
- "\t\tSET_NFLG(newv & 0x8000); \n"
- "\t\tdreg_68000_long_replace_low(dstreg, newv);\n");
+ "int bflgs = ((uae_s16)(src)) < 0;\n"
+ "int bflgo = ((uae_s16)(dst)) < 0;\n"
+ "int bflgn = ((uae_s16)(newv)) < 0;\n"
+ "SET_VFLG((bflgs ^ bflgn) & (bflgo ^ bflgn));\n"
+ "SET_CFLG(bflgs ^ ((bflgs ^ bflgo) & (bflgo ^ bflgn)));\n"
+ "SET_XFLG(GET_CFLG());\n"
+ "if (newv & 0xffff) SET_ZFLG(0);\n"
+ "SET_NFLG(newv & 0x8000); \n"
+ "dreg_68000_long_replace_low(dstreg, newv);\n");
} else {
fill_prefetch_next_t();
}
addcycles000 (2);
genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA);
genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_AA | GF_RMW);
- out("\tuae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG () ? 1 : 0);\n");
- out("\tuae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);\n");
- out("\tuae_u16 newv, tmp_newv;\n");
- out("\tint cflg;\n");
- out("\tnewv = tmp_newv = newv_hi + newv_lo;");
- out("\tif (newv_lo > 9) { newv += 6; }\n");
- out("\tcflg = (newv & 0x3F0) > 0x90;\n");
- out("\tif (cflg) newv += 0x60;\n");
- out("\tSET_CFLG (cflg);\n");
+ out("uae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG () ? 1 : 0);\n");
+ out("uae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);\n");
+ out("uae_u16 newv, tmp_newv;\n");
+ out("int cflg;\n");
+ out("newv = tmp_newv = newv_hi + newv_lo;");
+ out("if (newv_lo > 9) { newv += 6; }\n");
+ out("cflg = (newv & 0x3F0) > 0x90;\n");
+ out("if (cflg) newv += 0x60;\n");
+ out("SET_CFLG (cflg);\n");
duplicate_carry (0);
/* Manual says bits NV are undefined though a real 68030 clears V and 68040/060 don't change both */
if (cpu_level >= xBCD_KEEPS_N_FLAG) {
if (next_cpu_level < xBCD_KEEPS_V_FLAG)
next_cpu_level = xBCD_KEEPS_V_FLAG - 1;
if (cpu_level >= xBCD_KEEPS_V_FLAG && cpu_level < xBCD_KEEPS_N_FLAG)
- out("\tSET_VFLG(0);\n");
+ out("SET_VFLG(0);\n");
} else {
- out("\tSET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);\n");
+ out("SET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);\n");
}
fill_prefetch_next_after(1, NULL);
if (isreg (curi->smode)) {
// prefetch bus error and long register: only low word is updated
// N flag from high word. Z both.
fill_prefetch_next_after(1,
- "\t\tdreg_68000_long_replace_low(srcreg, dst);\n"
- "\t\tint bflgs = ((uae_s16)(src)) < 0;\n"
- "\t\tint bflgo = ((uae_s16)(0)) < 0;\n"
- "\t\tint bflgn = ((uae_s16)(dst)) < 0;\n"
- "\t\tSET_ZFLG(((uae_s16)(dst)) == 0);\n"
- "\t\tSET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));\n"
- "\t\tSET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));\n"
- "\t\tSET_NFLG(dst & 0x80000000);\n"
- "\t\tSET_XFLG(GET_CFLG());\n");
+ "dreg_68000_long_replace_low(srcreg, dst);\n"
+ "int bflgs = ((uae_s16)(src)) < 0;\n"
+ "int bflgo = ((uae_s16)(0)) < 0;\n"
+ "int bflgn = ((uae_s16)(dst)) < 0;\n"
+ "SET_ZFLG(((uae_s16)(dst)) == 0);\n"
+ "SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));\n"
+ "SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));\n"
+ "SET_NFLG(dst & 0x80000000);\n"
+ "SET_XFLG(GET_CFLG());\n");
genastore_rev("dst", curi->smode, "srcreg", curi->size, "src");
} else {
genastore_rev("dst", curi->smode, "srcreg", curi->size, "src");
} else if (curi->size == sz_long) {
// prefetch bus error and long memory: only low word CCR decoded
fill_prefetch_next_after(0,
- "\t\tint bflgs = ((uae_s16)(src)) < 0;\n"
- "\t\tint bflgo = ((uae_s16)(0)) < 0;\n"
- "\t\tint bflgn = ((uae_s16)(dst)) < 0;\n"
- "\t\tSET_ZFLG(((uae_s16)(dst)) == 0);\n"
- "\t\tSET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));\n"
- "\t\tSET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));\n"
- "\t\tSET_NFLG(bflgn != 0);\n"
- "\t\tSET_XFLG(GET_CFLG());\n");
+ "int bflgs = ((uae_s16)(src)) < 0;\n"
+ "int bflgo = ((uae_s16)(0)) < 0;\n"
+ "int bflgn = ((uae_s16)(dst)) < 0;\n"
+ "SET_ZFLG(((uae_s16)(dst)) == 0);\n"
+ "SET_VFLG((bflgs ^ bflgo) & (bflgn ^ bflgo));\n"
+ "SET_CFLG(((uae_u16)(src)) > ((uae_u16)(0)));\n"
+ "SET_NFLG(bflgn != 0);\n"
+ "SET_XFLG(GET_CFLG());\n");
} else {
fill_prefetch_next_after(1, NULL);
}
break;
case i_NEGX:
genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_RMW);
- out("\tuae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);\n");
+ out("uae_u32 newv = 0 - src - (GET_XFLG () ? 1 : 0);\n");
genflags(flag_subx, curi->size, "newv", "src", "0");
genflags(flag_zn, curi->size, "newv", "", "");
if (curi->smode == Dreg) {
// prefetch bus error and long register: only low word is updated
// N flag from high word. Z both.
fill_prefetch_next_after(1,
- "\t\tdreg_68000_long_replace_low(srcreg, newv);\n"
- "\t\tint bflgs = ((uae_s16)(src)) < 0;\n"
- "\t\tint bflgo = ((uae_s16)(0)) < 0;\n"
- "\t\tint bflgn = ((uae_s16)(newv)) < 0;\n"
- "\t\tSET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));\n"
- "\t\tSET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));\n"
- "\t\tSET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));\n"
- "\t\tSET_NFLG(((uae_s32)(newv)) < 0);\n"
- "\t\tSET_XFLG(GET_CFLG());\n");
+ "dreg_68000_long_replace_low(srcreg, newv);\n"
+ "int bflgs = ((uae_s16)(src)) < 0;\n"
+ "int bflgo = ((uae_s16)(0)) < 0;\n"
+ "int bflgn = ((uae_s16)(newv)) < 0;\n"
+ "SET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));\n"
+ "SET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));\n"
+ "SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));\n"
+ "SET_NFLG(((uae_s32)(newv)) < 0);\n"
+ "SET_XFLG(GET_CFLG());\n");
genastore_rev("newv", curi->smode, "srcreg", curi->size, "src");
} else {
genastore_rev("newv", curi->smode, "srcreg", curi->size, "src");
} else if (curi->size == sz_long) {
// prefetch bus error and long memory: only low word CCR decoded
fill_prefetch_next_after(0,
- "\t\tint bflgs = ((uae_s16)(src)) < 0;\n"
- "\t\tint bflgo = ((uae_s16)(0)) < 0;\n"
- "\t\tint bflgn = ((uae_s16)(newv)) < 0;\n"
- "\t\tSET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));\n"
- "\t\tSET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));\n"
- "\t\tSET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));\n"
- "\t\tSET_NFLG(((uae_s16)(newv)) < 0);\n"
- "\t\tSET_XFLG(GET_CFLG());\n");
+ "int bflgs = ((uae_s16)(src)) < 0;\n"
+ "int bflgo = ((uae_s16)(0)) < 0;\n"
+ "int bflgn = ((uae_s16)(newv)) < 0;\n"
+ "SET_VFLG((bflgs ^ bflgo) & (bflgo ^ bflgn));\n"
+ "SET_CFLG(bflgs ^ ((bflgs ^ bflgn) & (bflgo ^ bflgn)));\n"
+ "SET_ZFLG(GET_ZFLG() & (((uae_s16)(newv)) == 0));\n"
+ "SET_NFLG(((uae_s16)(newv)) < 0);\n"
+ "SET_XFLG(GET_CFLG());\n");
} else {
fill_prefetch_next_after(1, NULL);
}
genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_RMW);
if (isreg (curi->smode))
addcycles000 (2);
- out("\tuae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);\n");
- out("\tuae_u16 newv_hi = - (src & 0xF0);\n");
- out("\tuae_u16 newv;\n");
- out("\tint cflg, tmp_newv;\n");
- out("\ttmp_newv = newv_hi + newv_lo;\n");
- out("\tif (newv_lo > 9) { newv_lo -= 6; }\n");
- out("\tnewv = newv_hi + newv_lo;\n");
- out("\tcflg = (newv & 0x1F0) > 0x90;\n");
- out("\tif (cflg) newv -= 0x60;\n");
- out("\tSET_CFLG (cflg);\n");
+ out("uae_u16 newv_lo = - (src & 0xF) - (GET_XFLG () ? 1 : 0);\n");
+ out("uae_u16 newv_hi = - (src & 0xF0);\n");
+ out("uae_u16 newv;\n");
+ out("int cflg, tmp_newv;\n");
+ out("tmp_newv = newv_hi + newv_lo;\n");
+ out("if (newv_lo > 9) { newv_lo -= 6; }\n");
+ out("newv = newv_hi + newv_lo;\n");
+ out("cflg = (newv & 0x1F0) > 0x90;\n");
+ out("if (cflg) newv -= 0x60;\n");
+ out("SET_CFLG (cflg);\n");
duplicate_carry(0);
/* Manual says bits NV are undefined though a real 68030 doesn't change V and 68040/060 don't change both */
if (cpu_level >= xBCD_KEEPS_N_FLAG) {
if (next_cpu_level < xBCD_KEEPS_V_FLAG)
next_cpu_level = xBCD_KEEPS_V_FLAG - 1;
if (cpu_level >= xBCD_KEEPS_V_FLAG && cpu_level < xBCD_KEEPS_N_FLAG)
- out("\tSET_VFLG(0);\n");
+ out("SET_VFLG(0);\n");
} else {
- out("\tSET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);\n");
+ out("SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);\n");
}
fill_prefetch_next_after(1, NULL);
genastore ("newv", curi->smode, "srcreg", curi->size, "src");
// prefetch bus error and long register: only low word is updated
// N flag from high word. Z both.
fill_prefetch_next_after(1,
- "\t\tm68k_dreg(regs, srcreg) = (src & 0xffff0000);\n"
- "\t\tSET_VFLG(0);SET_ZFLG(1);SET_NFLG(0);SET_CFLG(0);\n");
+ "m68k_dreg(regs, srcreg) = (src & 0xffff0000);\n"
+ "SET_VFLG(0);SET_ZFLG(1);SET_NFLG(0);SET_CFLG(0);\n");
genastore_rev("0", curi->smode, "srcreg", curi->size, "src");
} else {
genastore_rev("0", curi->smode, "srcreg", curi->size, "src");
}
} else if (curi->size == sz_long) {
// prefetch bus error and long memory: only low word CCR decoded
- fill_prefetch_next_after(0, "\t\tSET_VFLG(0);SET_ZFLG(1);SET_NFLG(0);SET_CFLG(0);\n");
+ fill_prefetch_next_after(0, "SET_VFLG(0);SET_ZFLG(1);SET_NFLG(0);SET_CFLG(0);\n");
} else {
fill_prefetch_next_after(1, NULL);
}
addcycles000(2);
}
if (!isreg(curi->smode) && using_exception_3 && curi->size != sz_byte && (using_prefetch || using_ce)) {
- out("\tif(srca & 1) {\n");
+ out("if(srca & 1) {\n");
if (curi->size == sz_word) {
if (curi->smode == Aipi) {
- out("\t\tm68k_areg(regs, srcreg) -= 2;\n");
+ out("m68k_areg(regs, srcreg) -= 2;\n");
} else if (curi->smode == Apdi) {
- out("\t\tm68k_areg(regs, srcreg) += 2;\n");
+ out("m68k_areg(regs, srcreg) += 2;\n");
} else if (curi->smode >= Ad16) {
- out("\t%s(%d);\n", prefetch_word, m68k_pc_offset + 2);
+ out("%s(%d);\n", prefetch_word, m68k_pc_offset + 2);
genflags(flag_logical, curi->size, "0", "", "");
}
} else {
if (curi->smode == Aipi) {
- out("\t\tm68k_areg(regs, srcreg) -= 4;\n");
+ out("m68k_areg(regs, srcreg) -= 4;\n");
} else if (curi->smode == Apdi) {
- out("\t\tm68k_areg(regs, srcreg) += 4;\n");
- out("\t\tsrca += 2;\n");
+ out("m68k_areg(regs, srcreg) += 4;\n");
+ out("srca += 2;\n");
} else if (curi->smode >= Ad16) {
- out("\t\tsrca += 2;\n");
- out("\t%s(%d);\n", prefetch_word, m68k_pc_offset + 2);
+ out("srca += 2;\n");
+ out("%s(%d);\n", prefetch_word, m68k_pc_offset + 2);
genflags(flag_logical, curi->size, "0", "", "");
}
}
- out("\t\texception3_write(opcode, srca, 1, 0, 1);\n");
- write_return_cycles("\t\t", 0);
- out("\t}\n");
+ out("exception3_write(opcode, srca, 1, 0, 1);\n");
+ write_return_cycles("", 0);
+ out("}\n");
}
fill_prefetch_next();
genflags(flag_logical, curi->size, "0", "", "");
break;
case i_NOT:
genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_RMW);
- out("\tuae_u32 dst = ~src;\n");
+ out("uae_u32 dst = ~src;\n");
genflags(flag_logical, curi->size, "dst", "", "");
if (curi->smode == Dreg) {
if (curi->size == sz_long) {
// prefetch bus error and long register: only low word is updated
// N flag from high word. Z both.
fill_prefetch_next_after(1,
- "\t\tdreg_68000_long_replace_low(srcreg, dst);\n"
- "\t\tSET_VFLG(0);SET_ZFLG(!dst);\n"
- "\t\tSET_NFLG(dst & 0x80000000);\n"
- "\t\tSET_CFLG(0);\n");
+ "dreg_68000_long_replace_low(srcreg, dst);\n"
+ "SET_VFLG(0);SET_ZFLG(!dst);\n"
+ "SET_NFLG(dst & 0x80000000);\n"
+ "SET_CFLG(0);\n");
genastore_rev("dst", curi->smode, "srcreg", curi->size, "src");
} else {
genastore_rev("dst", curi->smode, "srcreg", curi->size, "src");
} else if (curi->size == sz_long) {
// prefetch bus error and long memory: only low word CCR decoded
fill_prefetch_next_after(0,
- "\t\tSET_VFLG(0);\n"
- "\t\tSET_ZFLG(!(dst & 0xffff));\n"
- "\t\tSET_NFLG(dst & 0x8000);\n"
- "\t\tSET_CFLG(0);\n");
+ "SET_VFLG(0);\n"
+ "SET_ZFLG(!(dst & 0xffff));\n"
+ "SET_NFLG(dst & 0x8000);\n"
+ "SET_CFLG(0);\n");
} else {
fill_prefetch_next_after(1, NULL);
}
if (curi->size == sz_long) {
fill_prefetch_next_after(1, NULL);
bsetcycles(curi);
- out("\tSET_ZFLG(1 ^ ((dst >> src) & 1));\n");
+ out("SET_ZFLG(1 ^ ((dst >> src) & 1));\n");
} else {
bsetcycles(curi);
if (curi->dmode == imm) {
// btst dn,#x
addcycles000(2);
fill_prefetch_next_after(1, NULL);
- out("\tSET_ZFLG(1 ^ ((dst >> src) & 1));\n");
+ out("SET_ZFLG(1 ^ ((dst >> src) & 1));\n");
} else {
- out("\tSET_ZFLG(1 ^ ((dst >> src) & 1));\n");
+ out("SET_ZFLG(1 ^ ((dst >> src) & 1));\n");
fill_prefetch_next_t();
}
}
next_level_000();
}
if (curi->mnemo == i_BCHG) {
- out("\tdst ^= (1 << src);\n");
- out("\tSET_ZFLG(((uae_u32)dst & (1 << src)) >> src);\n");
+ out("dst ^= (1 << src);\n");
+ out("SET_ZFLG(((uae_u32)dst & (1 << src)) >> src);\n");
} else if (curi->mnemo == i_BCLR) {
- out("\tSET_ZFLG(1 ^ ((dst >> src) & 1));\n");
- out("\tdst &= ~(1 << src);\n");
+ out("SET_ZFLG(1 ^ ((dst >> src) & 1));\n");
+ out("dst &= ~(1 << src);\n");
} else if (curi->mnemo == i_BSET) {
- out("\tSET_ZFLG(1 ^ ((dst >> src) & 1));\n");
- out("\tdst |= (1 << src);\n");
+ out("SET_ZFLG(1 ^ ((dst >> src) & 1));\n");
+ out("dst |= (1 << src);\n");
}
if (curi->size != sz_long) {
if (curi->smode < imm && curi->smode != Dreg) {
* weird things... */
case i_MVPRM: // MOVEP R->M
genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, cpu_level == 1 ? GF_NOFETCH : 0);
- out("\tuaecptr mempa = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)%s;\n", gen_nextiword (0));
+ out("uaecptr mempa = m68k_areg(regs, dstreg) + (uae_s32)(uae_s16)%s;\n", gen_nextiword (0));
check_prefetch_buserror(m68k_pc_offset);
if (curi->size == sz_word) {
- out("\t%s(mempa, src >> 8);\n", dstb);
+ out("%s(mempa, src >> 8);\n", dstb);
count_write++;
check_bus_error("memp", 0, 1, 0, "src >> 8", 1 | 0x10000);
- out("\t%s(mempa + 2, src); \n", dstb);
+ out("%s(mempa + 2, src); \n", dstb);
count_write++;
check_bus_error("memp", 2, 1, 0, "src", 1);
} else {
- out("\t%s(mempa, src >> 24);\n", dstb);
+ out("%s(mempa, src >> 24);\n", dstb);
count_write++;
check_bus_error("memp", 0, 1, 0, "src >> 24", 1 | 0x10000);
- out("\t%s(mempa + 2, src >> 16);\n", dstb);
+ out("%s(mempa + 2, src >> 16);\n", dstb);
count_write++;
check_bus_error("memp", 2, 1, 0, "src >> 16", 1);
- out("\t%s(mempa + 4, src >> 8);\n", dstb);
+ out("%s(mempa + 4, src >> 8);\n", dstb);
count_write++;
check_bus_error("memp", 4, 1, 0, "src >> 8", 1 | 0x10000);
- out("\t%s(mempa + 6, src); \n", dstb);
+ out("%s(mempa + 6, src); \n", dstb);
count_write++;
check_bus_error("memp", 6, 1, 0, "src", 1);
}
fill_prefetch_next_t();
break;
case i_MVPMR: // MOVEP M->R
- out("\tuaecptr mempa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)%s;\n", gen_nextiword (0));
+ out("uaecptr mempa = m68k_areg(regs, srcreg) + (uae_s32)(uae_s16)%s;\n", gen_nextiword (0));
check_prefetch_buserror(m68k_pc_offset);
genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 2, 0, cpu_level == 1 ? GF_NOFETCH : 0);
if (curi->size == sz_word) {
- out("\tuae_u16 val = (%s(mempa) & 0xff) << 8;\n", srcb);
+ out("uae_u16 val = (%s(mempa) & 0xff) << 8;\n", srcb);
count_read++;
check_bus_error("memp", 0, 0, 0, NULL, 1 | 0x10000);
- out("\tval |= (%s(mempa + 2) & 0xff);\n", srcb);
+ out("val |= (%s(mempa + 2) & 0xff);\n", srcb);
count_read++;
check_bus_error("memp", 2, 0, 0, NULL, 1);
} else {
- out("\tuae_u32 val = (%s(mempa) & 0xff) << 24;\n", srcb);
+ out("uae_u32 val = (%s(mempa) & 0xff) << 24;\n", srcb);
count_read++;
check_bus_error("memp", 0, 0, 0, NULL, 1 | 0x10000);
- out("\tval |= (%s(mempa + 2) & 0xff) << 16;\n", srcb);
+ out("val |= (%s(mempa + 2) & 0xff) << 16;\n", srcb);
count_read++;
check_bus_error("memp", 2, 0, 0, NULL, 1);
// upper word gets updated after two bytes (makes only difference if bus error is possible)
if (cpu_level <= 1) {
- out("\tm68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & 0x0000ffff) | val;\n");
+ out("m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & 0x0000ffff) | val;\n");
}
- out("\tval |= (%s(mempa + 4) & 0xff) << 8;\n", srcb);
+ out("val |= (%s(mempa + 4) & 0xff) << 8;\n", srcb);
count_read++;
check_bus_error("memp", 4, 0, 0, NULL, 1 | 0x10000);
- out("\tval |= (%s(mempa + 6) & 0xff);\n", srcb);
+ out("val |= (%s(mempa + 6) & 0xff);\n", srcb);
count_read++;
check_bus_error("memp", 6, 0, 0, NULL, 1);
}
genamode2 (curi->dmode, "dstreg", curi->size, "dst", 2, 0, GF_MOVE);
addopcycles_ce20 (h, t, c, -subhead, 0);
if (curi->mnemo == i_MOVEA && curi->size == sz_word)
- out("\tsrc = (uae_s32)(uae_s16)src;\n");
+ out("src = (uae_s32)(uae_s16)src;\n");
if (curi->mnemo == i_MOVE)
genflags (flag_logical, curi->size, "src", "", "");
genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
if (curi->size == sz_long) {
if (curi->smode == imm) {
if (curi->dmode == absw) {
- strcpy(bus_error_code, "\t\tccr_68000_long_move_ae_LZN(src);\n");
+ strcpy(bus_error_code, "ccr_68000_long_move_ae_LZN(src);\n");
} else if (curi->dmode == absl) {
- strcpy(bus_error_code2, "\t\tccr_68000_long_move_ae_LZN(src);\n");
+ strcpy(bus_error_code2, "ccr_68000_long_move_ae_LZN(src);\n");
}
} else if (curi->smode == Dreg || curi->smode == Areg) {
if (curi->dmode == absl) {
- strcpy(bus_error_code, "\t\t// nothing;\n");
- strcpy(bus_error_code2, "\t\tccr_68000_long_move_ae_LZN(src);\n");
+ strcpy(bus_error_code, "// nothing;\n");
+ strcpy(bus_error_code2, "ccr_68000_long_move_ae_LZN(src);\n");
} else if (curi->dmode == absw) {
- strcpy(bus_error_code, "\t\tccr_68000_long_move_ae_LZN(src);\n");
+ strcpy(bus_error_code, "ccr_68000_long_move_ae_LZN(src);\n");
}
} else {
if (curi->dmode == absl) {
- strcpy(bus_error_code, "\t\t// nothing;\n");
- strcpy(bus_error_code2, "\t\tccr_68000_long_move_ae_LZN(src);\n");
+ strcpy(bus_error_code, "// nothing;\n");
+ strcpy(bus_error_code2, "ccr_68000_long_move_ae_LZN(src);\n");
} else {
- strcpy(bus_error_code, "\t\tccr_68000_long_move_ae_LZN(src);\n");
+ strcpy(bus_error_code, "ccr_68000_long_move_ae_LZN(src);\n");
}
}
} else {
// if data prefetches needed for destination EA, CCR is set before fetch completes.
if (curi->smode == Areg || curi->smode == Dreg || curi->smode == imm) {
if (curi->dmode == absl) {
- strcpy(bus_error_code2, "\t\tccr_68000_word_move_ae_normal((uae_s16)src);\n");
+ strcpy(bus_error_code2, "ccr_68000_word_move_ae_normal((uae_s16)src);\n");
} else if (curi->dmode == absw) {
- strcpy(bus_error_code, "\t\tccr_68000_word_move_ae_normal((uae_s16)src);\n");
+ strcpy(bus_error_code, "ccr_68000_word_move_ae_normal((uae_s16)src);\n");
}
} else {
if (curi->dmode == Ad16 || curi->dmode == PC16 || curi->dmode == Ad8r || curi->dmode == PC8r || curi->dmode == absw || curi->dmode == absl) {
- strcpy(bus_error_code, "\t\tccr_68000_word_move_ae_normal((uae_s16)src);\n");
+ strcpy(bus_error_code, "ccr_68000_word_move_ae_normal((uae_s16)src);\n");
}
}
}
genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 2, 0, flags);
if (curi->mnemo == i_MOVEA && curi->size == sz_word)
- out("\tsrc = (uae_s32)(uae_s16)src;\n");
+ out("src = (uae_s32)(uae_s16)src;\n");
if (curi->dmode == Apdi) {
// -(an) decrease is not done if bus error
if (curi->size == sz_long) {
fill_prefetch_next_after(0,
- "\t\tm68k_areg(regs, dstreg) += 4;\n"
- "\t\tccr_68000_long_move_ae_LZN(src);\n"
+ "m68k_areg(regs, dstreg) += 4;\n"
+ "ccr_68000_long_move_ae_LZN(src);\n"
);
} else {
// x,-(an): flags are set before prefetch detects possible bus error
if (curi->mnemo == i_MOVE) {
fill_prefetch_next_after(1,
- "\t\tm68k_areg(regs, dstreg) += %s;\n"
- "\t\tccr_68000_word_move_ae_normal((uae_s16)src);\n",
+ "m68k_areg(regs, dstreg) += %s;\n"
+ "ccr_68000_word_move_ae_normal((uae_s16)src);\n",
curi->size == sz_byte ? "areg_byteinc[dstreg]" : "2");
} else {
fill_prefetch_next_after(1,
- "\t\tm68k_areg(regs, dstreg) += %s;\n",
+ "m68k_areg(regs, dstreg) += %s;\n",
curi->size == sz_byte ? "areg_byteinc[dstreg]" : "2");
}
}
genamode(curi, curi->dmode, "dstreg", curi->size, "dst", 2, 0, 0);
if (curi->mnemo == i_MOVEA) {
if (curi->size == sz_word)
- out("\tsrc = (uae_s32)(uae_s16)src;\n");
+ out("src = (uae_s32)(uae_s16)src;\n");
} else {
genflags(flag_logical, curi->size, "src", "", "");
}
case i_MVSR2: // MOVE FROM SR
next_level_000();
genamode (curi, curi->smode, "srcreg", sz_word, "src", cpu_level == 0 ? 2 : 3, 0, cpu_level == 1 ? GF_NOFETCH : 0);
- out("\tMakeSR();\n");
+ out("MakeSR();\n");
if (isreg (curi->smode)) {
if (cpu_level == 0 && curi->size == sz_word) {
fill_prefetch_next_after(1,
- "\t\tMakeSR();\n"
- "\t\tm68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((regs.sr) & 0xffff);\n");
+ "MakeSR();\n"
+ "m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((regs.sr) & 0xffff);\n");
} else {
fill_prefetch_next_after(1, NULL);
}
} else {
// 68000: read first and ignore result
if (cpu_level == 0 && curi->size == sz_word) {
- out("\t%s(srca);\n", srcw);
+ out("%s(srca);\n", srcw);
count_write++;
check_bus_error("src", 0, 0, 1, NULL, 1);
}
fill_prefetch_next_after(1, NULL);
}
if (!isreg(curi->smode) && cpu_level == 1 && using_exception_3 && (using_prefetch || using_ce)) {
- out("\tif(srca & 1) {\n");
- out("\t\texception3_write(opcode, srca, 1, regs.sr & 0x%x, 1);\n", curi->size == sz_byte ? 0x00ff : 0xffff);
- write_return_cycles("\t\t", 0);
- out("\t}\n");
+ out("if(srca & 1) {\n");
+ out("exception3_write(opcode, srca, 1, regs.sr & 0x%x, 1);\n", curi->size == sz_byte ? 0x00ff : 0xffff);
+ write_return_cycles("", 0);
+ out("}\n");
}
// real write
if (curi->size == sz_byte)
case i_MV2SR: // MOVE TO SR
genamode (curi, curi->smode, "srcreg", sz_word, "src", 1, 0, 0);
if (cpu_level == 0)
- out("\tint t1 = regs.t1;\n");
+ out("int t1 = regs.t1;\n");
if (curi->size == sz_byte) {
// MOVE TO CCR
addcycles000 (4);
- out("\tMakeSR();\n\tregs.sr &= 0xFF00;\n\tregs.sr |= src & 0xFF;\n");
+ out("MakeSR();\nregs.sr &= 0xFF00;\nregs.sr |= src & 0xFF;\n");
} else {
// MOVE TO SR
check_trace();
addcycles000 (4);
- out("\tregs.sr = src;\n");
+ out("regs.sr = src;\n");
}
makefromsr_t0();
// does full prefetch because S-bit change may change memory mapping under the CPU
break;
case i_SWAP:
genamode (curi, curi->smode, "srcreg", sz_long, "src", 1, 0, 0);
- out("\tuae_u32 dst = ((src >> 16)&0xFFFF) | ((src&0xFFFF)<<16);\n");
+ out("uae_u32 dst = ((src >> 16)&0xFFFF) | ((src&0xFFFF)<<16);\n");
if (cpu_level >= 2) {
genflags(flag_logical, sz_long, "dst", "", "");
genastore("dst", curi->smode, "srcreg", sz_long, "src");
// confirmed
genamode (curi, curi->smode, "srcreg", sz_long, "src", 1, 0, 0);
switch (curi->size) {
- case sz_byte: out("\tuae_u32 dst = (uae_s32)(uae_s8)src;\n"); break;
- case sz_word: out("\tuae_u16 dst = (uae_s16)(uae_s8)src;\n"); break;
- case sz_long: out("\tuae_u32 dst = (uae_s32)(uae_s16)src;\n"); break;
+ case sz_byte: out("uae_u32 dst = (uae_s32)(uae_s8)src;\n"); break;
+ case sz_word: out("uae_u16 dst = (uae_s16)(uae_s8)src;\n"); break;
+ case sz_long: out("uae_u32 dst = (uae_s32)(uae_s16)src;\n"); break;
default: term ();
}
if (curi->size != sz_word) {
genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
gen_set_fault_pc (false, true);
sync_m68k_pc ();
- out("\tException_cpu(src + 32);\n");
+ out("Exception_cpu(src + 32);\n");
did_prefetch = 1;
clear_m68k_offset();
break;
case i_MVR2USP:
next_level_000();
genamode(curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
- out("\tregs.usp = src;\n");
+ out("regs.usp = src;\n");
if (cpu_level == 1) {
addcycles000(2);
}
fill_prefetch_next_t();
break;
case i_RESET:
- out("\tcpureset();\n");
+ out("cpureset();\n");
addcycles000(128);
fill_prefetch_next_t();
break;
case i_STOP:
next_level_000();
if (using_prefetch) {
- out("\tuae_u16 sr = regs.irc;\n");
+ out("uae_u16 sr = regs.irc;\n");
m68k_pc_offset += 2;
} else {
genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
- out("\tuae_u16 sr = src;\n");
+ out("uae_u16 sr = src;\n");
}
// STOP undocumented features:
// if new SR S-bit is not set:
// 68020 68030 68040: STOP works normally
// 68060: Immediate privilege violation exception
if ((cpu_level == 0 || cpu_level == 1) && using_ce) {
- out("\t%s(regs.t1 ? 4 : 8);\n", do_cycles);
+ out("%s(regs.t1 ? 4 : 8);\n", do_cycles);
}
if (cpu_level >= 5) {
- out("\tif (!(sr & 0x2000)) {\n");
+ out("if (!(sr & 0x2000)) {\n");
incpc("%d", m68k_pc_offset);
- out("\t\tException(8);\n");
- write_return_cycles("\t\t", 0);
- out("\t}\n");
+ out("Exception(8);\n");
+ write_return_cycles("", 0);
+ out("}\n");
}
- out("\tregs.sr = sr;\n");
+ out("regs.sr = sr;\n");
makefromsr();
- out("\tm68k_setstopped ();\n");
+ out("m68k_setstopped ();\n");
sync_m68k_pc ();
// STOP does not prefetch anything
did_prefetch = -1;
next_cpu_level = cpu_level - 1;
break;
case i_LPSTOP: /* 68060 */
- out("\tuae_u16 sw = %s(2);\n", srcwi);
- out("\tif (sw != 0x01c0) {\n");
- out("\t\tException(11);\n");
- write_return_cycles("\t\t", 0);
- out("\t\t}\n");
- out("\tif (!(regs.sr & 0x2000)) {\n");
- out("\t\tException(8);\n");
- write_return_cycles("\t\t", 0);
- out("\t}\n");
- out("\tuae_u16 newsr = %s(4);\n", srcwi);
- out("\tif (!(newsr & 0x2000)) {\n");
- out("\t\tException(8);\n");
- write_return_cycles("\t\t", 0);
- out("\t}\n");
- out("\tregs.sr = newsr;\n");
+ out("uae_u16 sw = %s(2);\n", srcwi);
+ out("if (sw != 0x01c0) {\n");
+ out("Exception(11);\n");
+ write_return_cycles("", 0);
+ out("}\n");
+ out("if (!(regs.sr & 0x2000)) {\n");
+ out("Exception(8);\n");
+ write_return_cycles("", 0);
+ out("}\n");
+ out("uae_u16 newsr = %s(4);\n", srcwi);
+ out("if (!(newsr & 0x2000)) {\n");
+ out("Exception(8);\n");
+ write_return_cycles("", 0);
+ out("}\n");
+ out("regs.sr = newsr;\n");
makefromsr();
- out("\tm68k_setstopped();\n");
+ out("m68k_setstopped();\n");
m68k_pc_offset += 4;
sync_m68k_pc ();
fill_prefetch_full_ntx(0);
break;
case i_HALT: /* 68060 debug */
- out("\tcpu_halt(CPU_HALT_68060_HALT);\n");
+ out("cpu_halt(CPU_HALT_68060_HALT);\n");
break;
case i_PULSE: /* 68060 debug */
break;
addop_ce020 (curi, 0, 0);
next_level_000 ();
if (cpu_level <= 1 && using_exception_3) {
- out("\tif (m68k_areg(regs, 7) & 1) {\n");
- out("\t\texception3_read(opcode, m68k_areg(regs, 7), 1, 1);\n");
- write_return_cycles_noadd("\t\t", 0);
- out("\t}\n");
+ out("if (m68k_areg(regs, 7) & 1) {\n");
+ out("exception3_read(opcode, m68k_areg(regs, 7), 1, 1);\n");
+ write_return_cycles_noadd("", 0);
+ out("}\n");
}
if (cpu_level == 0) {
// 68000
// Read SR, Read PC high, Read PC low.
genamode (NULL, Aipi, "7", sz_word, "sr", 1, 0, GF_NOREFILL);
genamode (NULL, Aipi, "7", sz_long, "pc", 1, 0, GF_NOREFILL);
- out("\tuaecptr oldpc = %s;\n", getpc);
- out("\tuae_u16 oldt1 = regs.t1;\n");
- out("\tregs.sr = sr;\n");
+ out("uaecptr oldpc = %s;\n", getpc);
+ out("uae_u16 oldt1 = regs.t1;\n");
+ out("regs.sr = sr;\n");
makefromsr();
- out("\tif (pc & 1) {\n");
- out("\t\texception3_read(opcode | 0x20000, pc, 1, 2);\n");
- write_return_cycles("\t\t", 0);
- out("\t}\n");
+ out("if (pc & 1) {\n");
+ out("exception3_read(opcode | 0x20000, pc, 1, 2);\n");
+ write_return_cycles("", 0);
+ out("}\n");
setpc ("pc");
- out("\topcode |= 0x20000;\n");
+ out("opcode |= 0x20000;\n");
if (using_debugmem) {
- out("\tbranch_stack_pop_rte(oldpc);\n");
+ out("branch_stack_pop_rte(oldpc);\n");
}
} else if (cpu_level == 1 && using_prefetch) {
// 68010
// Read SR, Read Format, Read PC high, Read PC low.
int old_brace_level = n_braces;
- out("\tuaecptr oldpc = %s;\n", getpc);
- out("\tuae_u16 newsr;\n");
- out("\tuae_u32 newpc;\n");
- out("\tuaecptr a = m68k_areg(regs, 7);\n");
- out("\tuae_u16 sr = %s(a);\n", srcw);
+ out("uaecptr oldpc = %s;\n", getpc);
+ out("uae_u16 newsr;\n");
+ out("uae_u32 newpc;\n");
+ out("uaecptr a = m68k_areg(regs, 7);\n");
+ out("uae_u16 sr = %s(a);\n", srcw);
count_read++;
check_bus_error("", 0, 0, 1, NULL, 1);
- out("\tuae_u16 format = %s(a + 2 + 4);\n", srcw);
+ out("uae_u16 format = %s(a + 2 + 4);\n", srcw);
count_read++;
check_bus_error("", 6, 0, 1, NULL, 1);
- out("\tint frame = format >> 12;\n");
- out("\tint offset = 8;\n");
- out("\tif (frame == 0x0) {\n");
- out("\t\tm68k_areg(regs, 7) += offset;\n");
- out("\t} else if (frame == 0x8) {\n");
- out("\t\tm68k_areg(regs, 7) += offset + 50;\n");
- out("\t} else {\n");
- out("\t\tSET_NFLG(((uae_s16)format) < 0); \n");
- out("\t\tSET_ZFLG(format == 0);\n");
- out("\t\tSET_VFLG(0);\n");
- out("\t\tException_cpu(14);\n");
- write_return_cycles("\t\t", 0);
- out("\t}\n");
-
- out("\tuae_u32 pc = %s(a + 2) << 16;\n", srcw);
+ out("int frame = format >> 12;\n");
+ out("int offset = 8;\n");
+ out("if (frame == 0x0) {\n");
+ out("m68k_areg(regs, 7) += offset;\n");
+ out("} else if (frame == 0x8) {\n");
+ out("m68k_areg(regs, 7) += offset + 50;\n");
+ out("} else {\n");
+ out("SET_NFLG(((uae_s16)format) < 0); \n");
+ out("SET_ZFLG(format == 0);\n");
+ out("SET_VFLG(0);\n");
+ out("Exception_cpu(14);\n");
+ write_return_cycles("", 0);
+ out("}\n");
+
+ out("uae_u32 pc = %s(a + 2) << 16;\n", srcw);
count_read++;
check_bus_error("", 2, 0, 1, NULL, 1);
- out("\tpc |= %s(a + 2 + 2); \n", srcw);
+ out("pc |= %s(a + 2 + 2); \n", srcw);
count_read++;
check_bus_error("", 4, 0, 1, NULL, 1);
pop_braces (old_brace_level);
- out("\tregs.sr = sr;\n");
+ out("regs.sr = sr;\n");
makefromsr();
- out("\tif (pc & 1) {\n");
+ out("if (pc & 1) {\n");
dummy_prefetch("pc", "oldpc");
- out("\texception3i(opcode, pc);\n");
- write_return_cycles("\t\t", 0);
- out("\t}\n");
- out("\tnewsr = sr; newpc = pc;\n");
+ out("exception3i(opcode, pc);\n");
+ write_return_cycles("", 0);
+ out("}\n");
+ out("newsr = sr; newpc = pc;\n");
setpc ("newpc");
if (using_debugmem) {
- out("\tbranch_stack_pop_rte(oldpc);\n");
+ out("branch_stack_pop_rte(oldpc);\n");
}
check_ipl ();
} else {
int old_brace_level = n_braces;
- out("\tuaecptr oldpc = %s;\n", getpc);
- out("\tuae_u16 newsr; uae_u32 newpc;\n");
- out("\tfor (;;) {\n");
- out("\t\tuaecptr a = m68k_areg(regs, 7);\n");
- out("\t\tuae_u16 sr = %s(a);\n", srcw);
+ out("uaecptr oldpc = %s;\n", getpc);
+ out("uae_u16 newsr; uae_u32 newpc;\n");
+ out("for (;;) {\n");
+ out("uaecptr a = m68k_areg(regs, 7);\n");
+ out("uae_u16 sr = %s(a);\n", srcw);
count_read++;
- out("\t\tuae_u32 pc = %s(a + 2);\n", srcl);
+ out("uae_u32 pc = %s(a + 2);\n", srcl);
count_read += 2;
- out("\t\tuae_u16 format = %s(a + 2 + 4);\n", srcw);
+ out("uae_u16 format = %s(a + 2 + 4);\n", srcw);
count_read++;
- out("\t\tint frame = format >> 12;\n");
- out("\t\tint offset = 8;\n");
- out("\t\tnewsr = sr; newpc = pc;\n");
+ out("int frame = format >> 12;\n");
+ out("int offset = 8;\n");
+ out("newsr = sr; newpc = pc;\n");
addcycles_ce020 (6);
- out("\t\tif (frame == 0x0) {\n\t\t\tm68k_areg(regs, 7) += offset; break; }\n");
+ out("if (frame == 0x0) {\nm68k_areg(regs, 7) += offset; break; }\n");
if (cpu_level >= 2) {
// 68020+
- out("\t\telse if (frame == 0x1) {\n\t\t\tm68k_areg(regs, 7) += offset; }\n");
- out("\t\telse if (frame == 0x2) {\n\t\t\tm68k_areg(regs, 7) += offset + 4; break; }\n");
+ out("else if (frame == 0x1) {\nm68k_areg(regs, 7) += offset; }\n");
+ out("else if (frame == 0x2) {\nm68k_areg(regs, 7) += offset + 4; break; }\n");
}
if (cpu_level >= 4) {
// 68040+
- out("\t\telse if (frame == 0x3) {\n\t\t\tm68k_areg(regs, 7) += offset + 4; break; }\n");
+ out("else if (frame == 0x3) {\nm68k_areg(regs, 7) += offset + 4; break; }\n");
}
if (using_mmu == 68060) {
- out("\t\telse if (frame == 0x4) {\n\t\t\tm68k_do_rte_mmu060 (a); m68k_areg(regs, 7) += offset + 8; break; }\n");
+ out("else if (frame == 0x4) {\nm68k_do_rte_mmu060 (a); m68k_areg(regs, 7) += offset + 8; break; }\n");
} else if (cpu_level >= 4) {
// 68040+
- out("\t\telse if (frame == 0x4) {\n\t\t\tm68k_areg(regs, 7) += offset + 8; break; }\n");
+ out("else if (frame == 0x4) {\nm68k_areg(regs, 7) += offset + 8; break; }\n");
}
if (cpu_level == 1) {
// 68010 only
- out("\t\telse if (frame == 0x8) {\n\t\t\tm68k_areg(regs, 7) += offset + 50; break; }\n");
+ out("else if (frame == 0x8) {\nm68k_areg(regs, 7) += offset + 50; break; }\n");
}
if (using_mmu == 68040) {
- out("\t\telse if (frame == 0x7) {\n\t\t\tm68k_do_rte_mmu040 (a); m68k_areg(regs, 7) += offset + 52; break; }\n");
+ out("else if (frame == 0x7) {\nm68k_do_rte_mmu040 (a); m68k_areg(regs, 7) += offset + 52; break; }\n");
} else if (cpu_level == 4) {
// 68040 only
- out("\t\telse if (frame == 0x7) {\n\t\t\tm68k_areg(regs, 7) += offset + 52; break; }\n");
+ out("else if (frame == 0x7) {\nm68k_areg(regs, 7) += offset + 52; break; }\n");
}
if (cpu_level == 2 || cpu_level == 3) {
// 68020/68030 only
- out("\t\telse if (frame == 0x9) {\n\t\t\tm68k_areg(regs, 7) += offset + 12; break; }\n");
+ out("else if (frame == 0x9) {\nm68k_areg(regs, 7) += offset + 12; break; }\n");
if (using_mmu == 68030) {
if (using_prefetch_020) {
- out("\t\telse if (frame == 0xa) {\n");
- out("\t\t\tm68k_do_rte_mmu030c(a);\n");
- write_return_cycles("\t\t\t", 0);
- out("\t\t} else if (frame == 0xb) {\n");
- out("\t\t\tm68k_do_rte_mmu030c(a);\n");
- write_return_cycles("\t\t\t", 0);
- out("\t\t\t}\n");
+ out("else if (frame == 0xa) {\n");
+ out("m68k_do_rte_mmu030c(a);\n");
+ write_return_cycles("", 0);
+ out("} else if (frame == 0xb) {\n");
+ out("m68k_do_rte_mmu030c(a);\n");
+ write_return_cycles("", 0);
+ out("}\n");
} else {
- out("\t\telse if (frame == 0xa) {\n");
- out("\t\t\tm68k_do_rte_mmu030(a);\n");
- write_return_cycles("\t\t\t", 0);
- out("\t\t} else if (frame == 0xb) {\n");
- out("\t\t\tm68k_do_rte_mmu030(a);\n");
- write_return_cycles("\t\t\t", 0);
- out("\t\t\t}\n");
+ out("else if (frame == 0xa) {\n");
+ out("m68k_do_rte_mmu030(a);\n");
+ write_return_cycles("", 0);
+ out("} else if (frame == 0xb) {\n");
+ out("m68k_do_rte_mmu030(a);\n");
+ write_return_cycles("", 0);
+ out("}\n");
}
} else {
- out("\t\telse if (frame == 0xa) {\n\t\t\tm68k_areg(regs, 7) += offset + 24; break; }\n");
- out("\t\telse if (frame == 0xb) {\n\t\t\tm68k_areg(regs, 7) += offset + 84; break; }\n");
+ out("else if (frame == 0xa) {\nm68k_areg(regs, 7) += offset + 24; break; }\n");
+ out("else if (frame == 0xb) {\nm68k_areg(regs, 7) += offset + 84; break; }\n");
}
}
if (cpu_level == 1) {
- out("\t\telse {\n");
- out("\t\t\tSET_NFLG(((uae_s16)format) < 0); \n");
- out("\t\t\tSET_ZFLG(format == 0);\n");
- out("\t\t\tSET_VFLG(0);\n");
- out("\t\t\tException_cpu(14);\n");
- write_return_cycles("\t\t", 0);
- out("\t\t}\n");
+ out("else {\n");
+ out("SET_NFLG(((uae_s16)format) < 0); \n");
+ out("SET_ZFLG(format == 0);\n");
+ out("SET_VFLG(0);\n");
+ out("Exception_cpu(14);\n");
+ write_return_cycles("", 0);
+ out("}\n");
} else {
- out("\t\telse {\n");
- out("\t\t\tException_cpu(14);\n");
- write_return_cycles("\t\t\t", 0);
- out("\t\t}\n");
+ out("else {\n");
+ out("Exception_cpu(14);\n");
+ write_return_cycles("", 0);
+ out("}\n");
}
- out("\t\tregs.sr = newsr;\n");
+ out("regs.sr = newsr;\n");
makefromsr_t0();
out("}\n");
pop_braces (old_brace_level);
- out("\tregs.sr = newsr;\n");
+ out("regs.sr = newsr;\n");
addcycles_ce020 (4);
makefromsr_t0();
- out("\tif (newpc & 1) {\n");
- out("\t\texception3i(opcode, newpc);\n");
- write_return_cycles("\t\t", 0);
- out("\t}\n");
+ out("if (newpc & 1) {\n");
+ out("exception3i(opcode, newpc);\n");
+ write_return_cycles("", 0);
+ out("}\n");
setpc ("newpc");
if (using_debugmem) {
- out("\tbranch_stack_pop_rte(oldpc);\n");
+ out("branch_stack_pop_rte(oldpc);\n");
}
check_ipl ();
}
if (using_mmu) {
genamode (curi, curi->smode, "srcreg", curi->size, "offs", GENA_GETV_FETCH, GENA_MOVEM_DO_INC, 0);
genamode (NULL, Aipi, "7", sz_long, "pc", GENA_GETV_FETCH, GENA_MOVEM_DO_INC, 0);
- out("\tm68k_areg(regs, 7) += offs;\n");
+ out("m68k_areg(regs, 7) += offs;\n");
} else {
genamode (NULL, Aipi, "7", sz_long, "pc", 1, 0, 0);
genamode (curi, curi->smode, "srcreg", curi->size, "offs", 1, 0, GF_NOREFILL);
- out("\tm68k_areg(regs, 7) += offs;\n");
+ out("m68k_areg(regs, 7) += offs;\n");
}
- out("\tif (pc & 1) {\n");
+ out("if (pc & 1) {\n");
if (cpu_level >= 4) {
- out("\t\tm68k_areg(regs, 7) -= 4 + offs;\n");
+ out("m68k_areg(regs, 7) -= 4 + offs;\n");
}
- out("\t\texception3i(0x%04X, pc);\n", opcode);
- write_return_cycles("\t\t", 0);
- out("\t}\n");
+ out("exception3i(0x%04X, pc);\n", opcode);
+ write_return_cycles("", 0);
+ out("}\n");
setpc ("pc");
/* PC is set and prefetch filled. */
clear_m68k_offset();
genamode(NULL, Apdi, "7", sz_long, "old", GENA_GETV_FETCH_ALIGN, GENA_MOVEM_DO_INC, 0);
genastore("m68k_areg(regs, 7)", curi->smode, "srcreg", sz_long, "src");
}
- out("\tm68k_areg(regs, 7) += offs;\n");
+ out("m68k_areg(regs, 7) += offs;\n");
genastore("src", Apdi, "7", sz_long, "old");
} else {
addop_ce020(curi, 0, 0);
genamode(NULL, curi->smode, "srcreg", sz_long, "src", 1, 0, GF_AA);
genamode(NULL, Apdi, "7", sz_long, "old", 2, 0, GF_AA);
}
- strcpy(bus_error_code, "\t\tm68k_areg(regs, 7) += 4;\n");
+ strcpy(bus_error_code, "m68k_areg(regs, 7) += 4;\n");
genamode(NULL, curi->dmode, "dstreg", curi->size, "offs", 1, 0, 0);
genastore("src", Apdi, "7", sz_long, "old");
genastore("m68k_areg(regs, 7)", curi->smode, "srcreg", sz_long, "src");
- out("\tm68k_areg(regs, 7) += offs;\n");
+ out("m68k_areg(regs, 7) += offs;\n");
fill_prefetch_next_t();
if (cpu_level >= 5) {
if (next_cpu_level < 5)
// ce confirmed
if (using_mmu) {
genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
- out("\tuae_s32 old = %s(src);\n", srcl);
- out("\tm68k_areg(regs, 7) = src + 4;\n");
- out("\tm68k_areg(regs, srcreg) = old;\n");
+ out("uae_s32 old = %s(src);\n", srcl);
+ out("m68k_areg(regs, 7) = src + 4;\n");
+ out("m68k_areg(regs, srcreg) = old;\n");
} else {
genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
genamode(NULL, am_unknown, "src", sz_long, "old", 1, 0, 0);
- out("\tm68k_areg(regs, 7) = src + 4;\n");
+ out("m68k_areg(regs, 7) = src + 4;\n");
genastore ("old", curi->smode, "srcreg", curi->size, "src");
fill_prefetch_next_t();
}
break;
case i_RTS:
addop_ce020 (curi, 0, 0);
- out("\tuaecptr pc = %s;\n", getpc);
+ out("uaecptr pc = %s;\n", getpc);
if (cpu_level <= 1 && using_exception_3) {
- out("\tif (m68k_areg(regs, 7) & 1) {\n");
- out("\t\texception3_read(opcode, m68k_areg(regs, 7), 1, 1);\n");
- write_return_cycles("\t\t", 0);
- out("\t}\n");
+ out("if (m68k_areg(regs, 7) & 1) {\n");
+ out("exception3_read(opcode, m68k_areg(regs, 7), 1, 1);\n");
+ write_return_cycles("", 0);
+ out("}\n");
}
if (using_indirect > 0 && !using_ce020 && !using_prefetch_020 && !using_ce && !using_test) {
- out("\tm68k_do_rtsi_jit ();\n");
+ out("m68k_do_rtsi_jit ();\n");
count_read += 2;
} else if (using_mmu) {
- out("\tm68k_do_rts_mmu%s();\n", mmu_postfix);
+ out("m68k_do_rts_mmu%s();\n", mmu_postfix);
count_read += 2;
} else if (using_ce020 == 1) {
add_head_cycs (1);
- out("\tm68k_do_rts_ce020 ();\n");
+ out("m68k_do_rts_ce020 ();\n");
count_read += 2;
} else if (using_ce020 == 2) {
add_head_cycs (1);
- out("\tm68k_do_rts_ce030 ();\n");
+ out("m68k_do_rts_ce030 ();\n");
count_read += 2;
} else if (using_ce || using_prefetch || (using_test && cpu_level <= 1)) {
- out("\tuaecptr newpc, dsta = m68k_areg(regs, 7);\n");
- out("\tnewpc = %s(dsta) << 16;\n", srcw);
+ out("uaecptr newpc, dsta = m68k_areg(regs, 7);\n");
+ out("newpc = %s(dsta) << 16;\n", srcw);
count_read++;
check_bus_error("dst", 0, 0, 1, NULL, 1);
- out("\tnewpc |= %s(dsta + 2);\n", srcw);
+ out("newpc |= %s(dsta + 2);\n", srcw);
count_read++;
check_bus_error("dst", 2, 0, 1, NULL, 1);
- out("\tm68k_areg(regs, 7) += 4;\n");
+ out("m68k_areg(regs, 7) += 4;\n");
setpc("newpc");
} else if (using_prefetch_020 || (using_test && cpu_level >= 2)) {
- out("\tm68k_do_rtsi ();\n");
+ out("m68k_do_rtsi ();\n");
count_read += 2;
} else {
- out("\tm68k_do_rts ();\n");
+ out("m68k_do_rts ();\n");
count_read += 2;
}
if (using_debugmem) {
- out("\tif (debugmem_trace) {\n");
- out("\t\tbranch_stack_pop_rts(pc);\n");
+ out("if (debugmem_trace) {\n");
+ out("branch_stack_pop_rts(pc);\n");
out("}\n");
}
- out("\tif (%s & 1) {\n", getpc);
- out("\t\tuaecptr faultpc = %s;\n", getpc);
+ out("if (%s & 1) {\n", getpc);
+ out("uaecptr faultpc = %s;\n", getpc);
if (cpu_level == 1) {
dummy_prefetch(NULL, NULL);
}
setpc("pc");
if (cpu_level >= 4) {
- out("\t\tm68k_areg(regs, 7) -= 4;\n");
+ out("m68k_areg(regs, 7) -= 4;\n");
}
- out("\t\texception3i(0x%04X, faultpc);\n", opcode);
- write_return_cycles("\t\t", 0);
- out("\t}\n");
+ out("exception3i(0x%04X, faultpc);\n", opcode);
+ write_return_cycles("", 0);
+ out("}\n");
clear_m68k_offset();
if (using_prefetch || using_ce) {
fill_prefetch_full_000_special();
// If V is set but prefetch causes bus error: S is set.
// for some reason T is also cleared!
if (using_prefetch) {
- out("\tuae_u16 opcode_v = opcode;\n");
+ out("uae_u16 opcode_v = opcode;\n");
}
fill_prefetch_next_after(1,
- "\t\tif (GET_VFLG()) {\n"
- "\t\t\tMakeSR();\n"
- "\t\t\tregs.sr |= 0x2000;\n"
- "\t\t\tregs.sr &= ~0x8000;\n"
- "\t\t\tMakeFromSR();\n"
- "\t\t} else {\n"
- "\t\t\topcode = regs.ir | 0x20000;\n"
- "\t\t\tif(regs.t1) opcode |= 0x10000;\n"
- "\t\t}\n");
- out("\tif (GET_VFLG()) {\n");
+ "if (GET_VFLG()) {\n"
+ "MakeSR();\n"
+ "regs.sr |= 0x2000;\n"
+ "regs.sr &= ~0x8000;\n"
+ "MakeFromSR();\n"
+ "} else {\n"
+ "opcode = regs.ir | 0x20000;\n"
+ "if(regs.t1) opcode |= 0x10000;\n"
+ "}\n");
+ out("if (GET_VFLG()) {\n");
if (using_prefetch) {
// If exception vector is odd,
// stacked opcode is TRAPV
- out("\t\tregs.ir = opcode_v;\n");
+ out("regs.ir = opcode_v;\n");
}
- out("\t\tException_cpu(7);\n");
- write_return_cycles("\t\t", 0);
- out("\t}\n");
+ out("Exception_cpu(7);\n");
+ write_return_cycles("", 0);
+ out("}\n");
} else if (cpu_level == 1) {
push_ins_cnt();
- out("\tif (GET_VFLG()) {\n");
+ out("if (GET_VFLG()) {\n");
addcycles000(2);
- out("\t\tException_cpu(7);\n");
- write_return_cycles("\t\t", 0);
- out("\t}\n");
+ out("Exception_cpu(7);\n");
+ write_return_cycles("", 0);
+ out("}\n");
pop_ins_cnt();
fill_prefetch_next();
} else {
fill_prefetch_next();
- out("\tif (GET_VFLG()) {\n");
- out("\t\tException_cpu(7);\n");
- write_return_cycles("\t\t", 0);
- out("\t}\n");
+ out("if (GET_VFLG()) {\n");
+ out("Exception_cpu(7);\n");
+ write_return_cycles("", 0);
+ out("}\n");
}
break;
case i_RTR:
- out("\tuaecptr oldpc = %s;\n", getpc);
- out("\tMakeSR();\n");
+ out("uaecptr oldpc = %s;\n", getpc);
+ out("MakeSR();\n");
genamode (NULL, Aipi, "7", sz_word, "sr", 1, 0, 0);
genamode(NULL, Aipi, "7", sz_long, "pc", 1, 0, 0);
if (cpu_level >= 4) {
- out("\tif (pc & 1) {\n");
- out("\t\tm68k_areg(regs, 7) -= 6;\n");
- out("\t\texception3i(0x%04X, pc);\n", opcode);
- write_return_cycles("\t\t", 0);
- out("\t}\n");
- }
- out("\tregs.sr &= 0xFF00; sr &= 0xFF;\n");
- out("\tregs.sr |= sr;\n");
+ out("if (pc & 1) {\n");
+ out("m68k_areg(regs, 7) -= 6;\n");
+ out("exception3i(0x%04X, pc);\n", opcode);
+ write_return_cycles("", 0);
+ out("}\n");
+ }
+ out("regs.sr &= 0xFF00; sr &= 0xFF;\n");
+ out("regs.sr |= sr;\n");
makefromsr();
setpc ("pc");
if (cpu_level < 4) {
- out("\tif (%s & 1) {\n", getpc);
- out("\t\tuaecptr faultpc = %s;\n", getpc);
+ out("if (%s & 1) {\n", getpc);
+ out("uaecptr faultpc = %s;\n", getpc);
if (cpu_level == 1) {
dummy_prefetch(NULL, NULL);
}
setpc("oldpc");
- out("\t\texception3i(0x%04X, faultpc);\n", opcode);
- write_return_cycles("\t\t", 0);
- out("\t}\n");
+ out("exception3i(0x%04X, faultpc);\n", opcode);
+ write_return_cycles("", 0);
+ out("}\n");
}
clear_m68k_offset();
if (using_prefetch || using_ce) {
no_prefetch_ce020 = true;
genamode(curi, curi->smode, "srcreg", curi->size, "src", 0, 0, GF_AA | GF_NOREFILL);
start_brace();
- out("\tuaecptr oldpc = %s;\n", getpc);
- out("\tuaecptr nextpc = oldpc + %d;\n", m68k_pc_offset);
+ out("uaecptr oldpc = %s;\n", getpc);
+ out("uaecptr nextpc = oldpc + %d;\n", m68k_pc_offset);
if (using_exception_3 && cpu_level <= 1) {
push_ins_cnt();
- out("\tif (srca & 1) {\n");
+ out("if (srca & 1) {\n");
if (curi->smode >= Ad16 && cpu_level == 1 && using_prefetch) {
dummy_prefetch("srca", NULL);
}
if (curi->smode == Ad16 || curi->smode == absw || curi->smode == PC16) {
addcycles000_onlyce(2);
- addcycles000_nonce("\t\t", 2);
+ addcycles000_nonce("", 2);
}
if (curi->smode == Ad8r || curi->smode == PC8r) {
addcycles000_onlyce(6);
- addcycles000_nonce("\t\t", 6);
+ addcycles000_nonce("", 6);
}
- out("\t\texception3i(opcode, srca);\n");
- write_return_cycles_noadd("\t\t", 0);
- out("\t}\n");
+ out("exception3i(opcode, srca);\n");
+ write_return_cycles_noadd("", 0);
+ out("}\n");
pop_ins_cnt();
}
if (using_mmu) {
- out("\t%s(m68k_areg(regs, 7) - 4, nextpc);\n", dstl);
- out("\tm68k_areg(regs, 7) -= 4;\n");
+ out("%s(m68k_areg(regs, 7) - 4, nextpc);\n", dstl);
+ out("m68k_areg(regs, 7) -= 4;\n");
setpc("srca");
clear_m68k_offset();
} else {
if (curi->smode == Ad8r || curi->smode == PC8r) {
addcycles000(6);
if (cpu_level <= 1 && using_prefetch)
- out("\tnextpc += 2;\n");
+ out("nextpc += 2;\n");
}
setpc("srca");
clear_m68k_offset();
if (cpu_level >= 2 && cpu_level < 4)
- out("\tm68k_areg(regs, 7) -= 4;\n");
+ out("m68k_areg(regs, 7) -= 4;\n");
if (using_exception_3 && cpu_level >= 2) {
- out("\tif (%s & 1) {\n", getpc);
- out("\t\texception3i(opcode, %s);\n", getpc);
- write_return_cycles("\t\t", 0);
- out("\t}\n");
+ out("if (%s & 1) {\n", getpc);
+ out("exception3i(opcode, %s);\n", getpc);
+ write_return_cycles("", 0);
+ out("}\n");
}
fill_prefetch_1(0);
if (cpu_level < 2)
- out("\tm68k_areg(regs, 7) -= 4;\n");
+ out("m68k_areg(regs, 7) -= 4;\n");
if (using_exception_3 && cpu_level <= 1) {
- out("\tif (m68k_areg(regs, 7) & 1) {\n");
- out("\t\texception3_write(opcode, m68k_areg(regs, 7), 1, m68k_areg(regs, 7) >> 16, 1);\n");
- write_return_cycles("\t\t", 0);
- out("\t}\n");
+ out("if (m68k_areg(regs, 7) & 1) {\n");
+ out("exception3_write(opcode, m68k_areg(regs, 7), 1, m68k_areg(regs, 7) >> 16, 1);\n");
+ write_return_cycles("", 0);
+ out("}\n");
}
if (using_ce || using_prefetch) {
- out("\tuaecptr dsta = m68k_areg(regs, 7);\n");
- out("\t%s(dsta, nextpc >> 16);\n", dstw);
+ out("uaecptr dsta = m68k_areg(regs, 7);\n");
+ out("%s(dsta, nextpc >> 16);\n", dstw);
count_write++;
check_bus_error("dst", 0, 1, 1, "nextpc >> 16", 1);
- out("\t%s(dsta + 2, nextpc);\n", dstw);
+ out("%s(dsta + 2, nextpc);\n", dstw);
count_write++;
check_bus_error("dst", 2, 1, 1, "nextpc", 1);
} else {
if (cpu_level < 4)
- out("\t%s(m68k_areg(regs, 7), nextpc);\n", dstl);
+ out("%s(m68k_areg(regs, 7), nextpc);\n", dstl);
else
- out("\t%s(m68k_areg(regs, 7) - 4, nextpc);\n", dstl);
+ out("%s(m68k_areg(regs, 7) - 4, nextpc);\n", dstl);
count_write += 2;
}
if (cpu_level >= 4)
- out("\tm68k_areg(regs, 7) -= 4;\n");
+ out("m68k_areg(regs, 7) -= 4;\n");
if (using_debugmem) {
- out("\tif (debugmem_trace) {\n");
- out("\t\tbranch_stack_push(oldpc, nextpc);\n");
+ out("if (debugmem_trace) {\n");
+ out("branch_stack_push(oldpc, nextpc);\n");
out("}\n");
}
}
irc2ir();
copy_opcode();
if (sp < 0 && cpu_level == 0)
- out("\tif(regs.t1) opcode |= 0x10000;\n");
- out("\t%s(%d);\n", prefetch_word, 2);
+ out("if(regs.t1) opcode |= 0x10000;\n");
+ out("%s(%d);\n", prefetch_word, 2);
count_read++;
check_prefetch_bus_error(-2, sp);
did_prefetch = 1;
genamode (curi, curi->smode, "srcreg", curi->size, "src", 0, 0, GF_AA|GF_NOREFILL);
if (using_exception_3) {
push_ins_cnt();
- out("\tif (srca & 1) {\n");
+ out("if (srca & 1) {\n");
if (curi->smode >= Ad16 && cpu_level == 1 && using_prefetch) {
dummy_prefetch("srca", NULL);
}
if (curi->smode == Ad16 || curi->smode == absw || curi->smode == PC16) {
addcycles000_onlyce(2);
- addcycles000_nonce("\t\t", 2);
+ addcycles000_nonce("", 2);
}
if (curi->smode == Ad8r || curi->smode == PC8r) {
addcycles000_onlyce(6);
- addcycles000_nonce("\t\t", 6);
+ addcycles000_nonce("", 6);
}
- out("\t\texception3i(opcode, srca);\n");
- write_return_cycles_noadd("\t\t", 0);
- out("\t}\n");
+ out("exception3i(opcode, srca);\n");
+ write_return_cycles_noadd("", 0);
+ out("}\n");
pop_ins_cnt();
}
if (curi->smode == Ad16 || curi->smode == absw || curi->smode == PC16)
setpc ("srca");
clear_m68k_offset();
if (using_prefetch || using_ce) {
- out("\t%s(%d);\n", prefetch_word, 0);
+ out("%s(%d);\n", prefetch_word, 0);
count_read++;
check_prefetch_bus_error(-1, 0);
irc2ir();
- out("\t%s(%d);\n", prefetch_word, 2);
+ out("%s(%d);\n", prefetch_word, 2);
int sp = (curi->smode == Ad16 || curi->smode == absw || curi->smode == absl || curi->smode == PC16 || curi->smode == Ad8r || curi->smode == PC8r) ? -1 : 0;
copy_opcode();
if (sp < 0 && cpu_level == 0)
- out("\tif(regs.t1) opcode |= 0x10000;\n");
+ out("if(regs.t1) opcode |= 0x10000;\n");
count_read++;
check_prefetch_bus_error(-2, sp);
did_prefetch = 1;
// .b/.w = idle cycle, store high, store low, 2xprefetch
if (isce020())
no_prefetch_ce020 = true;
- out("\tuae_s32 s;\n");
+ out("uae_s32 s;\n");
if (curi->size == sz_long) {
if (next_cpu_level < 1)
next_cpu_level = 1;
}
if (curi->size == sz_long && cpu_level < 2) {
- out("\tuae_u32 src = 0xffffffff;\n");
+ out("uae_u32 src = 0xffffffff;\n");
} else {
genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA|GF_NOREFILL);
}
- out("\ts = (uae_s32)src + 2;\n");
+ out("s = (uae_s32)src + 2;\n");
if (using_exception_3) {
if (cpu_level == 0) {
- out("\tif (m68k_areg(regs, 7) & 1) {\n");
- out("\t\tm68k_areg(regs, 7) -= 4;\n");
- out("\t\texception3b(opcode, m68k_areg(regs, 7), true, false, %s + 2);\n", getpc);
- write_return_cycles("\t\t", 0);
- out("\t}\n");
+ out("if (m68k_areg(regs, 7) & 1) {\n");
+ out("m68k_areg(regs, 7) -= 4;\n");
+ out("exception3b(opcode, m68k_areg(regs, 7), true, false, %s + 2);\n", getpc);
+ write_return_cycles("", 0);
+ out("}\n");
} else if (cpu_level == 1) {
- out("\tif (m68k_areg(regs, 7) & 1) {\n");
- out("\t\texception3b(opcode, m68k_areg(regs, 7), true, true, %s);\n", getpc);
- write_return_cycles("\t\t", 0);
- out("\t}\n");
+ out("if (m68k_areg(regs, 7) & 1) {\n");
+ out("exception3b(opcode, m68k_areg(regs, 7), true, true, %s);\n", getpc);
+ write_return_cycles("", 0);
+ out("}\n");
}
}
addcycles000(2);
- out("\tuaecptr oldpc = %s;\n", getpc);
- out("\tuaecptr nextpc = oldpc + %d;\n", m68k_pc_offset);
+ out("uaecptr oldpc = %s;\n", getpc);
+ out("uaecptr nextpc = oldpc + %d;\n", m68k_pc_offset);
if (using_exception_3 && cpu_level == 1) {
// 68010 TODO: looks like prefetches are done first and stack writes last
- out("\tif (s & 1) {\n");
+ out("if (s & 1) {\n");
dummy_prefetch("(oldpc + s) & ~1", "oldpc");
- out("\t\texception3b(opcode, oldpc + s, false, true, %s);\n", getpc);
- write_return_cycles("\t\t", 0);
- out("\t}\n");
+ out("exception3b(opcode, oldpc + s, false, true, %s);\n", getpc);
+ write_return_cycles("", 0);
+ out("}\n");
}
if (using_exception_3 && cpu_level >= 2) {
- out("\tif (s & 1) {\n");
+ out("if (s & 1) {\n");
if (cpu_level < 4)
- out("\t\tm68k_areg(regs, 7) -= 4;\n");
- out("\t\texception3b(opcode, %s + s, 0, 1, %s + s);\n", getpc, getpc);
- write_return_cycles("\t\t", 0);
- out("\t}\n");
+ out("m68k_areg(regs, 7) -= 4;\n");
+ out("exception3b(opcode, %s + s, 0, 1, %s + s);\n", getpc, getpc);
+ write_return_cycles("", 0);
+ out("}\n");
}
if (using_indirect > 0 && !using_ce020 && !using_prefetch_020 && !using_ce && !using_test) {
- out("\tm68k_do_bsri_jit (nextpc, s);\n");
+ out("m68k_do_bsri_jit (nextpc, s);\n");
} else if (using_mmu) {
- out("\tm68k_do_bsr_mmu%s(nextpc, s);\n", mmu_postfix);
+ out("m68k_do_bsr_mmu%s(nextpc, s);\n", mmu_postfix);
} else if (using_ce020 == 1) {
- out("\tm68k_do_bsr_ce020(nextpc, s);\n");
+ out("m68k_do_bsr_ce020(nextpc, s);\n");
} else if (using_ce020 == 2) {
- out("\tm68k_do_bsr_ce030(nextpc, s);\n");
+ out("m68k_do_bsr_ce030(nextpc, s);\n");
} else if (using_ce) {
- out("\tm68k_do_bsr_ce(nextpc, s);\n");
+ out("m68k_do_bsr_ce(nextpc, s);\n");
} else if (using_prefetch || (using_test && cpu_level <= 1)) {
- out("\tm68k_areg(regs, 7) -= 4;\n");
- out("\tuaecptr dsta = m68k_areg(regs, 7);\n");
- out("\t%s(dsta, nextpc >> 16);\n", dstw);
+ out("m68k_areg(regs, 7) -= 4;\n");
+ out("uaecptr dsta = m68k_areg(regs, 7);\n");
+ out("%s(dsta, nextpc >> 16);\n", dstw);
check_bus_error("dst", 0, 1, 1, "nextpc >> 16", 1);
- out("\t%s(dsta + 2, nextpc);\n", dstw);
+ out("%s(dsta + 2, nextpc);\n", dstw);
check_bus_error("dst", 2, 1, 1, "nextpc", 1);
incpc("s");
} else if (using_prefetch_020 || (using_test && cpu_level >= 2)) {
- out("\tm68k_do_bsri (nextpc, s);\n");
+ out("m68k_do_bsri (nextpc, s);\n");
} else {
- out("\tm68k_do_bsr (nextpc, s);\n");
+ out("m68k_do_bsr (nextpc, s);\n");
}
count_write += 2;
if (using_exception_3 && cpu_level == 0) {
- out("\tif (%s & 1) {\n", getpc);
- out("\t\texception3b(opcode, %s, false, true, %s);\n", getpc, getpc);
- write_return_cycles("\t\t", 0);
- out("\t}\n");
+ out("if (%s & 1) {\n", getpc);
+ out("exception3b(opcode, %s, false, true, %s);\n", getpc, getpc);
+ write_return_cycles("", 0);
+ out("}\n");
}
if (using_debugmem) {
- out("\tif (debugmem_trace) {\n");
- out("\t\tbranch_stack_push(oldpc, nextpc);\n");
+ out("if (debugmem_trace) {\n");
+ out("branch_stack_push(oldpc, nextpc);\n");
out("}\n");
}
clear_m68k_offset();
if (curi->size == sz_long) {
if (cpu_level < 2) {
addcycles000 (2);
- out("\tif (cctrue(%d)) {\n", curi->cc);
- out("\t\texception3i(opcode, %s + 1);\n", getpc);
- write_return_cycles("\t\t", 0);
- out("\t}\n");
+ out("if (cctrue(%d)) {\n", curi->cc);
+ out("exception3i(opcode, %s + 1);\n", getpc);
+ write_return_cycles("", 0);
+ out("}\n");
sync_m68k_pc ();
addcycles000 (2);
irc2ir ();
genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA | (cpu_level < 2 ? GF_NOREFILL : 0));
addcycles000 (2);
if (using_exception_3 && cpu_level >= 4) {
- out("\tif (src & 1) {\n");
- out("\t\texception3i(opcode, %s + 2 + (uae_s32)src);\n", getpc);
- write_return_cycles("\t\t", 0);
- out("\t}\n");
+ out("if (src & 1) {\n");
+ out("exception3i(opcode, %s + 2 + (uae_s32)src);\n", getpc);
+ write_return_cycles("", 0);
+ out("}\n");
}
- out("\tif (cctrue(%d)) {\n", curi->cc);
+ out("if (cctrue(%d)) {\n", curi->cc);
if (using_exception_3 && cpu_level < 4) {
- out("\t\tif (src & 1) {\n");
+ out("if (src & 1) {\n");
if (cpu_level == 1) {
- out("\t\tuaecptr oldpc = %s;\n", getpc);
+ out("uaecptr oldpc = %s;\n", getpc);
incpc("((uae_s32)src + 2) & ~1");
dummy_prefetch(NULL, "oldpc");
}
- out("\t\t\texception3i(opcode, %s + 2 + (uae_s32)src);\n", getpc);
- write_return_cycles("\t\t\t", 0);
- out("\t\t}\n");
+ out("exception3i(opcode, %s + 2 + (uae_s32)src);\n", getpc);
+ write_return_cycles("", 0);
+ out("}\n");
}
push_ins_cnt();
if (using_prefetch) {
incpc ("(uae_s32)src + 2");
fill_prefetch_full_000_special();
if (using_ce)
- out("\t\treturn;\n");
+ out("return;\n");
else
- out("\t\treturn 10 * CYCLE_UNIT / 2;\n");
+ out("return 10 * CYCLE_UNIT / 2;\n");
} else {
incpc ("(uae_s32)src + 2");
add_head_cycs (6);
fill_prefetch_full_020 ();
- returncycles ("\t\t", 10);
+ returncycles ("", 10);
}
pop_ins_cnt();
- out("\t}\n");
+ out("}\n");
sync_m68k_pc ();
if (cpu_level == 1) {
if (curi->size != sz_byte)
if (curi->smode == Ad8r || curi->smode == PC8r)
addcycles000 (2);
if (curi->smode == absl) {
- strcpy(bus_error_code, "\t\tm68k_areg(regs, dstreg) = (m68k_areg(regs, dstreg) & 0x0000ffff) | (srca & 0xffff0000);\n");
- strcpy(bus_error_code2, "\t\tm68k_areg(regs, dstreg) = (srca);\n");
+ strcpy(bus_error_code, "m68k_areg(regs, dstreg) = (m68k_areg(regs, dstreg) & 0x0000ffff) | (srca & 0xffff0000);\n");
+ strcpy(bus_error_code2, "m68k_areg(regs, dstreg) = (srca);\n");
} else if (curi->smode != Ad8r && curi->smode != PC8r) {
- strcpy(bus_error_code, "\t\tm68k_areg(regs, dstreg) = (srca);\n");
+ strcpy(bus_error_code, "m68k_areg(regs, dstreg) = (srca);\n");
}
genamodedual (curi,
curi->smode, "srcreg", curi->size, "src", 0, GF_AA,
curi->smode, "srcreg", curi->size, "src", 1, GF_AA | (cpu_level < 2 ? GF_NOREFILL : 0),
curi->dmode, "dstreg", curi->size, "offs", 1, GF_AA | (cpu_level < 2 ? GF_NOREFILL : 0));
if (cpu_level == 1) {
- out("\tint was_loop_mode = regs.loop_mode;\n");
- out("\tregs.loop_mode = 0;\n");
+ out("int was_loop_mode = regs.loop_mode;\n");
+ out("regs.loop_mode = 0;\n");
}
- out("\tuaecptr oldpc = %s;\n", getpc);
+ out("uaecptr oldpc = %s;\n", getpc);
addcycles000(2);
- addcycles000_nonce("\t", 2);
+ addcycles000_nonce("", 2);
if (using_exception_3 && cpu_level >= 4) {
- out("\tif (offs & 1) {\n");
- out("\t\t\texception3i(opcode, oldpc + (uae_s32)offs + 2);\n");
- write_return_cycles("\t\t", 0);
- out("\t\t}\n");
+ out("if (offs & 1) {\n");
+ out("exception3i(opcode, oldpc + (uae_s32)offs + 2);\n");
+ write_return_cycles("", 0);
+ out("}\n");
}
push_ins_cnt();
- out("\tif (!cctrue(%d)) {\n", curi->cc);
- out("\t");
+ out("if (!cctrue(%d)) {\n", curi->cc);
+ out("");
incpc ("(uae_s32)offs + 2");
if (cpu_level >= 2 && cpu_level < 4) {
genastore("(src - 1)", curi->smode, "srcreg", curi->size, "src");
}
- out("\t");
+ out("");
if (using_exception_3 && cpu_level < 4) {
- out("\tif (offs & 1) {\n");
+ out("if (offs & 1) {\n");
if (cpu_level == 1) {
- out("\t\t\t%s(%d);\n", prefetch_word, -1);
+ out("%s(%d);\n", prefetch_word, -1);
}
- out("\t\t\texception3i(opcode, %s);\n", getpc);
- write_return_cycles("\t\t", 0);
- out("\t\t}\n");
+ out("exception3i(opcode, %s);\n", getpc);
+ write_return_cycles("", 0);
+ out("}\n");
}
// 68010 loop mode handling
if (cpu_level == 1) {
- out("\t\tif(offs == -4 && !regs.t1 && loop_mode_table[regs.ird]) {\n");
+ out("if(offs == -4 && !regs.t1 && loop_mode_table[regs.ird]) {\n");
// first loop takes as many cycles as normal DBcc branch
// perhaps it also does actual prefetches??
- out("\t\t\tif(!was_loop_mode) {\n");
+ out("if(!was_loop_mode) {\n");
addcycles000(6);
- addcycles000_nonce("\t\t", 6);
- out("\t\t\t}\n");
- out("\t\t\tregs.loop_mode = 1;\n");
- out("\t\t\tsrc = m68k_dreg(regs, srcreg);\n");
+ addcycles000_nonce("", 6);
+ out("}\n");
+ out("regs.loop_mode = 1;\n");
+ out("src = m68k_dreg(regs, srcreg);\n");
genastore("(src - 1)", curi->smode, "srcreg", curi->size, "src");
addcycles000(2);
- addcycles000_nonce("\t\t", 2);
- out("\t\t\tif (src) {\n");
+ addcycles000_nonce("", 2);
+ out("if (src) {\n");
if (using_ce) {
- out("\t\t\t\tloop_mode_table[regs.ird](regs.ird);\n");
+ out("loop_mode_table[regs.ird](regs.ird);\n");
} else {
- out("\t\t\t\tcount_cycles += loop_mode_table[regs.ird](regs.ird);\n");
+ out("count_cycles += loop_mode_table[regs.ird](regs.ird);\n");
}
- out("\t // quick exit if condition false and count expired\n");
- out("\t\t\t\tif (!cctrue(%d) && (m68k_dreg(regs, srcreg) & 0xffff) == 0) {\n", curi->cc);
- out("\t\t\t\t\tm68k_dreg(regs, srcreg) |= 0xffff;\n");
+ out(" // quick exit if condition false and count expired\n");
+ out("if (!cctrue(%d) && (m68k_dreg(regs, srcreg) & 0xffff) == 0) {\n", curi->cc);
+ out("m68k_dreg(regs, srcreg) |= 0xffff;\n");
- out("\t // loop exit: add possible extra cycle(s)\n");
- out("\t\t\t\t\tif(regs.loop_mode >> 16) {\n");
+ out(" // loop exit: add possible extra cycle(s)\n");
+ out("if(regs.loop_mode >> 16) {\n");
if (using_ce) {
- out("\t\t\t\t\t\t%s(regs.loop_mode >> 16);\n", do_cycles);
+ out("%s(regs.loop_mode >> 16);\n", do_cycles);
}
- addcycles000_nonces("\t\t\t\t\t\t", "regs.loop_mode >> 16");
- out("\t\t\t\t\t}\n");
+ addcycles000_nonces("", "regs.loop_mode >> 16");
+ out("}\n");
- out("\t\t\t\t\tregs.loop_mode = 0;\n");
+ out("regs.loop_mode = 0;\n");
setpc("oldpc + %d", m68k_pc_offset);
int old_m68k_pc_offset = m68k_pc_offset;
int old_m68k_pc_total = m68k_pc_total;
clear_m68k_offset();
get_prefetch_020_continue();
fill_prefetch_full_000_special();
- returncycles("\t\t\t", 8);
+ returncycles("", 8);
m68k_pc_offset = old_m68k_pc_offset;
m68k_pc_total = old_m68k_pc_total;
- out("\t\t\t\t}\n");
+ out("}\n");
- out("\t // loop continue: add possible extra cycle(s)\n");
- out("\t\t\t\tif(regs.loop_mode & 0xfffe) {\n");
- addcycles000_nonces("\t\t\t\t\t", "regs.loop_mode & 0xfffe");
+ out(" // loop continue: add possible extra cycle(s)\n");
+ out("if(regs.loop_mode & 0xfffe) {\n");
+ addcycles000_nonces("", "regs.loop_mode & 0xfffe");
if (using_ce) {
- out("\t\t\t\t\t%s(regs.loop_mode & 0xfffe);\n", do_cycles);
+ out("%s(regs.loop_mode & 0xfffe);\n", do_cycles);
}
- out("\t\t\t\t}\n");
+ out("}\n");
setpc("oldpc");
check_ipl();
- returncycles("\t\t\t\t", 0);
- out("\t\t\t}\n");
- out("\t\t\tregs.loop_mode = 0;\n");
+ returncycles("", 0);
+ out("}\n");
+ out("regs.loop_mode = 0;\n");
setpc("oldpc + %d", m68k_pc_offset);
fill_prefetch_full_000_special();
- returncycles("\t\t\t", 8);
- out("\t\t}\n");
+ returncycles("", 8);
+ out("}\n");
}
- out("\t");
+ out("");
fill_prefetch_1(0);
- out("\t");
+ out("");
if (cpu_level < 2 || cpu_level >= 4) {
genastore("(src - 1)", curi->smode, "srcreg", curi->size, "src");
}
- out("\t\tif (src) {\n");
+ out("if (src) {\n");
irc2ir ();
add_head_cycs (6);
if (using_prefetch || using_ce) {
copy_opcode();
if (cpu_level == 0) {
- out("\tif(regs.t1) opcode |= 0x10000;\n");
+ out("if(regs.t1) opcode |= 0x10000;\n");
}
- out("\t%s(%d);\n", prefetch_word, 2);
+ out("%s(%d);\n", prefetch_word, 2);
check_prefetch_bus_error(-2, -1);
did_prefetch = 1;
ir2irc = 0;
}
fill_prefetch_full_020 ();
- returncycles ("\t\t\t", 10);
- out("\t\t}\n");
+ returncycles ("", 10);
+ out("}\n");
if (cpu_level == 1) {
- out("\t\tif (!src) {\n");
+ out("if (!src) {\n");
addcycles000_onlyce(2);
- addcycles000_nonce("\t\t\t", 2);
- out("\t\t}\n");
+ addcycles000_nonce("", 2);
+ out("}\n");
}
add_head_cycs (10);
- addcycles000_nonce("\t\t", 2 + 2);
+ addcycles000_nonce("", 2 + 2);
if (cpu_level == 0) {
- out("\t} else {\n");
+ out("} else {\n");
addcycles000_onlyce(2);
- addcycles000_nonce("\t\t", 2);
+ addcycles000_nonce("", 2);
}
- out("\t}\n");
+ out("}\n");
pop_ins_cnt();
setpc ("oldpc + %d", m68k_pc_offset);
clear_m68k_offset();
genamode(curi, curi->smode, "srcreg", curi->size, "src", cpu_level == 0 ? 1 : 2, 0, cpu_level == 1 ? GF_NOFETCH : 0);
if (isreg(curi->smode)) {
// If mode is Dn and condition true = 2 extra cycles needed.
- out("\tint val = cctrue(%d) ? 0xff : 0x00;\n", curi->cc);
+ out("int val = cctrue(%d) ? 0xff : 0x00;\n", curi->cc);
if (using_ce)
- out("\tint cycles = val ? 2 : 0;\n");
+ out("int cycles = val ? 2 : 0;\n");
if (using_bus_error && cpu_level <= 1) {
- out("\tif (!val) {\n");
+ out("if (!val) {\n");
genastore("val", curi->smode, "srcreg", curi->size, "src");
- out("\t}\n");
+ out("}\n");
if (cpu_level == 0) {
- out("\topcode |= 0x20000;\n");
+ out("opcode |= 0x20000;\n");
}
}
- fill_prefetch_next_extra("if (!val)", "\t\tif(!val && regs.t1) opcode |= 0x10000;\n");
+ fill_prefetch_next_extra("if (!val)", "if(!val && regs.t1) opcode |= 0x10000;\n");
genastore("val", curi->smode, "srcreg", curi->size, "src");
- addcycles000_3("\t");
- addcycles000_nonces("\t", "(val ? 2 : 0)");
+ addcycles000_3("");
+ addcycles000_nonces("", "(val ? 2 : 0)");
} else {
fill_prefetch_next_after(1, NULL);
- out("\tint val = cctrue(%d) ? 0xff : 0x00;\n", curi->cc);
+ out("int val = cctrue(%d) ? 0xff : 0x00;\n", curi->cc);
genastore("val", curi->smode, "srcreg", curi->size, "src");
}
break;
curi->smode, "srcreg", sz_word, "src", 1, 0,
curi->dmode, "dstreg", sz_long, "dst", 1, 0);
push_ins_cnt();
- out("\tif (src == 0) {\n");
- out("\t\tdivbyzero_special(0, dst);\n");
+ out("if (src == 0) {\n");
+ out("divbyzero_special(0, dst);\n");
incpc("%d", m68k_pc_offset);
addcycles000(4);
- out("\t\tException_cpu(5);\n");
- write_return_cycles("\t\t", 0);
- out("\t}\n");
+ out("Exception_cpu(5);\n");
+ write_return_cycles("", 0);
+ out("}\n");
pop_ins_cnt();
- out("\tuae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;\n");
- out("\tuae_u32 rem = (uae_u32)dst %%%% (uae_u32)(uae_u16)src;\n");
+ out("uae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;\n");
+ out("uae_u32 rem = (uae_u32)dst %%%% (uae_u32)(uae_u16)src;\n");
if (using_ce) {
- out("\tint cycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);\n");
- addcycles000_3("\t");
- }
- addcycles000_nonces("\t", "getDivu68kCycles((uae_u32)dst, (uae_u16)src)");
- out("\tif (newv > 0xffff) {\n");
- out("\t\tsetdivuflags((uae_u32)dst, (uae_u16)src);\n");
- out("\t} else {\n");
- out("\t");
+ out("int cycles = getDivu68kCycles((uae_u32)dst, (uae_u16)src);\n");
+ addcycles000_3("");
+ }
+ addcycles000_nonces("", "getDivu68kCycles((uae_u32)dst, (uae_u16)src)");
+ out("if (newv > 0xffff) {\n");
+ out("setdivuflags((uae_u32)dst, (uae_u16)src);\n");
+ out("} else {\n");
+ out("");
genflags (flag_logical, sz_word, "newv", "", "");
- out("\t\tnewv = (newv & 0xffff) | ((uae_u32)rem << 16);\n");
- out("\t");
+ out("newv = (newv & 0xffff) | ((uae_u32)rem << 16);\n");
+ out("");
genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
- out("\t}\n");
+ out("}\n");
fill_prefetch_next_t();
sync_m68k_pc();
count_ncycles++;
curi->smode, "srcreg", sz_word, "src", 1, 0,
curi->dmode, "dstreg", sz_long, "dst", 1, 0);
push_ins_cnt();
- out("\tif (src == 0) {\n");
- out("\t\tdivbyzero_special (1, dst);\n");
+ out("if (src == 0) {\n");
+ out("divbyzero_special (1, dst);\n");
incpc("%d", m68k_pc_offset);
addcycles000(4);
- out("\t\tException_cpu(5);\n");
- write_return_cycles("\t\t", 0);
- out("\t}\n");
+ out("Exception_cpu(5);\n");
+ write_return_cycles("", 0);
+ out("}\n");
pop_ins_cnt();
if (using_ce) {
- out("\tint cycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src);\n");
- addcycles000_3("\t");
- }
- addcycles000_nonces("\t", "getDivs68kCycles((uae_s32)dst, (uae_s16)src)");
- out("\tif (dst == 0x80000000 && src == -1) {\n");
- out("\t\tsetdivsflags((uae_s32)dst, (uae_s16)src);\n");
- out("\t} else {\n");
- out("\t\tuae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;\n");
- out("\t\tuae_u16 rem = (uae_s32)dst %%%% (uae_s32)(uae_s16)src;\n");
- out("\t\tif ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {\n");
- out("\t\t\tsetdivsflags((uae_s32)dst, (uae_s16)src);\n");
- out("\t\t} else {\n");
- out("\t\t\tif (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;\n");
+ out("int cycles = getDivs68kCycles((uae_s32)dst, (uae_s16)src);\n");
+ addcycles000_3("");
+ }
+ addcycles000_nonces("", "getDivs68kCycles((uae_s32)dst, (uae_s16)src)");
+ out("if (dst == 0x80000000 && src == -1) {\n");
+ out("setdivsflags((uae_s32)dst, (uae_s16)src);\n");
+ out("} else {\n");
+ out("uae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;\n");
+ out("uae_u16 rem = (uae_s32)dst %%%% (uae_s32)(uae_s16)src;\n");
+ out("if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) {\n");
+ out("setdivsflags((uae_s32)dst, (uae_s16)src);\n");
+ out("} else {\n");
+ out("if (((uae_s16)rem < 0) != ((uae_s32)dst < 0)) rem = -rem;\n");
genflags(flag_logical, sz_word, "newv", "", "");
- out("\t\t\tnewv = (newv & 0xffff) | ((uae_u32)rem << 16);\n");
- out("\t\t");
+ out("newv = (newv & 0xffff) | ((uae_u32)rem << 16);\n");
+ out("");
genastore("newv", curi->dmode, "dstreg", sz_long, "dst");
- out("\t\t}\n");
- out("\t}\n");
+ out("}\n");
+ out("}\n");
fill_prefetch_next_t();
sync_m68k_pc();
count_ncycles++;
curi->smode, "srcreg", sz_word, "src", 1, 0,
curi->dmode, "dstreg", sz_word, "dst", 1, 0);
fill_prefetch_next_after(1,
- "\t\tCLEAR_CZNV();\n"
- "\t\tSET_ZFLG(1);\n"
- "\t\tm68k_dreg(regs, dstreg) &= 0xffff0000;\n");
- out("\tuae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;\n");
+ "CLEAR_CZNV();\n"
+ "SET_ZFLG(1);\n"
+ "m68k_dreg(regs, dstreg) &= 0xffff0000;\n");
+ out("uae_u32 newv = (uae_u32)(uae_u16)dst * (uae_u32)(uae_u16)src;\n");
genflags (flag_logical, sz_long, "newv", "", "");
if (using_ce) {
- out("\tint cycles = getMulu68kCycles(src);\n");
- addcycles000_3("\t");
+ out("int cycles = getMulu68kCycles(src);\n");
+ addcycles000_3("");
}
- addcycles000_nonces("\t", "getMulu68kCycles(src)");
+ addcycles000_nonces("", "getMulu68kCycles(src)");
genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
sync_m68k_pc ();
count_ncycles++;
curi->smode, "srcreg", sz_word, "src", 1, 0,
curi->dmode, "dstreg", sz_word, "dst", 1, 0);
fill_prefetch_next_after(1,
- "\t\tCLEAR_CZNV();\n"
- "\t\tSET_ZFLG(1);\n"
- "\t\tm68k_dreg(regs, dstreg) &= 0xffff0000;\n");
- out("\tuae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;\n");
+ "CLEAR_CZNV();\n"
+ "SET_ZFLG(1);\n"
+ "m68k_dreg(regs, dstreg) &= 0xffff0000;\n");
+ out("uae_u32 newv = (uae_s32)(uae_s16)dst * (uae_s32)(uae_s16)src;\n");
genflags (flag_logical, sz_long, "newv", "", "");
if (using_ce) {
- out("\tint cycles = getMuls68kCycles(src);\n");
- addcycles000_3("\t");
+ out("int cycles = getMuls68kCycles(src);\n");
+ addcycles000_3("");
}
- addcycles000_nonces("\t", "getMuls68kCycles(src)");
+ addcycles000_nonces("", "getMuls68kCycles(src)");
genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
count_ncycles++;
insn_n_cycles += (70 - 38) / 2 + 38; /* average */
genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
sync_m68k_pc();
addcycles000(4);
- out("\tif (dst > src) {\n");
- out("\t\tsetchkundefinedflags(src, dst, %d);\n", curi->size);
- out("\t\tException_cpu(6);\n");
- write_return_cycles("\t\t", 0);
- out("\t}\n");
+ out("if (dst > src) {\n");
+ out("setchkundefinedflags(src, dst, %d);\n", curi->size);
+ out("Exception_cpu(6);\n");
+ write_return_cycles("", 0);
+ out("}\n");
addcycles000(2);
- out("\tif ((uae_s32)dst < 0) {\n");
- out("\t\tsetchkundefinedflags(src, dst, %d);\n", curi->size);
- out("\t\tException_cpu(6);\n");
- write_return_cycles("\t\t", 0);
- out("\t}\n");
- out("\tsetchkundefinedflags(src, dst, %d);\n", curi->size);
+ out("if ((uae_s32)dst < 0) {\n");
+ out("setchkundefinedflags(src, dst, %d);\n", curi->size);
+ out("Exception_cpu(6);\n");
+ write_return_cycles("", 0);
+ out("}\n");
+ out("setchkundefinedflags(src, dst, %d);\n", curi->size);
fill_prefetch_next_t();
break;
case i_CHK2:
genamode (curi, curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 2, 0, 0);
fill_prefetch_0 ();
- out("\tuae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];\n");
+ out("uae_s32 upper,lower,reg = regs.regs[(extra >> 12) & 15];\n");
switch (curi->size) {
case sz_byte:
- out("\tlower = (uae_s32)(uae_s8)%s(dsta); upper = (uae_s32)(uae_s8)%s(dsta + 1);\n", srcb, srcb);
- out("\tif ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;\n");
+ out("lower = (uae_s32)(uae_s8)%s(dsta); upper = (uae_s32)(uae_s8)%s(dsta + 1);\n", srcb, srcb);
+ out("if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s8)reg;\n");
break;
case sz_word:
- out("\tlower = (uae_s32)(uae_s16)%s(dsta); upper = (uae_s32)(uae_s16)%s(dsta + 2);\n", srcw, srcw);
- out("\tif ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;\n");
+ out("lower = (uae_s32)(uae_s16)%s(dsta); upper = (uae_s32)(uae_s16)%s(dsta + 2);\n", srcw, srcw);
+ out("if ((extra & 0x8000) == 0) reg = (uae_s32)(uae_s16)reg;\n");
break;
case sz_long:
- out("\tlower = %s(dsta); upper = %s(dsta + 4);\n", srcl, srcl);
+ out("lower = %s(dsta); upper = %s(dsta + 4);\n", srcl, srcl);
break;
default:
term ();
}
- out("\tSET_CFLG(0);\n");
- out("\tSET_ZFLG(0);\n");
- out("\tsetchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : %d);\n", curi->size);
- out("\tif(upper == reg || lower == reg) {\n");
- out("\t\tSET_ZFLG(1);\n");
- out("\t}else{\n");
- out("\t\tif (lower <= upper && (reg < lower || reg > upper)) SET_CFLG(1);\n");
- out("\t\tif (lower > upper && reg > upper && reg < lower) SET_CFLG(1);\n");
- out("\t}\n");
- out("\tif ((extra & 0x800) && GET_CFLG()) {\n");
- out("\t\tException_cpu(6);\n");
- write_return_cycles("\t\t", 0);
- out("\t}\n");
+ out("SET_CFLG(0);\n");
+ out("SET_ZFLG(0);\n");
+ out("setchk2undefinedflags(lower, upper, reg, (extra & 0x8000) ? 2 : %d);\n", curi->size);
+ out("if(upper == reg || lower == reg) {\n");
+ out("SET_ZFLG(1);\n");
+ out("}else{\n");
+ out("if (lower <= upper && (reg < lower || reg > upper)) SET_CFLG(1);\n");
+ out("if (lower > upper && reg > upper && reg < lower) SET_CFLG(1);\n");
+ out("}\n");
+ out("if ((extra & 0x800) && GET_CFLG()) {\n");
+ out("Exception_cpu(6);\n");
+ write_return_cycles("", 0);
+ out("}\n");
break;
case i_ASR:
genamodedual (curi,
curi->smode, "srcreg", curi->size, "cnt", 1, 0,
curi->dmode, "dstreg", curi->size, "data", 1, GF_RMW);
switch (curi->size) {
- case sz_byte: out("\tuae_u32 val = (uae_u8)data;\n"); break;
- case sz_word: out("\tuae_u32 val = (uae_u16)data;\n"); break;
- case sz_long: out("\tuae_u32 val = data;\n"); break;
+ case sz_byte: out("uae_u32 val = (uae_u8)data;\n"); break;
+ case sz_word: out("uae_u32 val = (uae_u16)data;\n"); break;
+ case sz_long: out("uae_u32 val = data;\n"); break;
default: term ();
}
- out("\tCLEAR_CZNV();\n");
+ out("CLEAR_CZNV();\n");
if (curi->size == sz_long) {
- fill_prefetch_next_noopcodecopy("\t\tSET_NFLG(val & 0x8000);SET_ZFLG(!(val & 0xffff));\n");
+ fill_prefetch_next_noopcodecopy("SET_NFLG(val & 0x8000);SET_ZFLG(!(val & 0xffff));\n");
} else {
- fill_prefetch_next_noopcodecopy("\t\tSET_ZFLG(!(val & %s));SET_NFLG(val & %s);\n", bit_mask(curi->size), cmask(curi->size));
- }
- out("\tuae_u32 sign = (%s & val) >> %d;\n", cmask (curi->size), bit_size (curi->size) - 1);
- out("\tint ccnt = cnt & 63;\n");
- out("\tcnt &= 63;\n");
- out("\tif (cnt >= %d) {\n", bit_size (curi->size));
- out("\t\tval = %s & (uae_u32)(0 - sign);\n", bit_mask (curi->size));
- out("\t\tSET_CFLG (sign);\n");
+ fill_prefetch_next_noopcodecopy("SET_ZFLG(!(val & %s));SET_NFLG(val & %s);\n", bit_mask(curi->size), cmask(curi->size));
+ }
+ out("uae_u32 sign = (%s & val) >> %d;\n", cmask (curi->size), bit_size (curi->size) - 1);
+ out("int ccnt = cnt & 63;\n");
+ out("cnt &= 63;\n");
+ out("if (cnt >= %d) {\n", bit_size (curi->size));
+ out("val = %s & (uae_u32)(0 - sign);\n", bit_mask (curi->size));
+ out("SET_CFLG (sign);\n");
duplicate_carry (1);
if (source_is_imm1_8 (curi))
- out("\t} else {\n");
+ out("} else {\n");
else
- out("\t} else if (cnt > 0) {\n");
- out("\t\tval >>= cnt - 1;\n");
- out("\t\tSET_CFLG (val & 1);\n");
+ out("} else if (cnt > 0) {\n");
+ out("val >>= cnt - 1;\n");
+ out("SET_CFLG (val & 1);\n");
duplicate_carry (1);
- out("\t\tval >>= 1;\n");
- out("\t\tval |= (%s << (%d - cnt)) & (uae_u32)(0 - sign);\n",
+ out("val >>= 1;\n");
+ out("val |= (%s << (%d - cnt)) & (uae_u32)(0 - sign);\n",
bit_mask (curi->size),
bit_size (curi->size));
- out("\t\tval &= %s;\n", bit_mask (curi->size));
- out("\t}\n");
+ out("val &= %s;\n", bit_mask (curi->size));
+ out("}\n");
genflags (flag_logical_noclobber, curi->size, "val", "", "");
shift_ce (curi->dmode, curi->size);
genastore ("val", curi->dmode, "dstreg", curi->size, "data");
curi->smode, "srcreg", curi->size, "cnt", 1, 0,
curi->dmode, "dstreg", curi->size, "data", 1, GF_RMW);
switch (curi->size) {
- case sz_byte: out("\tuae_u32 val = (uae_u8)data;\n"); break;
- case sz_word: out("\tuae_u32 val = (uae_u16)data;\n"); break;
- case sz_long: out("\tuae_u32 val = data;\n"); break;
+ case sz_byte: out("uae_u32 val = (uae_u8)data;\n"); break;
+ case sz_word: out("uae_u32 val = (uae_u16)data;\n"); break;
+ case sz_long: out("uae_u32 val = data;\n"); break;
default: term ();
}
- out("\tCLEAR_CZNV();\n");
+ out("CLEAR_CZNV();\n");
if (curi->size == sz_long) {
- fill_prefetch_next_noopcodecopy("\t\tSET_NFLG(val & 0x8000);SET_ZFLG(!(val & 0xffff));\n");
+ fill_prefetch_next_noopcodecopy("SET_NFLG(val & 0x8000);SET_ZFLG(!(val & 0xffff));\n");
} else {
- fill_prefetch_next_noopcodecopy("\t\tSET_ZFLG(!(val & %s));SET_NFLG(val & %s);\n", bit_mask(curi->size), cmask(curi->size));
+ fill_prefetch_next_noopcodecopy("SET_ZFLG(!(val & %s));SET_NFLG(val & %s);\n", bit_mask(curi->size), cmask(curi->size));
}
- out("\tint ccnt = cnt & 63;\n");
- out("\tcnt &= 63;\n");
- out("\tif (cnt >= %d) {\n", bit_size (curi->size));
- out("\t\tSET_VFLG (val != 0);\n");
- out("\t\tSET_CFLG (cnt == %d ? val & 1 : 0);\n",
+ out("int ccnt = cnt & 63;\n");
+ out("cnt &= 63;\n");
+ out("if (cnt >= %d) {\n", bit_size (curi->size));
+ out("SET_VFLG (val != 0);\n");
+ out("SET_CFLG (cnt == %d ? val & 1 : 0);\n",
bit_size (curi->size));
duplicate_carry (1);
- out("\t\tval = 0;\n");
+ out("val = 0;\n");
if (source_is_imm1_8 (curi))
- out("\t} else {\n");
+ out("} else {\n");
else
- out("\t} else if (cnt > 0) {\n");
- out("\t\tuae_u32 mask = (%s << (%d - cnt)) & %s;\n",
+ out("} else if (cnt > 0) {\n");
+ out("uae_u32 mask = (%s << (%d - cnt)) & %s;\n",
bit_mask (curi->size),
bit_size (curi->size) - 1,
bit_mask (curi->size));
- out("\t\tSET_VFLG ((val & mask) != mask && (val & mask) != 0);\n");
- out("\t\tval <<= cnt - 1;\n");
- out("\t\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1);
+ out("SET_VFLG ((val & mask) != mask && (val & mask) != 0);\n");
+ out("val <<= cnt - 1;\n");
+ out("SET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1);
duplicate_carry (1);
- out("\t\tval <<= 1;\n");
- out("\t\tval &= %s;\n", bit_mask (curi->size));
- out("\t}\n");
+ out("val <<= 1;\n");
+ out("val &= %s;\n", bit_mask (curi->size));
+ out("}\n");
genflags (flag_logical_noclobber, curi->size, "val", "", "");
shift_ce (curi->dmode, curi->size);
genastore ("val", curi->dmode, "dstreg", curi->size, "data");
curi->smode, "srcreg", curi->size, "cnt", 1, 0,
curi->dmode, "dstreg", curi->size, "data", 1, GF_RMW);
switch (curi->size) {
- case sz_byte: out("\tuae_u32 val = (uae_u8)data;\n"); break;
- case sz_word: out("\tuae_u32 val = (uae_u16)data;\n"); break;
- case sz_long: out("\tuae_u32 val = data;\n"); break;
+ case sz_byte: out("uae_u32 val = (uae_u8)data;\n"); break;
+ case sz_word: out("uae_u32 val = (uae_u16)data;\n"); break;
+ case sz_long: out("uae_u32 val = data;\n"); break;
default: term ();
}
- out("\tCLEAR_CZNV();\n");
+ out("CLEAR_CZNV();\n");
if (curi->size == sz_long) {
- fill_prefetch_next_noopcodecopy("\t\tSET_NFLG(val & 0x8000);SET_ZFLG(!(val & 0xffff));\n");
+ fill_prefetch_next_noopcodecopy("SET_NFLG(val & 0x8000);SET_ZFLG(!(val & 0xffff));\n");
} else {
- fill_prefetch_next_noopcodecopy("\t\tSET_ZFLG(!(val & %s));SET_NFLG(val & %s);\n", bit_mask(curi->size), cmask(curi->size));
+ fill_prefetch_next_noopcodecopy("SET_ZFLG(!(val & %s));SET_NFLG(val & %s);\n", bit_mask(curi->size), cmask(curi->size));
}
- out("\tint ccnt = cnt & 63;\n");
- out("\tcnt &= 63;\n");
- out("\tif (cnt >= %d) {\n", bit_size (curi->size));
- out("\t\tSET_CFLG ((cnt == %d) & (val >> %d));\n",
+ out("int ccnt = cnt & 63;\n");
+ out("cnt &= 63;\n");
+ out("if (cnt >= %d) {\n", bit_size (curi->size));
+ out("SET_CFLG ((cnt == %d) & (val >> %d));\n",
bit_size (curi->size), bit_size (curi->size) - 1);
duplicate_carry (1);
- out("\t\tval = 0;\n");
+ out("val = 0;\n");
if (source_is_imm1_8 (curi))
- out("\t} else {\n");
+ out("} else {\n");
else
- out("\t} else if (cnt > 0) {\n");
- out("\t\tval >>= cnt - 1;\n");
- out("\t\tSET_CFLG (val & 1);\n");
+ out("} else if (cnt > 0) {\n");
+ out("val >>= cnt - 1;\n");
+ out("SET_CFLG (val & 1);\n");
duplicate_carry (1);
- out("\t\tval >>= 1;\n");
- out("\t}\n");
+ out("val >>= 1;\n");
+ out("}\n");
genflags (flag_logical_noclobber, curi->size, "val", "", "");
shift_ce (curi->dmode, curi->size);
genastore ("val", curi->dmode, "dstreg", curi->size, "data");
curi->smode, "srcreg", curi->size, "cnt", 1, 0,
curi->dmode, "dstreg", curi->size, "data", 1, GF_RMW);
switch (curi->size) {
- case sz_byte: out("\tuae_u32 val = (uae_u8)data;\n"); break;
- case sz_word: out("\tuae_u32 val = (uae_u16)data;\n"); break;
- case sz_long: out("\tuae_u32 val = data;\n"); break;
+ case sz_byte: out("uae_u32 val = (uae_u8)data;\n"); break;
+ case sz_word: out("uae_u32 val = (uae_u16)data;\n"); break;
+ case sz_long: out("uae_u32 val = data;\n"); break;
default: term ();
}
- out("\tCLEAR_CZNV();\n");
+ out("CLEAR_CZNV();\n");
if (curi->size == sz_long) {
- fill_prefetch_next_noopcodecopy("\t\tSET_NFLG(val & 0x8000);SET_ZFLG(!(val & 0xffff));\n");
+ fill_prefetch_next_noopcodecopy("SET_NFLG(val & 0x8000);SET_ZFLG(!(val & 0xffff));\n");
} else {
- fill_prefetch_next_noopcodecopy("\t\tSET_ZFLG(!(val & %s));SET_NFLG(val & %s);\n", bit_mask(curi->size), cmask(curi->size));
+ fill_prefetch_next_noopcodecopy("SET_ZFLG(!(val & %s));SET_NFLG(val & %s);\n", bit_mask(curi->size), cmask(curi->size));
}
- out("\tint ccnt = cnt & 63;\n");
- out("\tcnt &= 63;\n");
- out("\tif (cnt >= %d) {\n", bit_size (curi->size));
- out("\t\tSET_CFLG (cnt == %d ? val & 1 : 0);\n", bit_size(curi->size));
+ out("int ccnt = cnt & 63;\n");
+ out("cnt &= 63;\n");
+ out("if (cnt >= %d) {\n", bit_size (curi->size));
+ out("SET_CFLG (cnt == %d ? val & 1 : 0);\n", bit_size(curi->size));
duplicate_carry(1);
- out("\t\tval = 0;\n");
+ out("val = 0;\n");
if (source_is_imm1_8(curi))
- out("\t} else {\n");
+ out("} else {\n");
else
- out("\t} else if (cnt > 0) {\n");
- out("\t\tval <<= (cnt - 1);\n");
- out("\t\tSET_CFLG((val & %s) >> %d);\n", cmask(curi->size), bit_size(curi->size) - 1);
+ out("} else if (cnt > 0) {\n");
+ out("val <<= (cnt - 1);\n");
+ out("SET_CFLG((val & %s) >> %d);\n", cmask(curi->size), bit_size(curi->size) - 1);
duplicate_carry (1);
- out("\t\tval <<= 1;\n");
- out("\tval &= %s;\n", bit_mask (curi->size));
- out("\t}\n");
+ out("val <<= 1;\n");
+ out("val &= %s;\n", bit_mask (curi->size));
+ out("}\n");
genflags(flag_logical_noclobber, curi->size, "val", "", "");
shift_ce(curi->dmode, curi->size);
genastore("val", curi->dmode, "dstreg", curi->size, "data");
curi->smode, "srcreg", curi->size, "cnt", 1, 0,
curi->dmode, "dstreg", curi->size, "data", 1, GF_RMW);
switch (curi->size) {
- case sz_byte: out("\tuae_u32 val = (uae_u8)data;\n"); break;
- case sz_word: out("\tuae_u32 val = (uae_u16)data;\n"); break;
- case sz_long: out("\tuae_u32 val = data;\n"); break;
+ case sz_byte: out("uae_u32 val = (uae_u8)data;\n"); break;
+ case sz_word: out("uae_u32 val = (uae_u16)data;\n"); break;
+ case sz_long: out("uae_u32 val = data;\n"); break;
default: term ();
}
- out("\tCLEAR_CZNV();\n");
+ out("CLEAR_CZNV();\n");
if (curi->size == sz_long) {
- fill_prefetch_next_noopcodecopy("\t\tSET_NFLG(val & 0x8000);SET_ZFLG(!(val & 0xffff));\n");
+ fill_prefetch_next_noopcodecopy("SET_NFLG(val & 0x8000);SET_ZFLG(!(val & 0xffff));\n");
} else {
- fill_prefetch_next_noopcodecopy("\t\tSET_ZFLG(!(val & %s));SET_NFLG(val & %s);\n", bit_mask(curi->size), cmask(curi->size));
+ fill_prefetch_next_noopcodecopy("SET_ZFLG(!(val & %s));SET_NFLG(val & %s);\n", bit_mask(curi->size), cmask(curi->size));
}
- out("\tint ccnt = cnt & 63;\n");
- out("\tcnt &= 63;\n");
+ out("int ccnt = cnt & 63;\n");
+ out("cnt &= 63;\n");
if (source_is_imm1_8 (curi))
out("{");
else
- out("\tif (cnt > 0) {\n");
- out("\tuae_u32 loval;\n");
- out("\tcnt &= %d;\n", bit_size (curi->size) - 1);
- out("\tloval = val >> (%d - cnt);\n", bit_size (curi->size));
- out("\tval <<= cnt;\n");
- out("\tval |= loval;\n");
- out("\tval &= %s;\n", bit_mask (curi->size));
- out("\tSET_CFLG (val & 1);\n");
+ out("if (cnt > 0) {\n");
+ out("uae_u32 loval;\n");
+ out("cnt &= %d;\n", bit_size (curi->size) - 1);
+ out("loval = val >> (%d - cnt);\n", bit_size (curi->size));
+ out("val <<= cnt;\n");
+ out("val |= loval;\n");
+ out("val &= %s;\n", bit_mask (curi->size));
+ out("SET_CFLG (val & 1);\n");
out("}\n");
genflags (flag_logical_noclobber, curi->size, "val", "", "");
shift_ce (curi->dmode, curi->size);
curi->smode, "srcreg", curi->size, "cnt", 1, 0,
curi->dmode, "dstreg", curi->size, "data", 1, GF_RMW);
switch (curi->size) {
- case sz_byte: out("\tuae_u32 val = (uae_u8)data;\n"); break;
- case sz_word: out("\tuae_u32 val = (uae_u16)data;\n"); break;
- case sz_long: out("\tuae_u32 val = data;\n"); break;
+ case sz_byte: out("uae_u32 val = (uae_u8)data;\n"); break;
+ case sz_word: out("uae_u32 val = (uae_u16)data;\n"); break;
+ case sz_long: out("uae_u32 val = data;\n"); break;
default: term ();
}
- out("\tCLEAR_CZNV();\n");
+ out("CLEAR_CZNV();\n");
if (curi->size == sz_long) {
- fill_prefetch_next_noopcodecopy("\t\tSET_NFLG(val & 0x8000);SET_ZFLG(!(val & 0xffff));\n");
+ fill_prefetch_next_noopcodecopy("SET_NFLG(val & 0x8000);SET_ZFLG(!(val & 0xffff));\n");
} else {
- fill_prefetch_next_noopcodecopy("\t\tSET_ZFLG(!(val & %s));SET_NFLG(val & %s);\n", bit_mask(curi->size), cmask(curi->size));
+ fill_prefetch_next_noopcodecopy("SET_ZFLG(!(val & %s));SET_NFLG(val & %s);\n", bit_mask(curi->size), cmask(curi->size));
}
- out("\tint ccnt = cnt & 63;\n");
- out("\tcnt &= 63;\n");
+ out("int ccnt = cnt & 63;\n");
+ out("cnt &= 63;\n");
if (source_is_imm1_8 (curi))
out("{");
else
- out("\tif (cnt > 0) {");
- out("\tuae_u32 hival;\n");
- out("\tcnt &= %d;\n", bit_size (curi->size) - 1);
- out("\thival = val << (%d - cnt);\n", bit_size (curi->size));
- out("\tval >>= cnt;\n");
- out("\tval |= hival;\n");
- out("\tval &= %s;\n", bit_mask (curi->size));
- out("\tSET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1);
- out("\t}\n");
+ out("if (cnt > 0) {");
+ out("uae_u32 hival;\n");
+ out("cnt &= %d;\n", bit_size (curi->size) - 1);
+ out("hival = val << (%d - cnt);\n", bit_size (curi->size));
+ out("val >>= cnt;\n");
+ out("val |= hival;\n");
+ out("val &= %s;\n", bit_mask (curi->size));
+ out("SET_CFLG ((val & %s) >> %d);\n", cmask (curi->size), bit_size (curi->size) - 1);
+ out("}\n");
genflags (flag_logical_noclobber, curi->size, "val", "", "");
shift_ce (curi->dmode, curi->size);
genastore ("val", curi->dmode, "dstreg", curi->size, "data");
curi->smode, "srcreg", curi->size, "cnt", 1, 0,
curi->dmode, "dstreg", curi->size, "data", 1, GF_RMW);
switch (curi->size) {
- case sz_byte: out("\tuae_u32 val = (uae_u8)data;\n"); break;
- case sz_word: out("\tuae_u32 val = (uae_u16)data;\n"); break;
- case sz_long: out("\tuae_u32 val = data;\n"); break;
+ case sz_byte: out("uae_u32 val = (uae_u8)data;\n"); break;
+ case sz_word: out("uae_u32 val = (uae_u16)data;\n"); break;
+ case sz_long: out("uae_u32 val = data;\n"); break;
default: term ();
}
- out("\tCLEAR_CZNV();\n");
+ out("CLEAR_CZNV();\n");
if (curi->size == sz_long) {
- fill_prefetch_next_noopcodecopy("\t\tSET_NFLG(val & 0x8000);SET_ZFLG(!(val & 0xffff));SET_CFLG(GET_XFLG());\n");
+ fill_prefetch_next_noopcodecopy("SET_NFLG(val & 0x8000);SET_ZFLG(!(val & 0xffff));SET_CFLG(GET_XFLG());\n");
} else {
- fill_prefetch_next_noopcodecopy("\t\tSET_ZFLG(!(val & %s));SET_NFLG(val & %s);SET_CFLG(GET_XFLG());\n", bit_mask(curi->size), cmask(curi->size));
+ fill_prefetch_next_noopcodecopy("SET_ZFLG(!(val & %s));SET_NFLG(val & %s);SET_CFLG(GET_XFLG());\n", bit_mask(curi->size), cmask(curi->size));
}
- out("\tint ccnt = cnt & 63;\n");
- out("\tcnt &= 63;\n");
+ out("int ccnt = cnt & 63;\n");
+ out("cnt &= 63;\n");
if (source_is_imm1_8 (curi))
out("{");
else {
force_range_for_rox ("cnt", curi->size);
- out("\tif (cnt > 0) {\n");
- }
- out("\tcnt--;\n");
- out("\t{\n\tuae_u32 carry;\n");
- out("\tuae_u32 loval = val >> (%d - cnt);\n", bit_size (curi->size) - 1);
- out("\tcarry = loval & 1;\n");
- out("\tval = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);\n");
- out("\tSET_XFLG (carry);\n");
- out("\tval &= %s;\n", bit_mask (curi->size));
- out("\t} }\n");
- out("\tSET_CFLG (GET_XFLG ());\n");
+ out("if (cnt > 0) {\n");
+ }
+ out("cnt--;\n");
+ out("{\nuae_u32 carry;\n");
+ out("uae_u32 loval = val >> (%d - cnt);\n", bit_size (curi->size) - 1);
+ out("carry = loval & 1;\n");
+ out("val = (((val << 1) | GET_XFLG ()) << cnt) | (loval >> 1);\n");
+ out("SET_XFLG (carry);\n");
+ out("val &= %s;\n", bit_mask (curi->size));
+ out("} }\n");
+ out("SET_CFLG (GET_XFLG ());\n");
genflags (flag_logical_noclobber, curi->size, "val", "", "");
shift_ce (curi->dmode, curi->size);
genastore ("val", curi->dmode, "dstreg", curi->size, "data");
curi->smode, "srcreg", curi->size, "cnt", 1, 0,
curi->dmode, "dstreg", curi->size, "data", 1, GF_RMW);
switch (curi->size) {
- case sz_byte: out("\tuae_u32 val = (uae_u8)data;\n"); break;
- case sz_word: out("\tuae_u32 val = (uae_u16)data;\n"); break;
- case sz_long: out("\tuae_u32 val = data;\n"); break;
+ case sz_byte: out("uae_u32 val = (uae_u8)data;\n"); break;
+ case sz_word: out("uae_u32 val = (uae_u16)data;\n"); break;
+ case sz_long: out("uae_u32 val = data;\n"); break;
default: term ();
}
- out("\tCLEAR_CZNV ();\n");
+ out("CLEAR_CZNV ();\n");
if (curi->size == sz_long) {
- fill_prefetch_next_noopcodecopy("\t\tSET_NFLG(val & 0x8000);SET_ZFLG(!(val & 0xffff));SET_CFLG(GET_XFLG());\n");
+ fill_prefetch_next_noopcodecopy("SET_NFLG(val & 0x8000);SET_ZFLG(!(val & 0xffff));SET_CFLG(GET_XFLG());\n");
} else {
- fill_prefetch_next_noopcodecopy("\t\tSET_ZFLG(!(val & %s));SET_NFLG(val & %s);SET_CFLG(GET_XFLG());\n", bit_mask(curi->size), cmask(curi->size));
+ fill_prefetch_next_noopcodecopy("SET_ZFLG(!(val & %s));SET_NFLG(val & %s);SET_CFLG(GET_XFLG());\n", bit_mask(curi->size), cmask(curi->size));
}
- out("\tint ccnt = cnt & 63;\n");
- out("\tcnt &= 63;\n");
+ out("int ccnt = cnt & 63;\n");
+ out("cnt &= 63;\n");
if (source_is_imm1_8 (curi))
out("{");
else {
force_range_for_rox ("cnt", curi->size);
- out("\tif (cnt > 0) {\n");
- }
- out("\tcnt--;\n");
- out("\t{\n\tuae_u32 carry;\n");
- out("\tuae_u32 hival = (val << 1) | GET_XFLG ();\n");
- out("\thival <<= (%d - cnt);\n", bit_size (curi->size) - 1);
- out("\tval >>= cnt;\n");
- out("\tcarry = val & 1;\n");
- out("\tval >>= 1;\n");
- out("\tval |= hival;\n");
- out("\tSET_XFLG (carry);\n");
- out("\tval &= %s;\n", bit_mask (curi->size));
- out("\t} }\n");
- out("\tSET_CFLG (GET_XFLG ());\n");
+ out("if (cnt > 0) {\n");
+ }
+ out("cnt--;\n");
+ out("{\nuae_u32 carry;\n");
+ out("uae_u32 hival = (val << 1) | GET_XFLG ();\n");
+ out("hival <<= (%d - cnt);\n", bit_size (curi->size) - 1);
+ out("val >>= cnt;\n");
+ out("carry = val & 1;\n");
+ out("val >>= 1;\n");
+ out("val |= hival;\n");
+ out("SET_XFLG (carry);\n");
+ out("val &= %s;\n", bit_mask (curi->size));
+ out("} }\n");
+ out("SET_CFLG (GET_XFLG ());\n");
genflags (flag_logical_noclobber, curi->size, "val", "", "");
shift_ce (curi->dmode, curi->size);
genastore ("val", curi->dmode, "dstreg", curi->size, "data");
case i_ASRW:
genamode (curi, curi->smode, "srcreg", curi->size, "data", 1, 0, GF_RMW);
switch (curi->size) {
- case sz_byte: out("\tuae_u32 val = (uae_u8)data;\n"); break;
- case sz_word: out("\tuae_u32 val = (uae_u16)data;\n"); break;
- case sz_long: out("\tuae_u32 val = data;\n"); break;
+ case sz_byte: out("uae_u32 val = (uae_u8)data;\n"); break;
+ case sz_word: out("uae_u32 val = (uae_u16)data;\n"); break;
+ case sz_long: out("uae_u32 val = data;\n"); break;
default: term ();
}
- fill_prefetch_next_noopcodecopy("\t\tCLEAR_CZNV();SET_CFLG(val & 1);SET_ZFLG(!(val >> 1));SET_NFLG(val & 0x8000);SET_XFLG(GET_CFLG());\n");
- out("\tuae_u32 sign = %s & val;\n", cmask (curi->size));
- out("\tuae_u32 cflg = val & 1;\n");
- out("\tval = (val >> 1) | sign;\n");
+ fill_prefetch_next_noopcodecopy("CLEAR_CZNV();SET_CFLG(val & 1);SET_ZFLG(!(val >> 1));SET_NFLG(val & 0x8000);SET_XFLG(GET_CFLG());\n");
+ out("uae_u32 sign = %s & val;\n", cmask (curi->size));
+ out("uae_u32 cflg = val & 1;\n");
+ out("val = (val >> 1) | sign;\n");
genflags (flag_logical, curi->size, "val", "", "");
- out("\tSET_CFLG (cflg);\n");
+ out("SET_CFLG (cflg);\n");
duplicate_carry (0);
genastore ("val", curi->smode, "srcreg", curi->size, "data");
loopmodeextra = 2;
case i_ASLW:
genamode (curi, curi->smode, "srcreg", curi->size, "data", 1, 0, GF_RMW);
switch (curi->size) {
- case sz_byte: out("\tuae_u32 val = (uae_u8)data;\n"); break;
- case sz_word: out("\tuae_u32 val = (uae_u16)data;\n"); break;
- case sz_long: out("\tuae_u32 val = data;\n"); break;
+ case sz_byte: out("uae_u32 val = (uae_u8)data;\n"); break;
+ case sz_word: out("uae_u32 val = (uae_u16)data;\n"); break;
+ case sz_long: out("uae_u32 val = data;\n"); break;
default: term ();
}
- fill_prefetch_next_noopcodecopy("\t\tCLEAR_CZNV();SET_CFLG(val & %s);SET_ZFLG(!((val << 1) & 0x7fff));SET_NFLG(val & 0x4000);SET_XFLG(GET_CFLG());SET_VFLG((val & 0x8000) != ((val << 1) & 0x8000));\n", cmask(curi->size));
- out("\tuae_u32 sign = %s & val;\n", cmask (curi->size));
- out("\tuae_u32 sign2;\n");
- out("\tval <<= 1;\n");
+ fill_prefetch_next_noopcodecopy("CLEAR_CZNV();SET_CFLG(val & %s);SET_ZFLG(!((val << 1) & 0x7fff));SET_NFLG(val & 0x4000);SET_XFLG(GET_CFLG());SET_VFLG((val & 0x8000) != ((val << 1) & 0x8000));\n", cmask(curi->size));
+ out("uae_u32 sign = %s & val;\n", cmask (curi->size));
+ out("uae_u32 sign2;\n");
+ out("val <<= 1;\n");
genflags (flag_logical, curi->size, "val", "", "");
- out("\tsign2 = %s & val;\n", cmask (curi->size));
- out("\tSET_CFLG (sign != 0);\n");
+ out("sign2 = %s & val;\n", cmask (curi->size));
+ out("SET_CFLG (sign != 0);\n");
duplicate_carry (0);
- out("\tSET_VFLG (GET_VFLG () | (sign2 != sign));\n");
+ out("SET_VFLG (GET_VFLG () | (sign2 != sign));\n");
genastore ("val", curi->smode, "srcreg", curi->size, "data");
loopmodeextra = 2;
break;
case i_LSRW:
genamode (curi, curi->smode, "srcreg", curi->size, "data", 1, 0, GF_RMW);
switch (curi->size) {
- case sz_byte: out("\tuae_u32 val = (uae_u8)data;\n"); break;
- case sz_word: out("\tuae_u32 val = (uae_u16)data;\n"); break;
- case sz_long: out("\tuae_u32 val = data;\n"); break;
+ case sz_byte: out("uae_u32 val = (uae_u8)data;\n"); break;
+ case sz_word: out("uae_u32 val = (uae_u16)data;\n"); break;
+ case sz_long: out("uae_u32 val = data;\n"); break;
default: term ();
}
- fill_prefetch_next_noopcodecopy("\t\tCLEAR_CZNV();SET_CFLG(val & 1);SET_ZFLG(!(val >> 1));SET_NFLG(0);SET_XFLG(GET_CFLG());\n");
- out("\tuae_u32 carry = val & 1;\n");
- out("\tval >>= 1;\n");
+ fill_prefetch_next_noopcodecopy("CLEAR_CZNV();SET_CFLG(val & 1);SET_ZFLG(!(val >> 1));SET_NFLG(0);SET_XFLG(GET_CFLG());\n");
+ out("uae_u32 carry = val & 1;\n");
+ out("val >>= 1;\n");
genflags (flag_logical, curi->size, "val", "", "");
- out("\tSET_CFLG (carry);\n");
+ out("SET_CFLG (carry);\n");
duplicate_carry (0);
genastore ("val", curi->smode, "srcreg", curi->size, "data");
loopmodeextra = 2;
case i_LSLW:
genamode (curi, curi->smode, "srcreg", curi->size, "data", 1, 0, GF_RMW);
switch (curi->size) {
- case sz_byte: out("\tuae_u8 val = data;\n"); break;
- case sz_word: out("\tuae_u16 val = data;\n"); break;
- case sz_long: out("\tuae_u32 val = data;\n"); break;
+ case sz_byte: out("uae_u8 val = data;\n"); break;
+ case sz_word: out("uae_u16 val = data;\n"); break;
+ case sz_long: out("uae_u32 val = data;\n"); break;
default: term ();
}
- fill_prefetch_next_noopcodecopy("\t\tCLEAR_CZNV();SET_CFLG(val & %s);SET_ZFLG(!(val << 1));SET_NFLG(val & 0x4000);SET_XFLG(GET_CFLG());\n", cmask(curi->size));
- out("\tuae_u32 carry = val & %s;\n", cmask (curi->size));
- out("\tval <<= 1;\n");
+ fill_prefetch_next_noopcodecopy("CLEAR_CZNV();SET_CFLG(val & %s);SET_ZFLG(!(val << 1));SET_NFLG(val & 0x4000);SET_XFLG(GET_CFLG());\n", cmask(curi->size));
+ out("uae_u32 carry = val & %s;\n", cmask (curi->size));
+ out("val <<= 1;\n");
genflags (flag_logical, curi->size, "val", "", "");
- out("\tSET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
+ out("SET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
duplicate_carry (0);
genastore ("val", curi->smode, "srcreg", curi->size, "data");
loopmodeextra = 2;
case i_ROLW:
genamode (curi, curi->smode, "srcreg", curi->size, "data", 1, 0, GF_RMW);
switch (curi->size) {
- case sz_byte: out("\tuae_u8 val = data;\n"); break;
- case sz_word: out("\tuae_u16 val = data;\n"); break;
- case sz_long: out("\tuae_u32 val = data;\n"); break;
+ case sz_byte: out("uae_u8 val = data;\n"); break;
+ case sz_word: out("uae_u16 val = data;\n"); break;
+ case sz_long: out("uae_u32 val = data;\n"); break;
default: term ();
}
- fill_prefetch_next_noopcodecopy("\t\tCLEAR_CZNV();SET_CFLG(val & %s);SET_ZFLG(!val);SET_NFLG(val & 0x4000);\n", cmask(curi->size));
- out("\tuae_u32 carry = val & %s;\n", cmask (curi->size));
- out("\tval <<= 1;\n");
- out("\tif (carry) val |= 1;\n");
+ fill_prefetch_next_noopcodecopy("CLEAR_CZNV();SET_CFLG(val & %s);SET_ZFLG(!val);SET_NFLG(val & 0x4000);\n", cmask(curi->size));
+ out("uae_u32 carry = val & %s;\n", cmask (curi->size));
+ out("val <<= 1;\n");
+ out("if (carry) val |= 1;\n");
genflags (flag_logical, curi->size, "val", "", "");
- out("\tSET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
+ out("SET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
genastore ("val", curi->smode, "srcreg", curi->size, "data");
loopmodeextra = 2;
break;
case i_RORW:
genamode (curi, curi->smode, "srcreg", curi->size, "data", 1, 0, GF_RMW);
switch (curi->size) {
- case sz_byte: out("\tuae_u8 val = data;\n"); break;
- case sz_word: out("\tuae_u16 val = data;\n"); break;
- case sz_long: out("\tuae_u32 val = data;\n"); break;
+ case sz_byte: out("uae_u8 val = data;\n"); break;
+ case sz_word: out("uae_u16 val = data;\n"); break;
+ case sz_long: out("uae_u32 val = data;\n"); break;
default: term ();
}
- fill_prefetch_next_noopcodecopy("\t\tCLEAR_CZNV();SET_CFLG(val & 1);SET_ZFLG(!val);SET_NFLG(val & 0x0001);\n");
- out("\tuae_u32 carry = val & 1;\n");
- out("\tval >>= 1;\n");
- out("\tif (carry) val |= %s;\n", cmask (curi->size));
+ fill_prefetch_next_noopcodecopy("CLEAR_CZNV();SET_CFLG(val & 1);SET_ZFLG(!val);SET_NFLG(val & 0x0001);\n");
+ out("uae_u32 carry = val & 1;\n");
+ out("val >>= 1;\n");
+ out("if (carry) val |= %s;\n", cmask (curi->size));
genflags (flag_logical, curi->size, "val", "", "");
- out("\tSET_CFLG (carry);\n");
+ out("SET_CFLG (carry);\n");
genastore ("val", curi->smode, "srcreg", curi->size, "data");
loopmodeextra = 2;
break;
case i_ROXLW:
genamode (curi, curi->smode, "srcreg", curi->size, "data", 1, 0, GF_RMW);
switch (curi->size) {
- case sz_byte: out("\tuae_u8 val = data;\n"); break;
- case sz_word: out("\tuae_u16 val = data;\n"); break;
- case sz_long: out("\tuae_u32 val = data;\n"); break;
+ case sz_byte: out("uae_u8 val = data;\n"); break;
+ case sz_word: out("uae_u16 val = data;\n"); break;
+ case sz_long: out("uae_u32 val = data;\n"); break;
default: term ();
}
- fill_prefetch_next_noopcodecopy("\t\tCLEAR_CZNV();SET_CFLG(val & 0x8000);SET_ZFLG(!((val << 1) | GET_XFLG()));SET_NFLG(val & 0x4000);SET_XFLG(GET_CFLG());\n", cmask(curi->size));
- out("\tuae_u32 carry = val & %s;\n", cmask (curi->size));
- out("\tval <<= 1;\n");
- out("\tif (GET_XFLG ()) val |= 1;\n");
+ fill_prefetch_next_noopcodecopy("CLEAR_CZNV();SET_CFLG(val & 0x8000);SET_ZFLG(!((val << 1) | GET_XFLG()));SET_NFLG(val & 0x4000);SET_XFLG(GET_CFLG());\n", cmask(curi->size));
+ out("uae_u32 carry = val & %s;\n", cmask (curi->size));
+ out("val <<= 1;\n");
+ out("if (GET_XFLG ()) val |= 1;\n");
genflags (flag_logical, curi->size, "val", "", "");
- out("\tSET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
+ out("SET_CFLG (carry >> %d);\n", bit_size (curi->size) - 1);
duplicate_carry (0);
genastore ("val", curi->smode, "srcreg", curi->size, "data");
loopmodeextra = 2;
case i_ROXRW:
genamode (curi, curi->smode, "srcreg", curi->size, "data", 1, 0, GF_RMW);
switch (curi->size) {
- case sz_byte: out("\tuae_u8 val = data;\n"); break;
- case sz_word: out("\tuae_u16 val = data;\n"); break;
- case sz_long: out("\tuae_u32 val = data;\n"); break;
+ case sz_byte: out("uae_u8 val = data;\n"); break;
+ case sz_word: out("uae_u16 val = data;\n"); break;
+ case sz_long: out("uae_u32 val = data;\n"); break;
default: term ();
}
- fill_prefetch_next_noopcodecopy("\t\tCLEAR_CZNV();SET_CFLG(val & 1);SET_ZFLG(!((val >> 1) | GET_XFLG()));SET_NFLG(GET_XFLG());SET_XFLG(GET_CFLG());\n", cmask(curi->size));
- out("\tuae_u32 carry = val & 1;\n");
- out("\tval >>= 1;\n");
- out("\tif (GET_XFLG ()) val |= %s;\n", cmask (curi->size));
+ fill_prefetch_next_noopcodecopy("CLEAR_CZNV();SET_CFLG(val & 1);SET_ZFLG(!((val >> 1) | GET_XFLG()));SET_NFLG(GET_XFLG());SET_XFLG(GET_CFLG());\n", cmask(curi->size));
+ out("uae_u32 carry = val & 1;\n");
+ out("val >>= 1;\n");
+ out("if (GET_XFLG ()) val |= %s;\n", cmask (curi->size));
genflags (flag_logical, curi->size, "val", "", "");
- out("\tSET_CFLG (carry);\n");
+ out("SET_CFLG (carry);\n");
duplicate_carry (0);
genastore ("val", curi->smode, "srcreg", curi->size, "data");
loopmodeextra = 2;
break;
case i_MOVEC2:
if (cpu_level == 1) {
- out("\tif(!regs.s) {\n");
- out("\t\tException(8);\n");
- write_return_cycles_none("\t\t");
- out("\t}\n");
+ out("if(!regs.s) {\n");
+ out("Exception(8);\n");
+ write_return_cycles_none("");
+ out("}\n");
}
genamode(curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
fill_prefetch_next();
- out("\tint regno = (src >> 12) & 15;\n");
- out("\tuae_u32 *regp = regs.regs + regno;\n");
- out("\tif (!m68k_movec2(src & 0xFFF, regp)) {\n");
- write_return_cycles("\t\t", 0);
- out("\t}\n");
+ out("int regno = (src >> 12) & 15;\n");
+ out("uae_u32 *regp = regs.regs + regno;\n");
+ out("if (!m68k_movec2(src & 0xFFF, regp)) {\n");
+ write_return_cycles("", 0);
+ out("}\n");
addcycles000(4);
trace_t0_68040_only();
break;
case i_MOVE2C:
if (cpu_level == 1) {
- out("\tif(!regs.s) {\n");
- out("\t\tException(8);\n");
- write_return_cycles_none("\t\t");
- out("\t}\n");
+ out("if(!regs.s) {\n");
+ out("Exception(8);\n");
+ write_return_cycles_none("");
+ out("}\n");
}
genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
fill_prefetch_next ();
- out("\tint regno = (src >> 12) & 15;\n");
- out("\tuae_u32 *regp = regs.regs + regno;\n");
- out("\tif (!m68k_move2c(src & 0xFFF, regp)) {\n");
- write_return_cycles("\t\t", 0);
- out("\t}\n");
+ out("int regno = (src >> 12) & 15;\n");
+ out("uae_u32 *regp = regs.regs + regno;\n");
+ out("if (!m68k_move2c(src & 0xFFF, regp)) {\n");
+ write_return_cycles("", 0);
+ out("}\n");
addcycles000(2);
trace_t0_68040_only();
break;
genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_LRMW);
genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 1, 0, GF_LRMW);
if (cpu_level == 5 && curi->size > 0) {
- out("\tif ((dsta & %d) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {\n", curi->size == 1 ? 1 : 3);
+ out("if ((dsta & %d) && currprefs.int_no_unimplemented && get_cpu_model () == 68060) {\n", curi->size == 1 ? 1 : 3);
if (mmufixupcnt)
- out("\t\tcpu_restore_fixup();\n");
+ out("cpu_restore_fixup();\n");
sync_m68k_pc_noreset ();
- out("\t\top_unimpl (opcode);\n");
- write_return_cycles("\t\t", 0);
- out("\t}\n");
+ out("op_unimpl (opcode);\n");
+ write_return_cycles("", 0);
+ out("}\n");
}
fill_prefetch_0 ();
start_brace();
- out("\tint ru = (src >> 6) & 7;\n");
- out("\tint rc = src & 7;\n");
+ out("int ru = (src >> 6) & 7;\n");
+ out("int rc = src & 7;\n");
genflags (flag_cmp, curi->size, "newv", "m68k_dreg(regs, rc)", "dst");
gen_set_fault_pc (false, true);
- out("\tif (GET_ZFLG ()) {\n");
+ out("if (GET_ZFLG ()) {\n");
old_brace_level = n_braces;
start_brace();
genastore_cas ("(m68k_dreg(regs, ru))", curi->dmode, "dstreg", curi->size, "dst");
pop_braces(old_brace_level);
- out("\t} else {\n");
+ out("} else {\n");
start_brace();
get_prefetch_020 ();
if (cpu_level >= 4) {
// apparently 68040/060 needs to always write at the end of RMW cycle
- out("\t");
+ out("");
genastore_cas ("dst", curi->dmode, "dstreg", curi->size, "dst");
}
switch (curi->size) {
case sz_byte:
- out("\t\tm68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);\n");
+ out("m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xff) | (dst & 0xff);\n");
break;
case sz_word:
- out("\t\tm68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);\n");
+ out("m68k_dreg(regs, rc) = (m68k_dreg(regs, rc) & ~0xffff) | (dst & 0xffff);\n");
break;
default:
- out("\t\tm68k_dreg(regs, rc) = dst;\n");
+ out("m68k_dreg(regs, rc) = dst;\n");
break;
}
- out("\t}\n");
+ out("}\n");
pop_braces(old_brace_level);
trace_t0_68040_only();
}
break;
case i_CAS2:
genamode(curi, curi->smode, "srcreg", curi->size, "extra", 1, 0, GF_LRMW);
- out("\tuae_u32 rn1 = regs.regs[(extra >> 28) & 15];\n");
- out("\tuae_u32 rn2 = regs.regs[(extra >> 12) & 15];\n");
+ out("uae_u32 rn1 = regs.regs[(extra >> 28) & 15];\n");
+ out("uae_u32 rn2 = regs.regs[(extra >> 12) & 15];\n");
if (curi->size == sz_word) {
int old_brace_level = n_braces;
- out("\tuae_u16 dst1 = %s(rn1), dst2 = %s(rn2);\n", srcwlrmw, srcwlrmw);
+ out("uae_u16 dst1 = %s(rn1), dst2 = %s(rn2);\n", srcwlrmw, srcwlrmw);
genflags(flag_cmp, curi->size, "newv", "m68k_dreg(regs, (extra >> 16) & 7)", "dst1");
- out("\tif (GET_ZFLG ()) {\n");
+ out("if (GET_ZFLG ()) {\n");
genflags(flag_cmp, curi->size, "newv", "m68k_dreg(regs, extra & 7)", "dst2");
- out("\tif (GET_ZFLG ()) {\n");
- out("\t%s(rn1, m68k_dreg(regs, (extra >> 22) & 7));\n", dstwlrmw);
- out("\t%s(rn2, m68k_dreg(regs, (extra >> 6) & 7));\n", dstwlrmw);
- out("\t}}\n");
+ out("if (GET_ZFLG ()) {\n");
+ out("%s(rn1, m68k_dreg(regs, (extra >> 22) & 7));\n", dstwlrmw);
+ out("%s(rn2, m68k_dreg(regs, (extra >> 6) & 7));\n", dstwlrmw);
+ out("}}\n");
pop_braces(old_brace_level);
- out("\tif (! GET_ZFLG ()) {\n");
+ out("if (! GET_ZFLG ()) {\n");
if (cpu_level >= 4) {
// 68040: register update order swapped
- out("\tm68k_dreg(regs, (extra >> 16) & 7) = (m68k_dreg(regs, (extra >> 16) & 7) & ~0xffff) | (dst1 & 0xffff);\n");
- out("\tm68k_dreg(regs, (extra >> 0) & 7) = (m68k_dreg(regs, (extra >> 0) & 7) & ~0xffff) | (dst2 & 0xffff);\n");
+ out("m68k_dreg(regs, (extra >> 16) & 7) = (m68k_dreg(regs, (extra >> 16) & 7) & ~0xffff) | (dst1 & 0xffff);\n");
+ out("m68k_dreg(regs, (extra >> 0) & 7) = (m68k_dreg(regs, (extra >> 0) & 7) & ~0xffff) | (dst2 & 0xffff);\n");
} else {
- out("\tm68k_dreg(regs, (extra >> 0) & 7) = (m68k_dreg(regs, (extra >> 0) & 7) & ~0xffff) | (dst2 & 0xffff);\n");
- out("\tm68k_dreg(regs, (extra >> 16) & 7) = (m68k_dreg(regs, (extra >> 16) & 7) & ~0xffff) | (dst1 & 0xffff);\n");
+ out("m68k_dreg(regs, (extra >> 0) & 7) = (m68k_dreg(regs, (extra >> 0) & 7) & ~0xffff) | (dst2 & 0xffff);\n");
+ out("m68k_dreg(regs, (extra >> 16) & 7) = (m68k_dreg(regs, (extra >> 16) & 7) & ~0xffff) | (dst1 & 0xffff);\n");
}
- out("\t}\n");
+ out("}\n");
} else {
int old_brace_level = n_braces;
- out("\tuae_u32 dst1 = %s(rn1), dst2 = %s(rn2);\n", srcllrmw, srcllrmw);
+ out("uae_u32 dst1 = %s(rn1), dst2 = %s(rn2);\n", srcllrmw, srcllrmw);
genflags(flag_cmp, curi->size, "newv", "m68k_dreg(regs, (extra >> 16) & 7)", "dst1");
- out("\tif (GET_ZFLG ()) {\n");
+ out("if (GET_ZFLG ()) {\n");
genflags(flag_cmp, curi->size, "newv", "m68k_dreg(regs, extra & 7)", "dst2");
- out("\tif (GET_ZFLG ()) {\n");
- out("\t%s(rn1, m68k_dreg(regs, (extra >> 22) & 7));\n", dstllrmw);
- out("\t%s(rn2, m68k_dreg(regs, (extra >> 6) & 7));\n", dstllrmw);
- out("\t}}\n");
+ out("if (GET_ZFLG ()) {\n");
+ out("%s(rn1, m68k_dreg(regs, (extra >> 22) & 7));\n", dstllrmw);
+ out("%s(rn2, m68k_dreg(regs, (extra >> 6) & 7));\n", dstllrmw);
+ out("}}\n");
pop_braces(old_brace_level);
- out("\tif (! GET_ZFLG ()) {\n");
+ out("if (! GET_ZFLG ()) {\n");
if (cpu_level >= 4) {
// 68040: register update order swapped
- out("\tm68k_dreg(regs, (extra >> 16) & 7) = dst1;\n");
- out("\tm68k_dreg(regs, (extra >> 0) & 7) = dst2;\n");
+ out("m68k_dreg(regs, (extra >> 16) & 7) = dst1;\n");
+ out("m68k_dreg(regs, (extra >> 0) & 7) = dst2;\n");
} else {
- out("\tm68k_dreg(regs, (extra >> 0) & 7) = dst2;\n");
- out("\tm68k_dreg(regs, (extra >> 16) & 7) = dst1;\n");
+ out("m68k_dreg(regs, (extra >> 0) & 7) = dst2;\n");
+ out("m68k_dreg(regs, (extra >> 16) & 7) = dst1;\n");
}
- out("\t}\n");
+ out("}\n");
}
trace_t0_68040_only();
break;
int old_m68k_pc_total = m68k_pc_total;
push_ins_cnt();
// 68060 stores original value, 68010 MOVES.L also stores original value.
- out("\tuae_u32 src = regs.regs[(extra >> 12) & 15];\n");
+ out("uae_u32 src = regs.regs[(extra >> 12) & 15];\n");
genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 2, 0, cpu_level == 1 ? GF_NOFETCH : 0);
tail_ce020_done = false;
returntail(false);
did_prefetch = 0;
// Earlier models do -(an)/(an)+ EA calculation first
if (!(cpu_level == 5 || (curi->dmode != Aipi && curi->dmode != Apdi) || (cpu_level == 1 && curi->size == sz_long))) {
- out("\tsrc = regs.regs[(extra >> 12) & 15];\n");
+ out("src = regs.regs[(extra >> 12) & 15];\n");
}
genastore_fc ("src", curi->dmode, "dstreg", curi->size, "dst");
sync_m68k_pc();
out("} else {\n");
{
genamode(curi, curi->dmode, "dstreg", curi->size, "src", 1, 0, GF_FC | (cpu_level == 1 ? GF_NOFETCH : 0));
- out("\tif (extra & 0x8000) {\n");
+ out("if (extra & 0x8000) {\n");
switch (curi->size) {
- case sz_byte: out("\tm68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;\n"); break;
- case sz_word: out("\tm68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;\n"); break;
- case sz_long: out("\tm68k_areg(regs, (extra >> 12) & 7) = src;\n"); break;
+ case sz_byte: out("m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s8)src;\n"); break;
+ case sz_word: out("m68k_areg(regs, (extra >> 12) & 7) = (uae_s32)(uae_s16)src;\n"); break;
+ case sz_long: out("m68k_areg(regs, (extra >> 12) & 7) = src;\n"); break;
default: term();
}
- out("\t} else {\n");
+ out("} else {\n");
genastore("src", Dreg, "(extra >> 12) & 7", curi->size, "");
- out("\t}\n");
+ out("}\n");
sync_m68k_pc();
tail_ce020_done = false;
returntail(false);
case i_BKPT: /* only needed for hardware emulators */
sync_m68k_pc ();
addcycles000(4);
- out("\top_illg (opcode);\n");
+ out("op_illg (opcode);\n");
did_prefetch = -1;
break;
case i_CALLM: /* not present in 68030 */
sync_m68k_pc ();
- out("\top_illg (opcode);\n");
+ out("op_illg (opcode);\n");
did_prefetch = -1;
break;
case i_RTM: /* not present in 68030 */
sync_m68k_pc ();
- out("\top_illg (opcode);\n");
+ out("op_illg (opcode);\n");
did_prefetch = -1;
break;
case i_TRAPcc:
if (curi->smode != am_unknown && curi->smode != am_illg)
genamode (curi, curi->smode, "srcreg", curi->size, "dummy", 1, 0, 0);
fill_prefetch_0 ();
- out("\tif (cctrue(%d)) {\n", curi->cc);
- out("\t\tException_cpu(7);\n");
- write_return_cycles("\t\t", 0);
- out("\t}\n");
+ out("if (cctrue(%d)) {\n", curi->cc);
+ out("Exception_cpu(7);\n");
+ write_return_cycles("", 0);
+ out("}\n");
break;
case i_DIVL:
genamode (curi, curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
sync_m68k_pc ();
- out("\tif (!m68k_divl(opcode, dst, extra)) {\n");
+ out("if (!m68k_divl(opcode, dst, extra)) {\n");
if (mmufixupcnt)
- out("\t\tcpu_restore_fixup();\n");
- write_return_cycles("\t\t", 0);
- out("\t}\n");
+ out("cpu_restore_fixup();\n");
+ write_return_cycles("", 0);
+ out("}\n");
break;
case i_MULL:
genamode (curi, curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
genamode (curi, curi->dmode, "dstreg", curi->size, "dst", 1, 0, 0);
sync_m68k_pc ();
- out("\tif (!m68k_mull(opcode, dst, extra)) {\n");
+ out("if (!m68k_mull(opcode, dst, extra)) {\n");
if (mmufixupcnt)
- out("\t\tcpu_restore_fixup();\n");
- write_return_cycles("\t\t", 0);
- out("\t}\n");
+ out("cpu_restore_fixup();\n");
+ write_return_cycles("", 0);
+ out("}\n");
break;
case i_BFTST:
case i_BFEXTU:
genamode (curi, curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
genamode (curi, curi->dmode, "dstreg", sz_long, "dst", 2, 0, 0);
start_brace ();
- out("\tuae_u32 bdata[2];\n");
- out("\tuae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;\n");
- out("\tint width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;\n");
+ out("uae_u32 bdata[2];\n");
+ out("uae_s32 offset = extra & 0x800 ? m68k_dreg(regs, (extra >> 6) & 7) : (extra >> 6) & 0x1f;\n");
+ out("int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) -1) & 0x1f) +1;\n");
if (curi->mnemo == i_BFFFO)
- out("\tuae_u32 offset2 = offset;\n");
+ out("uae_u32 offset2 = offset;\n");
if (curi->dmode == Dreg) {
- out("\tuae_u32 tmp = m68k_dreg(regs, dstreg);\n");
- out("\toffset &= 0x1f;\n");
- out("\ttmp = (tmp << offset) | (tmp >> (32 - offset));\n");
- out("\tbdata[0] = tmp & ((1 << (32 - width)) - 1);\n");
+ out("uae_u32 tmp = m68k_dreg(regs, dstreg);\n");
+ out("offset &= 0x1f;\n");
+ out("tmp = (tmp << offset) | (tmp >> (32 - offset));\n");
+ out("bdata[0] = tmp & ((1 << (32 - width)) - 1);\n");
} else {
- out("\tuae_u32 tmp;\n");
- out("\tdsta += offset >> 3;\n");
- out("\ttmp = %s(dsta, bdata, offset, width);\n", getb);
+ out("uae_u32 tmp;\n");
+ out("dsta += offset >> 3;\n");
+ out("tmp = %s(dsta, bdata, offset, width);\n", getb);
}
- out("\tSET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);\n");
+ out("SET_NFLG_ALWAYS (((uae_s32)tmp) < 0 ? 1 : 0);\n");
if (curi->mnemo == i_BFEXTS)
- out("\ttmp = (uae_s32)tmp >> (32 - width);\n");
+ out("tmp = (uae_s32)tmp >> (32 - width);\n");
else
- out("\ttmp >>= (32 - width);\n");
- out("\tSET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);\n");
+ out("tmp >>= (32 - width);\n");
+ out("SET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);\n");
switch (curi->mnemo) {
case i_BFTST:
break;
case i_BFEXTU:
case i_BFEXTS:
- out("\tm68k_dreg(regs, (extra >> 12) & 7) = tmp;\n");
+ out("m68k_dreg(regs, (extra >> 12) & 7) = tmp;\n");
break;
case i_BFCHG:
- out("\ttmp = tmp ^ (0xffffffffu >> (32 - width));\n");
+ out("tmp = tmp ^ (0xffffffffu >> (32 - width));\n");
break;
case i_BFCLR:
- out("\ttmp = 0;\n");
+ out("tmp = 0;\n");
break;
case i_BFFFO:
- out("\t{ uae_u32 mask = 1 << (width - 1);\n");
- out("\twhile (mask) { if (tmp & mask) break; mask >>= 1; offset2++; }}\n");
- out("\tm68k_dreg(regs, (extra >> 12) & 7) = offset2;\n");
+ out("{ uae_u32 mask = 1 << (width - 1);\n");
+ out("while (mask) { if (tmp & mask) break; mask >>= 1; offset2++; }}\n");
+ out("m68k_dreg(regs, (extra >> 12) & 7) = offset2;\n");
break;
case i_BFSET:
- out("\ttmp = 0xffffffffu >> (32 - width);\n");
+ out("tmp = 0xffffffffu >> (32 - width);\n");
break;
case i_BFINS:
- out("\ttmp = m68k_dreg(regs, (extra >> 12) & 7);\n");
- out("\ttmp = tmp & (0xffffffffu >> (32 - width));\n");
- out("\tSET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);\n");
- out("\tSET_ZFLG (tmp == 0);\n");
+ out("tmp = m68k_dreg(regs, (extra >> 12) & 7);\n");
+ out("tmp = tmp & (0xffffffffu >> (32 - width));\n");
+ out("SET_NFLG (tmp & (1 << (width - 1)) ? 1 : 0);\n");
+ out("SET_ZFLG (tmp == 0);\n");
break;
default:
break;
|| curi->mnemo == i_BFSET
|| curi->mnemo == i_BFINS) {
if (curi->dmode == Dreg) {
- out("\ttmp = bdata[0] | (tmp << (32 - width));\n");
- out("\tm68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));\n");
+ out("tmp = bdata[0] | (tmp << (32 - width));\n");
+ out("m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));\n");
} else {
- out("\t%s(dsta, bdata, tmp, offset, width);\n", putb);
+ out("%s(dsta, bdata, tmp, offset, width);\n", putb);
}
}
}
break;
case i_PACK:
if (curi->smode == Dreg) {
- out("\tuae_u16 val = m68k_dreg(regs, srcreg) + %s;\n", gen_nextiword (0));
- out("\tm68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & 0xffffff00) | ((val >> 4) & 0xf0) | (val & 0xf);\n");
+ out("uae_u16 val = m68k_dreg(regs, srcreg) + %s;\n", gen_nextiword (0));
+ out("m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & 0xffffff00) | ((val >> 4) & 0xf0) | (val & 0xf);\n");
} else {
- out("\tuae_u16 val;\n");
+ out("uae_u16 val;\n");
addmmufixup("srcreg", curi->size, curi->smode);
- out("\tm68k_areg(regs, srcreg) -= 2;\n");
- out("\tval = (uae_u16)(%s(m68k_areg(regs, srcreg)));\n", srcw);
- out("\tval += %s;\n", gen_nextiword(0));
+ out("m68k_areg(regs, srcreg) -= 2;\n");
+ out("val = (uae_u16)(%s(m68k_areg(regs, srcreg)));\n", srcw);
+ out("val += %s;\n", gen_nextiword(0));
addmmufixup("dstreg", curi->size, curi->dmode);
- out("\tm68k_areg(regs, dstreg) -= areg_byteinc[dstreg];\n");
+ out("m68k_areg(regs, dstreg) -= areg_byteinc[dstreg];\n");
gen_set_fault_pc (false, false);
- out("\t%s(m68k_areg(regs, dstreg),((val >> 4) & 0xf0) | (val & 0xf));\n", dstb);
+ out("%s(m68k_areg(regs, dstreg),((val >> 4) & 0xf0) | (val & 0xf));\n", dstb);
}
break;
case i_UNPK:
if (curi->smode == Dreg) {
- out("\tuae_u16 val = m68k_dreg(regs, srcreg);\n");
- out("\tval = ((val << 4) & 0xf00) | (val & 0xf);\n");
- out("\tval += %s;\n", gen_nextiword(0));
- out("\tm68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & 0xffff0000) | (val & 0xffff);\n");
+ out("uae_u16 val = m68k_dreg(regs, srcreg);\n");
+ out("val = ((val << 4) & 0xf00) | (val & 0xf);\n");
+ out("val += %s;\n", gen_nextiword(0));
+ out("m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & 0xffff0000) | (val & 0xffff);\n");
} else {
- out("\tuae_u16 val;\n");
+ out("uae_u16 val;\n");
addmmufixup ("srcreg", curi->size, curi->smode);
- out("\tm68k_areg(regs, srcreg) -= areg_byteinc[srcreg];\n");
- out("\tval = (uae_u16)(%s(m68k_areg(regs, srcreg)) & 0xff);\n", srcb);
- out("\tval = (((val << 4) & 0xf00) | (val & 0xf)) + %s;\n", gen_nextiword (0));
+ out("m68k_areg(regs, srcreg) -= areg_byteinc[srcreg];\n");
+ out("val = (uae_u16)(%s(m68k_areg(regs, srcreg)) & 0xff);\n", srcb);
+ out("val = (((val << 4) & 0xf00) | (val & 0xf)) + %s;\n", gen_nextiword (0));
addmmufixup ("dstreg", curi->size, curi->dmode);
- out("\tm68k_areg(regs, dstreg) -= 2;\n");
+ out("m68k_areg(regs, dstreg) -= 2;\n");
gen_set_fault_pc(false, false);
- out("\t%s(m68k_areg(regs, dstreg), val);\n", dstw);
+ out("%s(m68k_areg(regs, dstreg), val);\n", dstw);
}
break;
case i_TAS:
if (!isreg(curi->smode)) {
addcycles000(2);
}
- out("\tsrc |= 0x80;\n");
+ out("src |= 0x80;\n");
if (isreg(curi->smode) || !using_ce) {
genastore_tas("src", curi->smode, "srcreg", curi->size, "src");
} else {
- out("\tif (!is_cycle_ce()) {\n");
+ out("if (!is_cycle_ce()) {\n");
genastore("src", curi->smode, "srcreg", curi->size, "src");
- out("\t} else {\n");
- out("\t\t%s(4);\n", do_cycles);
- addcycles000_nonce("\t\t", 4);
- out("\t}\n");
+ out("} else {\n");
+ out("%s(4);\n", do_cycles);
+ addcycles000_nonce("", 4);
+ out("}\n");
}
fill_prefetch_next();
} else if (cpu_level == 1) {
genamode(curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_LRMW);
} else {
genamode(curi, curi->smode, "srcreg", curi->size, "src", 2, 0, GF_LRMW | GF_NOFETCH);
- out("\tuae_u8 src = %s(srca);\n", srcb);
+ out("uae_u8 src = %s(srca);\n", srcb);
}
genflags(flag_logical, curi->size, "src", "", "");
if (!isreg(curi->smode)) {
addcycles000(2);
}
- out("\tsrc |= 0x80;\n");
+ out("src |= 0x80;\n");
if (isreg(curi->smode) || !using_ce) {
genastore_tas("src", curi->smode, "srcreg", curi->size, "src");
} else {
- out("\tif (!is_cycle_ce()) {\n");
+ out("if (!is_cycle_ce()) {\n");
genastore("src", curi->smode, "srcreg", curi->size, "src");
- out("\t} else {\n");
- out("\t\t%s(4);\n", do_cycles);
- addcycles000_nonce("\t\t", 4);
- out("\t}\n");
+ out("} else {\n");
+ out("%s(4);\n", do_cycles);
+ addcycles000_nonce("", 4);
+ out("}\n");
}
fill_prefetch_next();
} else {
genamode(curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_LRMW);
genflags(flag_logical, curi->size, "src", "", "");
- out("\tsrc |= 0x80;\n");
+ out("src |= 0x80;\n");
if (next_cpu_level < 2)
next_cpu_level = 2 - 1;
genastore_tas("src", curi->smode, "srcreg", curi->size, "src");
fpulimit();
genamode (curi, curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
sync_m68k_pc ();
- out("\tfpuop_arithmetic(opcode, extra);\n");
+ out("fpuop_arithmetic(opcode, extra);\n");
if (using_prefetch || using_prefetch_020) {
- out("\tif (regs.fp_exception) {\n");
- write_return_cycles("\t\t", 0);
- out("\t}\n");
+ out("if (regs.fp_exception) {\n");
+ write_return_cycles("", 0);
+ out("}\n");
}
break;
case i_FDBcc:
fpulimit();
genamode (curi, curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
sync_m68k_pc ();
- out("\tfpuop_dbcc (opcode, extra);\n");
+ out("fpuop_dbcc (opcode, extra);\n");
if (using_prefetch || using_prefetch_020) {
- out("\tif (regs.fp_exception) {\n");
- write_return_cycles("\t\t", 0);
- out("\t}\n");
- out("\tif (regs.fp_branch) {\n");
- out("\t\tregs.fp_branch = false;\n");
- out("\t\tfill_prefetch();\n");
- write_return_cycles("\t\t", 0);
- out("\t}\n");
+ out("if (regs.fp_exception) {\n");
+ write_return_cycles("", 0);
+ out("}\n");
+ out("if (regs.fp_branch) {\n");
+ out("regs.fp_branch = false;\n");
+ out("fill_prefetch();\n");
+ write_return_cycles("", 0);
+ out("}\n");
} else {
- out("\tif (regs.fp_branch) {\n");
- out("\t\tregs.fp_branch = false;\n");
- out("\t\tif(regs.t0) check_t0_trace();\n");
- out("\t}\n");
+ out("if (regs.fp_branch) {\n");
+ out("regs.fp_branch = false;\n");
+ out("if(regs.t0) check_t0_trace();\n");
+ out("}\n");
}
break;
case i_FScc:
fpulimit();
genamode (curi, curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
sync_m68k_pc ();
- out("\tfpuop_scc (opcode, extra);\n");
+ out("fpuop_scc (opcode, extra);\n");
if (using_prefetch || using_prefetch_020) {
- out("\tif (regs.fp_exception) {\n");
- write_return_cycles("\t\t", 0);
- out("\t}\n");
+ out("if (regs.fp_exception) {\n");
+ write_return_cycles("", 0);
+ out("}\n");
}
break;
case i_FTRAPcc:
fpulimit();
- out("\tuaecptr oldpc = %s;\n", getpc);
- out("\tuae_u16 extra = %s;\n", gen_nextiword (0));
+ out("uaecptr oldpc = %s;\n", getpc);
+ out("uae_u16 extra = %s;\n", gen_nextiword (0));
if (curi->smode != am_unknown && curi->smode != am_illg)
genamode (curi, curi->smode, "srcreg", curi->size, "dummy", 1, 0, 0);
sync_m68k_pc ();
- out("\tfpuop_trapcc (opcode, oldpc, extra);\n");
+ out("fpuop_trapcc (opcode, oldpc, extra);\n");
if (using_prefetch || using_prefetch_020) {
- out("\tif (regs.fp_exception) {\n");
- write_return_cycles("\t\t", 0);
- out("\t}\n");
+ out("if (regs.fp_exception) {\n");
+ write_return_cycles("", 0);
+ out("}\n");
}
break;
case i_FBcc:
fpulimit();
sync_m68k_pc ();
start_brace ();
- out("\tuaecptr pc = %s;\n", getpc);
+ out("uaecptr pc = %s;\n", getpc);
genamode (curi, curi->dmode, "srcreg", curi->size, "extra", 1, 0, 0);
sync_m68k_pc ();
- out("\tfpuop_bcc (opcode, pc,extra);\n");
+ out("fpuop_bcc (opcode, pc,extra);\n");
if (using_prefetch || using_prefetch_020) {
- out("\tif (regs.fp_exception) {\n");
- write_return_cycles("\t\t", 0);
- out("\t}\n");
- out("\tif (regs.fp_branch) {\n");
- out("\t\tregs.fp_branch = false;\n");
- out("\t\tfill_prefetch();\n");
- write_return_cycles("\t\t", 0);
- out("\t}\n");
+ out("if (regs.fp_exception) {\n");
+ write_return_cycles("", 0);
+ out("}\n");
+ out("if (regs.fp_branch) {\n");
+ out("regs.fp_branch = false;\n");
+ out("fill_prefetch();\n");
+ write_return_cycles("", 0);
+ out("}\n");
} else {
- out("\tif (regs.fp_branch) {\n");
- out("\t\tregs.fp_branch = false;\n");
- out("\t\tif(regs.t0) check_t0_trace();\n");
- out("\t}\n");
+ out("if (regs.fp_branch) {\n");
+ out("regs.fp_branch = false;\n");
+ out("if(regs.t0) check_t0_trace();\n");
+ out("}\n");
}
break;
case i_FSAVE:
fpulimit();
sync_m68k_pc ();
- out("\tfpuop_save (opcode);\n");
+ out("fpuop_save (opcode);\n");
if (using_prefetch || using_prefetch_020) {
- out("\tif (regs.fp_exception) {\n");
- write_return_cycles("\t\t", 0);
- out("\t}\n");
+ out("if (regs.fp_exception) {\n");
+ write_return_cycles("", 0);
+ out("}\n");
}
break;
case i_FRESTORE:
fpulimit();
sync_m68k_pc ();
- out("\tfpuop_restore (opcode);\n");
+ out("fpuop_restore (opcode);\n");
if (using_prefetch || using_prefetch_020) {
- out("\tif (regs.fp_exception) {\n");
- write_return_cycles("\t\t", 0);
- out("\t}\n");
+ out("if (regs.fp_exception) {\n");
+ write_return_cycles("", 0);
+ out("}\n");
}
break;
case i_CPUSHL:
case i_CPUSHP:
case i_CPUSHA:
- out("\tflush_cpu_caches_040(opcode);\n");
+ out("flush_cpu_caches_040(opcode);\n");
if (using_mmu)
- out("\tflush_mmu%s(m68k_areg(regs, opcode & 3), (opcode >> 6) & 3);\n", mmu_postfix);
- out("\tif (opcode & 0x80)\n");
- out("\t\tflush_icache((opcode >> 6) & 3);\n");
- out("\t\tcheck_t0_trace();\n");
+ out("flush_mmu%s(m68k_areg(regs, opcode & 3), (opcode >> 6) & 3);\n", mmu_postfix);
+ out("if (opcode & 0x80)\n");
+ out("flush_icache((opcode >> 6) & 3);\n");
+ out("check_t0_trace();\n");
break;
case i_MOVE16:
{
if ((opcode & 0xfff8) == 0xf620) {
/* MOVE16 (Ax)+,(Ay)+ */
- out("\tuaecptr mems = m68k_areg(regs, srcreg) & ~15, memd;\n");
- out("\tdstreg = (%s >> 12) & 7;\n", gen_nextiword (0));
- out("\tmemd = m68k_areg(regs, dstreg) & ~15;\n");
+ out("uaecptr mems = m68k_areg(regs, srcreg) & ~15, memd;\n");
+ out("dstreg = (%s >> 12) & 7;\n", gen_nextiword (0));
+ out("memd = m68k_areg(regs, dstreg) & ~15;\n");
if (using_mmu >= 68040) {
- out("\tuae_u32 v[4];\n");
- out("\tget_move16_mmu (mems, v);\n");
- out("\tput_move16_mmu (memd, v);\n");
+ out("uae_u32 v[4];\n");
+ out("get_move16_mmu (mems, v);\n");
+ out("put_move16_mmu (memd, v);\n");
} else {
- out("\tuae_u32 v[4];\n");
- out("\tv[0] = %s(mems);\n", srcl);
- out("\tv[1] = %s(mems + 4);\n", srcl);
- out("\tv[2] = %s(mems + 8);\n", srcl);
- out("\tv[3] = %s(mems + 12);\n", srcl);
- out("\t%s(memd , v[0]);\n", dstl);
- out("\t%s(memd + 4, v[1]);\n", dstl);
- out("\t%s(memd + 8, v[2]);\n", dstl);
- out("\t%s(memd + 12, v[3]);\n", dstl);
+ out("uae_u32 v[4];\n");
+ out("v[0] = %s(mems);\n", srcl);
+ out("v[1] = %s(mems + 4);\n", srcl);
+ out("v[2] = %s(mems + 8);\n", srcl);
+ out("v[3] = %s(mems + 12);\n", srcl);
+ out("%s(memd , v[0]);\n", dstl);
+ out("%s(memd + 4, v[1]);\n", dstl);
+ out("%s(memd + 8, v[2]);\n", dstl);
+ out("%s(memd + 12, v[3]);\n", dstl);
}
- out("\tif (srcreg != dstreg)\n");
- out("\t\tm68k_areg(regs, srcreg) += 16;\n");
- out("\tm68k_areg(regs, dstreg) += 16;\n");
+ out("if (srcreg != dstreg)\n");
+ out("m68k_areg(regs, srcreg) += 16;\n");
+ out("m68k_areg(regs, dstreg) += 16;\n");
} else {
/* Other variants */
genamode (curi, curi->smode, "srcreg", curi->size, "mems", 0, 2, 0);
genamode (curi, curi->dmode, "dstreg", curi->size, "memd", 0, 2, 0);
if (using_mmu == 68040) {
- out("\tget_move16_mmu (memsa, mmu040_move16);\n");
- out("\tput_move16_mmu (memda, mmu040_move16);\n");
+ out("get_move16_mmu (memsa, mmu040_move16);\n");
+ out("put_move16_mmu (memda, mmu040_move16);\n");
} else if (using_mmu == 68060) {
- out("\tuae_u32 v[4];\n");
- out("\tget_move16_mmu (memsa, v);\n");
- out("\tput_move16_mmu (memda, v);\n");
+ out("uae_u32 v[4];\n");
+ out("get_move16_mmu (memsa, v);\n");
+ out("put_move16_mmu (memda, v);\n");
} else {
- out("\tmemsa &= ~15;\n");
- out("\tmemda &= ~15;\n");
- out("\tuae_u32 v[4];\n");
- out("\tv[0] = %s(memsa);\n", srcl);
- out("\tv[1] = %s(memsa + 4);\n", srcl);
- out("\tv[2] = %s(memsa + 8);\n", srcl);
- out("\tv[3] = %s(memsa + 12);\n", srcl);
- out("\t%s(memda , v[0]);\n", dstl);
- out("\t%s(memda + 4, v[1]);\n", dstl);
- out("\t%s(memda + 8, v[2]);\n", dstl);
- out("\t%s(memda + 12, v[3]);\n", dstl);
+ out("memsa &= ~15;\n");
+ out("memda &= ~15;\n");
+ out("uae_u32 v[4];\n");
+ out("v[0] = %s(memsa);\n", srcl);
+ out("v[1] = %s(memsa + 4);\n", srcl);
+ out("v[2] = %s(memsa + 8);\n", srcl);
+ out("v[3] = %s(memsa + 12);\n", srcl);
+ out("%s(memda , v[0]);\n", dstl);
+ out("%s(memda + 4, v[1]);\n", dstl);
+ out("%s(memda + 8, v[2]);\n", dstl);
+ out("%s(memda + 12, v[3]);\n", dstl);
}
if ((opcode & 0xfff8) == 0xf600)
- out("\tm68k_areg(regs, srcreg) += 16;\n");
+ out("m68k_areg(regs, srcreg) += 16;\n");
else if ((opcode & 0xfff8) == 0xf608)
- out("\tm68k_areg(regs, dstreg) += 16;\n");
+ out("m68k_areg(regs, dstreg) += 16;\n");
}
}
break;
case i_PFLUSHAN:
case i_PFLUSHA:
sync_m68k_pc();
- out("\tmmu_op (opcode, 0);\n");
+ out("mmu_op (opcode, 0);\n");
trace_t0_68040_only();
break;
case i_PLPAR:
case i_PLPAW:
sync_m68k_pc();
- out("\tmmu_op (opcode, 0);\n");
+ out("mmu_op (opcode, 0);\n");
break;
case i_PTESTR:
case i_PTESTW:
sync_m68k_pc ();
- out("\tmmu_op (opcode, 0);\n");
+ out("mmu_op (opcode, 0);\n");
trace_t0_68040_only();
break;
case i_MMUOP030:
- out("\tuaecptr pc = %s;\n", getpc);
- out("\tuae_u16 extra = %s(2);\n", prefetch_word);
+ out("uaecptr pc = %s;\n", getpc);
+ out("uae_u16 extra = %s(2);\n", prefetch_word);
m68k_pc_offset += 2;
sync_m68k_pc();
if (curi->smode == Areg || curi->smode == Dreg)
- out("\tuae_u16 extraa = 0;\n");
+ out("uae_u16 extraa = 0;\n");
else
genamode(curi, curi->smode, "srcreg", curi->size, "extra", 0, 0, 0);
sync_m68k_pc();
if (using_ce020 || using_prefetch_020) {
- out("\tif (mmu_op30 (pc, opcode, extra, extraa)) {\n");
- write_return_cycles("\t\t", 0);
- out("\t}\n");
+ out("if (mmu_op30 (pc, opcode, extra, extraa)) {\n");
+ write_return_cycles("", 0);
+ out("}\n");
} else {
- out("\tmmu_op30 (pc, opcode, extra, extraa);\n");
+ out("mmu_op30 (pc, opcode, extra, extraa);\n");
}
break;
default:
}
end:
if (loopmode && loopmodeextra) {
- out("\tif (loop_mode) {\n");
+ out("if (loop_mode) {\n");
addcycles000_onlyce(loopmodeextra);
- addcycles000_nonce("\t\t", loopmodeextra);
- out("\t}\n");
+ addcycles000_nonce("", loopmodeextra);
+ out("}\n");
}
loopmode_stop();
if (!genastore_done)
out("#ifndef CPUEMU_68000_ONLY\n");
out("%s REGPARAM2 CPUFUNC(op_%04x_%d%s)(uae_u32 opcode)\n{\n", (using_ce || using_ce020) ? "void" : "uae_u32", opcode, postfix, extra);
if (using_simple_cycles)
- out("\tint count_cycles = 0;\n");
+ out("int count_cycles = 0;\n");
switch (table68k[opcode].stype) {
case 0: smsk = 7; break;
{
if (table68k[opcode].spos == -1) {
if (((int) table68k[opcode].sreg) >= 128)
- out("\tuae_u32 srcreg = (uae_s32)(uae_s8)%d;\n", (int) table68k[opcode].sreg);
+ out("uae_u32 srcreg = (uae_s32)(uae_s8)%d;\n", (int) table68k[opcode].sreg);
else
- out("\tuae_u32 srcreg = %d;\n", (int) table68k[opcode].sreg);
+ out("uae_u32 srcreg = %d;\n", (int) table68k[opcode].sreg);
} else {
char source[100];
int pos = table68k[opcode].spos;
sprintf(source, "(opcode & %d)", smsk);
if (table68k[opcode].stype == 3)
- out("\tuae_u32 srcreg = imm8_table[%s];\n", source);
+ out("uae_u32 srcreg = imm8_table[%s];\n", source);
else if (table68k[opcode].stype == 1)
- out("\tuae_u32 srcreg = (uae_s32)(uae_s8)%s;\n", source);
+ out("uae_u32 srcreg = (uae_s32)(uae_s8)%s;\n", source);
else
- out("\tuae_u32 srcreg = %s;\n", source);
+ out("uae_u32 srcreg = %s;\n", source);
}
}
if (table68k[opcode].duse
{
if (table68k[opcode].dpos == -1) {
if (((int) table68k[opcode].dreg) >= 128)
- out("\tuae_u32 dstreg = (uae_s32)(uae_s8)%d;\n", (int) table68k[opcode].dreg);
+ out("uae_u32 dstreg = (uae_s32)(uae_s8)%d;\n", (int) table68k[opcode].dreg);
else
- out("\tuae_u32 dstreg = %d;\n", (int) table68k[opcode].dreg);
+ out("uae_u32 dstreg = %d;\n", (int) table68k[opcode].dreg);
} else {
int pos = table68k[opcode].dpos;
if (pos)
- out("\tuae_u32 dstreg = (opcode >> %d) & %d;\n",
+ out("uae_u32 dstreg = (opcode >> %d) & %d;\n",
pos, dmsk);
else
- out("\tuae_u32 dstreg = opcode & %d;\n", dmsk);
+ out("uae_u32 dstreg = opcode & %d;\n", dmsk);
}
}
count_read = count_write = count_ncycles = count_cycles = 0;
gen_opcode (opcode);
clearmmufixup(0, 0);
clearmmufixup(1, 0);
- write_return_cycles("\t", 1);
+ write_return_cycles("", 1);
if ((opcode & 0xf000) == 0xf000)
m68k_pc_total = -1;
projects / francis / winuae.git / commitdiff