#include "autoconf.h"
#include "rommgr.h"
#include "debug.h"
+#include "devices.h"
#define DUMPPACKET 0
csr[0] |= CSR0_MISS;
}
pword (p + 2, rmd1);
- rethink_a2065 ();
+ devices_rethink_all(rethink_a2065);
return;
}
}
csr[0] |= CSR0_RINT;
- rethink_a2065 ();
+ devices_rethink_all(rethink_a2065);
}
static int getfunc (void *devv, uae_u8 *d, int *len)
ethernet_trigger (td, sysdata);
}
csr[0] |= CSR0_TINT;
- rethink_a2065 ();
+ devices_rethink_all(rethink_a2065);
}
static void check_transmit(bool tdmd)
void rethink_a2065 (void)
{
- bool was = (uae_int_requested & 4) != 0;
- atomic_and(&uae_int_requested, ~4);
if (!configured)
return;
csr[0] &= ~CSR0_INTR;
if (mask & (CSR0_BABL | CSR0_MISS | CSR0_MERR | CSR0_RINT | CSR0_TINT | CSR0_IDON))
csr[0] |= CSR0_INTR;
if ((csr[0] & (CSR0_INTR | CSR0_INEA)) == (CSR0_INTR | CSR0_INEA)) {
- set_special_exter(SPCFLAG_UAEINT);
- atomic_or(&uae_int_requested, 4);
- if (!was && log_a2065 > 2)
+ safe_interrupt_set(0x0008);
+ if (log_a2065 > 2)
write_log(_T("7990 +IRQ\n"));
}
- if (log_a2065 && was && !(uae_int_requested & 4)) {
+ if (log_a2065) {
write_log(_T("7990 -IRQ\n"));
}
}
}
csr[0] &= ~CSR0_TDMD;
- rethink_a2065 ();
+ devices_rethink_all(rethink_a2065);
break;
case 1:
if (csr[0] & 4) {
#include "savestate.h"
#include "cpuboard.h"
#include "rtc.h"
+#include "devices.h"
#define DMAC_8727_ROM_VECTOR 0x8000
#define CDMAC_ROM_VECTOR 0x2000
static struct wd_state *wd_gvps2accel;
static struct wd_state *wd_comspec[MAX_DUPLICATE_EXPANSION_BOARDS];
struct wd_state *wd_cdtv;
+static bool configured;
static struct wd_state *scsi_units[MAX_SCSI_UNITS + 1];
}
}
}
+ configured = true;
return *wd;
}
case COMMODORE_8727:
return wds->cdmac.dmac_dma > 0;
}
- return false;
+ return false;
}
void rethink_a2091 (void)
{
+ if (!configured)
+ return;
for (int i = 0; i < MAX_SCSI_UNITS; i++) {
if (scsi_units[i]) {
int irq = isirq(scsi_units[i]);
if (irq & 1)
- INTREQ_0(0x8000 | 0x0008);
+ safe_interrupt_set(0x0008);
if (irq & 2)
- INTREQ_0(0x8000 | 0x2000);
-#if A2091_DEBUG > 2 || A3000_DEBUG > 2
+ safe_interrupt_set(0x2000);
+#if DEBUG > 2 || A3000_DEBUG > 2
write_log (_T("Interrupt_RETHINK:%d\n"), irq);
#endif
}
return;
if (!(wd->wc.auxstatus & ASR_INT))
return;
- rethink_a2091();
+ devices_rethink_all(rethink_a2091);
}
static void dmac_a2091_xt_int(struct wd_state *wd)
if (!wd->enabled)
return;
wd->cdmac.xt_irq = true;
- rethink_a2091();
+ devices_rethink_all(rethink_a2091);
}
void scsi_dmac_a2091_start_dma (struct wd_state *wd)
static void dmac_a2091_cint (struct wd_state *wd)
{
wd->cdmac.dmac_istr = 0;
- rethink_a2091 ();
+ devices_rethink_all(rethink_a2091);
}
static void doscsistatus(struct wd_state *wd, uae_u8 status)
{
struct wd_chip_state *wd = &wds->wc;
if (wd->intmask) {
- INTREQ_0(0x8000 | wd->intmask);
+ safe_interrupt_set(wd->intmask);
wd->intmask = 0;
}
if (wd->auxstatus & ASR_INT)
static void irq (void)
{
if (!(intreq & 8)) {
- INTREQ_0 (0x8000 | 0x0008);
+ safe_interrupt_set(0x0008);
}
}
static void do_irq(void)
{
if (!(intreq & 8)) {
- INTREQ_0(0x8000 | 0x0008);
+ safe_interrupt_set(0x0008);
}
}
static void INT2 (void)
{
if (!(intreq & 8)) {
- INTREQ_0 (0x8000 | 0x0008);
+ safe_interrupt_set(0x0008);
}
cd_led ^= LED_CD_ACTIVE2;
}
void rethink_cdtvcr(void)
{
if ((cdtvcr_4510_ram[CDTVCR_INTREQ] & cdtvcr_4510_ram[CDTVCR_INTENA]) && !cdtvcr_4510_ram[CDTVCR_INTDISABLE]) {
- INTREQ_0 (0x8000 | 0x0008);
+ safe_interrupt_set(0x0008);
cd_led ^= LED_CD_ACTIVE2;
}
}
static void ICR (uae_u32 data)
{
- INTREQ_0 (0x8000 | data);
+ safe_interrupt_set(data);
}
static void ICRA (uae_u32 data)
#include "idecontrollers.h"
#include "scsi.h"
#include "cpummu030.h"
+#include "devices.h"
// ROM expansion board diagrom call
// 00F83B7C 3.1 A4000
{
if (is_csmk3(&currprefs) || is_blizzardppc(&currprefs)) {
if (!(io_reg[CSIII_REG_IRQ] & (P5_IRQ_SCSI_EN | P5_IRQ_SCSI))) {
- INTREQ_0(0x8000 | 0x0008);
+ safe_interrupt_set(0x0008);
if (currprefs.cachesize)
atomic_or(&uae_int_requested, 0x010000);
uae_ppc_wakeup_main();
} else if (!(io_reg[CSIII_REG_IRQ] & (P5_IRQ_PPC_1 | P5_IRQ_PPC_2))) {
- INTREQ_0(0x8000 | 0x0008);
+ safe_interrupt_set(0x0008);
if (currprefs.cachesize)
atomic_or(&uae_int_requested, 0x010000);
uae_ppc_wakeup_main();
map_banks_nojitdirect(&blizzardmaprom_bank, blizzardmaprom_bank.start >> 16, 524288 >> 16, 0);
}
-void cyberstorm_mk3_ppc_irq(int level)
+void cyberstorm_mk3_ppc_irq_setonly(int level)
{
if (level)
io_reg[CSIII_REG_IRQ] &= ~P5_IRQ_SCSI;
else
io_reg[CSIII_REG_IRQ] |= P5_IRQ_SCSI;
- cpuboard_rethink();
+}
+void cyberstorm_mk3_ppc_irq(int level)
+{
+ cyberstorm_mk3_ppc_irq_setonly(level);
+ devices_rethink_all(cpuboard_rethink);
}
-void blizzardppc_irq(int level)
+void blizzardppc_irq_setonly(int level)
{
if (level)
io_reg[CSIII_REG_IRQ] &= ~P5_IRQ_SCSI;
else
io_reg[CSIII_REG_IRQ] |= P5_IRQ_SCSI;
- cpuboard_rethink();
+}
+void blizzardppc_irq(int level)
+{
+ blizzardppc_irq_setonly(level);
+ devices_rethink_all(cpuboard_rethink);
}
static uae_u32 REGPARAM2 blizzardio_bget(uaecptr addr)
#include "videograb.h"
#include "arcadia.h"
#include "rommgr.h"
+#include "newcpu.h"
#ifdef RETROPLATFORM
#include "rp.h"
#endif
#endif
}
+void devices_rethink_all(void func(void))
+{
+ if (ppc_state || 0) {
+ devices_rethink();
+ } else {
+ func();
+ }
+}
+
// these really should be dynamically allocated..
void devices_rethink(void)
{
+ safe_interrupt_clear_all();
rethink_cias ();
#ifdef A2065
rethink_a2065 ();
#include "debug.h"
#include "autoconf.h"
#include "rommgr.h"
+#include "devices.h"
#define PCMCIA_SRAM 1
#define PCMCIA_IDE 2
if (currprefs.cs_ide == IDE_A4000) {
gayle_irq |= checkgayleideirq ();
if ((gayle_irq & GAYLE_IRQ_IDE) && !(intreq & 0x0008))
- INTREQ_0 (0x8000 | 0x0008);
+ safe_interrupt_set(0x0008);
return;
}
lev2 = 1;
}
if (lev2 && !(intreq & 0x0008))
- INTREQ_0 (0x8000 | 0x0008);
+ safe_interrupt_set(0x0008);
if (lev6 && !(intreq & 0x2000))
- INTREQ_0 (0x8000 | 0x2000);
+ safe_interrupt_set(0x2000);
}
static void gayle_cs_change (uae_u8 mask, int onoff)
}
if (changed) {
gayle_irq |= mask;
- rethink_gayle ();
+ devices_rethink_all(rethink_gayle);
if ((mask & GAYLE_CS_CCDET) && (gayle_irq & (GAYLE_IRQ_RESET | GAYLE_IRQ_BERR)) != (GAYLE_IRQ_RESET | GAYLE_IRQ_BERR)) {
if (gayle_irq & GAYLE_IRQ_RESET)
uae_reset (0, 0);
gayle_cs_change (GAYLE_CS_WR, 0);
gayle_cs_change (GAYLE_CS_BSY, 0);
}
- rethink_gayle ();
+ devices_rethink_all(rethink_gayle);
}
static void write_gayle_cfg (uae_u8 val)
if (ne2000)
ne2000->hsync(ne2000_board_state);
if (ide_interrupt_hsync(idedrive[0]) || ide_interrupt_hsync(idedrive[2]) || ide_interrupt_hsync(idedrive[4]) || checkpcmciane2000irq())
- rethink_gayle();
+ devices_rethink_all(rethink_gayle);
}
static uaecptr from_gayle_pcmcmia(uaecptr addr)
irq |= ide_rethink(ide_boards[i], false);
}
}
- if (irq && !(intreq & 0x0008)) {
- INTREQ_0(0x8000 | 0x0008);
+ if (irq) {
+ safe_interrupt_set(0x0008);
}
}
extern int REGPARAM3 cyberstorm_scsi_ram_check(uaecptr addr, uae_u32 size) REGPARAM;
extern uae_u8 *REGPARAM3 cyberstorm_scsi_ram_xlate(uaecptr addr) REGPARAM;
-void cyberstorm_irq(int level);
void cyberstorm_mk3_ppc_irq(int level);
void blizzardppc_irq(int level);
+void cyberstorm_mk3_ppc_irq_setonly(int level);
+void blizzardppc_irq_setonly(int level);
#define BOARD_MEMORY_Z2 1
#define BOARD_MEMORY_Z3 2
void devices_vsync_post(void);
void devices_hsync(void);
void devices_rethink(void);
+void devices_rethink_all(void func(void));
void devices_syncchange(void);
void devices_update_sound(double clk, double syncadjust);
void devices_update_sync(double svpos, double syncadjust);
extern int cpucycleunit;
extern int m68k_pc_indirect;
+extern void safe_interrupt_set(uae_u32 v);
+extern void safe_interrupt_clear_all(void);
+
STATIC_INLINE void set_special_exter(uae_u32 x)
{
atomic_or(®s.spcflags, x);
#include "qemuvga/scsi/scsi.h"
#include "qemuvga/scsi/esp.h"
#include "gui.h"
+#include "devices.h"
#define FASTLANE_BOARD_SIZE (2 * 16777216)
#define FASTLANE_ROM_SIZE 32768
for (int i = 0; ncr_units[i]; i++) {
if (ncr_units[i]->boardirq) {
if (ncr_units[i]->irq6)
- INTREQ_0(0x8000 | 0x2000);
+ safe_interrupt_set(0x2000);
else
- INTREQ_0(0x8000 | 0x0008);
+ safe_interrupt_set(0x0008);
return;
}
}
{
if (ncr->chipirq && !ncr->boardirq) {
ncr->boardirq = true;
- ncr9x_rethink();
+ devices_rethink_all(ncr9x_rethink);
}
if (!ncr->chipirq && ncr->boardirq) {
ncr->boardirq = false;
ncr->boardirq = false;
if (ncr->chipirq && !ncr->boardirq && (ncr->states[0] & 0x40)) {
ncr->boardirq = true;
- ncr9x_rethink();
+ devices_rethink_all(ncr9x_rethink);
}
}
ncr->boardirq = false;
if (ncr->chipirq && !ncr->boardirq && (ncr->states[0] & 0x80)) {
ncr->boardirq = true;
- ncr9x_rethink();
+ devices_rethink_all(ncr9x_rethink);
+ }
+}
+
static void set_irq2_alf3(struct ncr9x_state *ncr)
{
if (!(ncr->states[0] & 0x01))
if (ncr->states[0] & FLSC_PB_ESI) {
if (!ncr->boardirq) {
ncr->boardirq = true;
- ncr9x_rethink();
+ devices_rethink_all(ncr9x_rethink);
}
}
}
ncr->boardirqlatch = true;
if (1 || ncr->intena) {
ncr->boardirq = true;
- ncr9x_rethink();
+ devices_rethink_all(ncr9x_rethink);
#if NCR_DEBUG > 1
write_log(_T("MASOBOSHI IRQ\n"));
#endif
}
void scsiesp_req_cancel(SCSIRequest *req)
{
- write_log(_T("scsi_req_cancel\n"));
+ write_log(_T("scsi_req_cancel!?\n"));
+ esp_request_cancelled(req);
}
#define IO_MASK 0x3f
static void set_irq2(int level)
{
if (level)
- INTREQ(0x8000 | 0x0008);
+ safe_interrupt_set(0x0008);
}
void ncr_rethink(void)
{
for (int i = 0; ncr_units[i]; i++) {
if (ncr_units[i] != ncr_cs && ncr_units[i]->irq)
- INTREQ_0(0x8000 | 0x0008);
+ safe_interrupt_set(0x0008);
}
if (ncr_cs && ncr_cs->irq)
- cyberstorm_mk3_ppc_irq(1);
+ cyberstorm_mk3_ppc_irq_setonly(1);
}
/* 720+ */
irq = true;
}
if (uae_int_requested & 0xff0000) {
- if (!cpuboard_is_ppcboard_irq())
+ if (!cpuboard_is_ppcboard_irq()) {
atomic_and(&uae_int_requested, ~0x010000);
+ }
}
- if (irq)
+ if (irq) {
doint();
+ }
+ }
+}
+
+/* 0x0010 = generic expansion level 2
+ * 0x1000 = generic expansion level 6
+ */
+void safe_interrupt_clear_all(void)
+{
+ atomic_and(&uae_int_requested, ~(0x0010 | 0x1000));
+}
+
+void safe_interrupt_set(uae_u32 v)
+{
+ if (ppc_state || 0) {
+ set_special_exter(SPCFLAG_UAEINT);
+ if (v & 0x0008)
+ atomic_or(&uae_int_requested, 0x0010);
+ if (v & 0x2000)
+ atomic_or(&uae_int_requested, 0x1000);
+ } else {
+ if (currprefs.cpu_cycle_exact || (!(intreq & v) && !currprefs.cpu_cycle_exact)) {
+ INTREQ_0(0x8000 | v);
+ }
}
}
#include "rommgr.h"
#include "cpuboard.h"
#include "autoconf.h"
+#include "devices.h"
#include "qemuvga/qemuuaeglue.h"
#include "qemuvga/queue.h"
void pci_rethink(void)
{
- atomic_and(&uae_int_requested, ~(0x10 | 0x100));
for (int i = 0; i < PCI_BRIDGE_MAX; i++) {
struct pci_bridge *pcib = bridges[i];
if (!pcib)
}
}
if (pcib->irq & pcib->intena) {
- atomic_or(&uae_int_requested, pcib->intreq_mask);
+ safe_interrupt_set(pcib->intreq_mask);
}
}
}
pcibs->config_data[5] &= ~(1 << 3);
if (active)
pcibs->config_data[5] |= (1 << 3);
- pci_rethink();
+ devices_rethink_all(pci_rethink);
}
static void create_config_data(struct pci_board_state *s)
pcib->endian_swap_io = 0;
pcib->endian_swap_memory = 0;
pcib->intena = 0xff; // controlled by bridge config bits, bit unknown.
- pcib->intreq_mask = 0x100;
+ pcib->intreq_mask = 0x2000;
pcib->get_index = dkb_wildfire_get_index;
pcib->baseaddress = 0x80000000;
pcib->baseaddress_end = 0xffffffff;
pcib->endian_swap_io = -1;
pcib->endian_swap_memory = -1;
pcib->intena = 0xff;
- pcib->intreq_mask = 0x10;
+ pcib->intreq_mask = 0x0008;
pcib->get_index = prometheus_get_index;
pcib->bank = &pci_bridge_bank;
pcib->bank_zorro = 3;
bridges[PCI_BRIDGE_GREX] = pcib;
pcib->label = _T("G-REX");
pcib->intena = 0;
- pcib->intreq_mask = 0x10;
+ pcib->intreq_mask = 0x0008;
pcib->get_index = grex_get_index;
pcib->baseaddress = 0x80000000;
pcib->baseaddress_end = 0xffffffff;
bridges[PCI_BRIDGE_XVISION] = pcib;
pcib->label = _T("CBVision");
pcib->intena = 0;
- pcib->intreq_mask = 0x10;
+ pcib->intreq_mask = 0x0008;
pcib->get_index = xvision_get_index;
pcib->baseaddress = 0xe0000000;
pcib->baseaddress_end = 0xffffffff;
pcib->endian_swap_io = -1;
pcib->endian_swap_memory = -1;
pcib->intena = 0;
- pcib->intreq_mask = 0x10;
+ pcib->intreq_mask = 0x0008;
pcib->get_index = mediator_get_index_1200;
pcib->bank = &pci_bridge_bank;
pcib->bank_2 = &pci_bridge_bank_2;
pcib->endian_swap_io = -1;
pcib->endian_swap_memory = -1;
pcib->intena = 0;
- pcib->intreq_mask = 0x10;
+ pcib->intreq_mask = 0x0008;
pcib->get_index = mediator_get_index_4000;
pcib->bank = &pci_bridge_bank;
pcib->bank_2 = &pci_bridge_bank_2;
#include "custom.h"
#include "debug.h"
#include "sana2.h"
+#include "devices.h"
#include "qemuuaeglue.h"
#include "queue.h"
return;
if (ne->ariadne2_irq) {
if (ne->level6)
- INTREQ_0(0x8000 | 0x2000);
+ safe_interrupt_set(0x2000);
else
- INTREQ_0(0x8000 | 0x0008);
+ safe_interrupt_set(0x0008);
}
}
write_log(_T("ariadne2_irq_callback %d\n"), irq);
#endif
ne->ariadne2_irq = irq;
- rethink_ne2000();
+ devices_rethink_all(rethink_ne2000);
}
static addrbank ariadne2_bank = {
#include "custom.h"
#include "gayle.h"
#include "cia.h"
+#include "devices.h"
#define SCSI_EMU_DEBUG 0
#define RAW_SCSI_DEBUG 0
scsi->regs[16 + 8] |= mask;
if ((scsi->regs[16 + 8] & scsi->regs[3]) & 0x1f) {
scsi->irq = true;
- ncr80_rethink();
+ devices_rethink_all(ncr80_rethink);
} else {
scsi->irq = false;
}
x86_doirq(5);
} else {
if (soft_scsi_devices[i]->level6)
- INTREQ_0(0x8000 | 0x2000);
+ safe_interrupt_set(0x2000);
else
- INTREQ_0(0x8000 | 0x0008);
+ safe_interrupt_set(0x0008);
return;
}
}
if (scsi->irq)
return;
scsi->irq = true;
- ncr80_rethink();
+ devices_rethink_all(ncr80_rethink);
if (scsi->delayed_irq)
x_do_cycles(2 * CYCLE_UNIT);
#if NCR5380_DEBUG_IRQ
#include "pci_hw.h"
#include "qemuvga/qemuaudio.h"
#include "rommgr.h"
+#include "devices.h"
static uae_u8 *sndboard_get_buffer(int *frames);
static void sndboard_release_buffer(uae_u8 *buffer, int frames);
s->intreqmask |= mask;
if ((s->intenamask & mask)) {
s->intreqmask |= 0x80;
- sndboard_rethink();
+ devices_rethink_all(sndboard_rethink);
}
}
data->toccata_irq |= STATUS_READ_RECORD_HALF;
}
if (old != data->toccata_irq) {
- sndboard_rethink();
+ devices_rethink_all(sndboard_rethink);
#if DEBUG_TOCCATA > 2
write_log(_T("TOCCATA IRQ\n"));
#endif
irq |= uaesnd_rethink();
}
if (irq) {
- atomic_or(&uae_int_requested, 0x200);
- set_special_exter(SPCFLAG_UAEINT);
+ safe_interrupt_set(0x2000);
+ //atomic_or(&uae_int_requested, 0x200);
+ //set_special_exter(SPCFLAG_UAEINT);
} else {
- atomic_and(&uae_int_requested, ~0x200);
+ //atomic_and(&uae_int_requested, ~0x200);
}
}
#include "idecontrollers.h"
#include "gfxboard.h"
#include "pci_hw.h"
+#include "devices.h"
#include "dosbox/dosbox.h"
#include "dosbox/mem.h"
write_log(_T("IO_AMIGA_INTERRUPT_STATUS set bit %d\n"), bit);
#endif
xb->amiga_io[IO_AMIGA_INTERRUPT_STATUS] |= 1 << bit;
- x86_bridge_rethink();
+ devices_rethink_all(x86_bridge_rethink);
}
/* 8237 and 8253 from fake86 with small modifications */
uae_u8 intena = xb->amiga_io[IO_INTERRUPT_MASK];
uae_u8 status = intreq & ~intena;
if (status)
- INTREQ_0(0x8000 | 0x0008);
+ safe_interrupt_set(0x0008);
}
}
return;
if (xb->delayed_interrupt) {
- x86_bridge_rethink();
+ devices_rethink_all(x86_bridge_rethink);
}
}