static const struct expansionboardsettings dataflyersplus_settings[] = {
{
_T("Configuration\0") _T("SCSI+IDE\0") _T("SCSI\0") _T("IDE\0"),
- _T("config\0") _T("scsiide") _T("scsi\0") _T("ide\0"),
+ _T("config\0") _T("scsiide\0") _T("scsi\0") _T("ide\0"),
true
},
{
NULL
}
};
+static const struct expansionboardsettings alf3_settings[] = {
+ {
+ _T("Parity (J6)"),
+ _T("j6"),
+ },
+ {
+ _T("LUN (J7)"),
+ _T("j7"),
+ },
+ {
+ _T("Disconnect/Reconnect (J8)"),
+ _T("j8"),
+ },
+ {
+ _T("Login screen (J9)"),
+ _T("j9"),
+ },
+ {
+ _T("Login screen (J10)"),
+ _T("j10"),
+ },
+ {
+ _T("Interrupt level (J11)\0") _T("6\0") _T("2\0"),
+ _T("j11\0") _T("6\0") _T("2\0"),
+ true
+ },
+ {
+ NULL
+ }
+};
+
+
const struct expansionromtype expansionroms[] = {
{
true, 2, fastata_settings,
{ 0x90, 0, 0x10, 0x00, 0x08, 0x9e, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00 },
},
+ {
+ _T("elsathd"), _T("Mega Ram HD"), _T("Elsat"),
+ NULL, elsathd_init, NULL, elsathd_add_ide_unit, ROMTYPE_ELSATHD, 0, 0, BOARD_AUTOCONFIG_Z2, true,
+ NULL, 0,
+ true, EXPANSIONTYPE_IDE,
+ 17740, 1, 0
+ },
{
_T("eveshamref"), _T("Reference 40/100"), _T("Evesham Micros"),
NULL, eveshamref_init, NULL, eveshamref_add_scsi_unit, ROMTYPE_EVESHAMREF, 0, 0, BOARD_AUTOCONFIG_Z2, false,
NULL, 0,
false, EXPANSIONTYPE_CUSTOM | EXPANSIONTYPE_SCSI
},
+ {
+ _T("alf3"), _T("A.L.F.3"), _T("Elaborate Bytes"),
+ NULL, ncr_alf3_autoconfig_init, NULL, alf3_add_scsi_unit, ROMTYPE_ALF3 | ROMTYPE_NONE, 0, 0, BOARD_AUTOCONFIG_Z2, false,
+ NULL, 0,
+ true, EXPANSIONTYPE_SCSI,
+ 0, 0, 0, false, NULL,
+ true, 0, alf3_settings
+ },
{
_T("promigos"), _T("Promigos"), _T("Flesch und Hörnemann"),
NULL, promigos_init, NULL, promigos_add_scsi_unit, ROMTYPE_PROMIGOS | ROMTYPE_NOT, 0, 0, BOARD_NONAUTOCONFIG_BEFORE, true,
#include "scsi.h"
#include "ncr9x_scsi.h"
#include "autoconf.h"
+#include "devices.h"
#define DEBUG_IDE 0
#define DEBUG_IDE_GVP 0
#define DATAFLYERPLUS_IDE (BUDDHA_IDE + 3 * MAX_DUPLICATE_EXPANSION_BOARDS)
#define ATEAM_IDE (DATAFLYERPLUS_IDE + MAX_DUPLICATE_EXPANSION_BOARDS)
#define FASTATA4K_IDE (ATEAM_IDE + MAX_DUPLICATE_EXPANSION_BOARDS)
-#define TOTAL_IDE (FASTATA4K_IDE + 2 * MAX_DUPLICATE_EXPANSION_BOARDS)
+#define ELSATHD_IDE (FASTATA4K_IDE + 2 * MAX_DUPLICATE_EXPANSION_BOARDS)
+#define TOTAL_IDE (ELSATHD_IDE + MAX_DUPLICATE_EXPANSION_BOARDS)
#define ALF_ROM_OFFSET 0x0100
#define GVP_IDE_ROM_OFFSET 0x8000
static struct ide_board *ateam_board[MAX_DUPLICATE_EXPANSION_BOARDS];
static struct ide_board *arriba_board[MAX_DUPLICATE_EXPANSION_BOARDS];
static struct ide_board *fastata4k_board[MAX_DUPLICATE_EXPANSION_BOARDS];
+static struct ide_board *elsathd_board[MAX_DUPLICATE_EXPANSION_BOARDS];
static struct ide_hdf *idecontroller_drive[TOTAL_IDE * 2];
static struct ide_thread_state idecontroller_its;
}
}
if (ide_interrupt_check(board, false)) {
- idecontroller_rethink();
+ devices_rethink_all(idecontroller_rethink);
}
}
}
return reg;
}
+static int get_elsathd_reg(uaecptr addr, struct ide_board *board)
+{
+ if (!(addr & 0x8000))
+ return -1;
+ if (!(addr & 1))
+ return -1;
+ int reg = ((addr & 0x0fff) >> 9) & 7;
+ return reg;
+}
+
static int get_fastata4k_reg(uaecptr addr, struct ide_board *board, int *portnum)
{
*portnum = 0;
addr &= board->mask;
#if DEBUG_IDE
- write_log(_T("IDE IO BYTE READ %08x %08x\n"), addr, M68K_GETPC);
+ if (0 || (addr & 0x8000))
+ write_log(_T("IDE IO BYTE READ %08x %08x\n"), addr, M68K_GETPC);
#endif
if (addr < 0x40 && (!board->configured || board->keepautoconfig))
v = board->rom[offset];
}
+ } else if (board->type == ELSATHD_IDE) {
+
+ int reg = get_elsathd_reg(addr, board);
+ if (reg >= 0) {
+ v = get_ide_reg(board, reg);
+ } else if (board->rom && !(addr & 0x8000)) {
+ int offset = addr & 0x7fff;
+ v = board->rom[offset];
+ }
+
} else if (board->type == FASTATA4K_IDE) {
int portnum;
v |= board->rom[(offset + 1) & board->rom_mask];
}
+ } else if (board->type == ELSATHD_IDE) {
+
+ int reg = get_elsathd_reg(addr | 1, board);
+ if (reg == 0) {
+ v = get_ide_reg_multi(board, IDE_DATA, 0, 1);
+ } else if (reg > 0) {
+ v = get_ide_reg(board, reg);
+ } else if (board->rom && !(addr & 0x8000)) {
+ int offset = addr & 0x7fff;
+ v = board->rom[(offset + 0) & board->rom_mask];
+ v <<= 8;
+ v |= board->rom[(offset + 1) & board->rom_mask];
+ }
+
} else if (board->type == FASTATA4K_IDE) {
int portnum;
}
#if DEBUG_IDE
- write_log(_T("IDE IO WORD READ %08x %04x %08x\n"), addr, v, M68K_GETPC);
+ if (0 || (addr & 0x8000))
+ write_log(_T("IDE IO WORD READ %08x %04x %08x\n"), addr, v, M68K_GETPC);
#endif
return v;
addr &= board->mask;
#if DEBUG_IDE
- write_log(_T("IDE IO BYTE WRITE %08x=%02x %08x\n"), addr, v, M68K_GETPC);
+ if (0 || (addr & 0x8000))
+ write_log(_T("IDE IO BYTE WRITE %08x=%02x %08x\n"), addr, v, M68K_GETPC);
#endif
if (!board->configured) {
put_ide_reg(board, reg, v);
}
+ } else if (board->type == ELSATHD_IDE) {
+
+ int reg = get_elsathd_reg(addr, board);
+ if (reg >= 0) {
+ put_ide_reg(board, reg, v);
+ }
+
} else if (board->type == FASTATA4K_IDE) {
int portnum;
addr &= board->mask;
#if DEBUG_IDE
- write_log(_T("IDE IO WORD WRITE %08x=%04x %08x\n"), addr, v, M68K_GETPC);
+ if (0 || (addr & 0x8000))
+ write_log(_T("IDE IO WORD WRITE %08x=%04x %08x\n"), addr, v, M68K_GETPC);
#endif
if (board->configured) {
put_ide_reg_multi(board, IDE_DATA, v, 0, 1);
}
+ } else if (board->type == ELSATHD_IDE) {
+
+ int reg = get_elsathd_reg(addr | 1, board);
+ if (!reg) {
+ put_ide_reg_multi(board, IDE_DATA, v, 0, 1);
+ } else if (reg > 0) {
+ put_ide_reg(board, reg, v & 0xff);
+ }
+
} else if (board->type == FASTATA4K_IDE) {
int portnum;
add_ide_standard_unit(ch, ci, rc, arriba_board, ARRIBA_IDE, false, false, 2);
}
+bool elsathd_init(struct autoconfig_info *aci)
+{
+ uae_u8 *rom;
+ int rom_size = 16384;
+
+ rom = xcalloc(uae_u8, rom_size);
+ memset(rom, 0xff, rom_size);
+ load_rom_rc(aci->rc, ELSATHD_IDE, 16384, 0, rom, 16384, LOADROM_FILL);
+ if (aci->rc->autoboot_disabled)
+ rom[0] &= ~0x10;
+
+ if (!aci->doinit) {
+ memcpy(aci->autoconfig_raw, rom, sizeof aci->autoconfig_raw);
+ xfree(rom);
+ return true;
+ }
+
+ struct ide_board *ide = getide(aci);
+
+ ide->configured = 0;
+ ide->keepautoconfig = false;
+ ide->bank = &ide_bank_generic;
+ ide->mask = 65536 - 1;
+
+ ide->rom = rom;
+ ide->rom_size = rom_size;
+ ide->rom_mask = rom_size - 1;
+ memcpy(ide->acmemory, ide->rom, sizeof ide->acmemory);
+
+ aci->addrbank = ide->bank;
+ return true;
+}
+
+void elsathd_add_ide_unit(int ch, struct uaedev_config_info *ci, struct romconfig *rc)
+{
+ add_ide_standard_unit(ch, ci, rc, elsathd_board, ELSATHD_IDE, true, false, 2);
+}
extern void x86_xt_ide_bios(struct zfile*, struct romconfig*);
static bool x86_at_hd_init(struct autoconfig_info *aci, int type)
bool arriba_init(struct autoconfig_info *aci);
void arriba_add_ide_unit(int ch, struct uaedev_config_info *ci, struct romconfig *rc);
+bool elsathd_init(struct autoconfig_info *aci);
+void elsathd_add_ide_unit(int ch, struct uaedev_config_info *ci, struct romconfig *rc);
+
uae_u32 REGPARAM3 apollo_ide_lget (uaecptr addr) REGPARAM;
uae_u32 REGPARAM3 apollo_ide_wget (uaecptr addr) REGPARAM;
uae_u32 REGPARAM3 apollo_ide_bget (uaecptr addr) REGPARAM;
extern void golemfast_add_scsi_unit(int ch, struct uaedev_config_info *ci, struct romconfig *rc);
extern void scram5394_add_scsi_unit(int ch, struct uaedev_config_info *ci, struct romconfig *rc);
extern void rapidfire_add_scsi_unit(int ch, struct uaedev_config_info *ci, struct romconfig *rc);
+extern void alf3_add_scsi_unit(int ch, struct uaedev_config_info *ci, struct romconfig *rc);
extern bool ncr_fastlane_autoconfig_init(struct autoconfig_info *aci);
extern bool ncr_oktagon_autoconfig_init(struct autoconfig_info *aci);
extern bool ncr_multievolution_init(struct autoconfig_info *aci);
extern bool ncr_scram5394_init(struct autoconfig_info *aci);
extern bool ncr_rapidfire_init(struct autoconfig_info *aci);
+extern bool ncr_alf3_autoconfig_init(struct autoconfig_info *aci);
extern void cpuboard_ncr9x_scsi_put(uaecptr, uae_u32);
extern uae_u32 cpuboard_ncr9x_scsi_get(uaecptr);
#define ROMTYPE_ARRIBA 0x0010006e
#define ROMTYPE_EVESHAMREF 0x0010006f
#define ROMTYPE_PROFEX 0x00100070
+#define ROMTYPE_ELSATHD 0x00100071
+#define ROMTYPE_ALF3 0x00100072
#define ROMTYPE_NOT 0x00800000
#define ROMTYPE_QUAD 0x01000000
static struct ncr9x_state *ncr_blizzard_scsi;
static struct ncr9x_state *ncr_fastlane_scsi[MAX_DUPLICATE_EXPANSION_BOARDS];
static struct ncr9x_state *ncr_oktagon2008_scsi[MAX_DUPLICATE_EXPANSION_BOARDS];
+static struct ncr9x_state *ncr_alf3_scsi[MAX_DUPLICATE_EXPANSION_BOARDS];
static struct ncr9x_state *ncr_masoboshi_scsi[MAX_DUPLICATE_EXPANSION_BOARDS];
static struct ncr9x_state *ncr_dkb1200_scsi;
static struct ncr9x_state *ncr_ematrix530_scsi;
if (ncr->chipirq && !ncr->boardirq && (ncr->states[0] & 0x80)) {
ncr->boardirq = true;
ncr9x_rethink();
+static void set_irq2_alf3(struct ncr9x_state *ncr)
+{
+ if (!(ncr->states[0] & 0x01))
+ ncr->boardirq = false;
+ if (ncr->chipirq && !ncr->boardirq && (ncr->states[0] & 0x01)) {
+ ncr->boardirq = true;
+ devices_rethink_all(ncr9x_rethink);
}
}
return false;
}
-static void ncr9x_io_bput(struct ncr9x_state *ncr, uaecptr addr, uae_u32 val)
+static void ncr9x_io_bput3(struct ncr9x_state *ncr, uaecptr addr, uae_u32 val, int *reg)
{
int reg_shift = 2;
uaecptr oldaddr = addr;
return;
}
reg_shift = 1;
+
+ } else if (isncr(ncr, ncr_alf3_scsi)) {
+
+ if (addr >= 0xd000 && addr < 0xe000) {
+ ncr->data = val;
+ ncr->data_valid_r = true;
+ esp_dma_enable(ncr->devobject.lsistate, 1);
+ return;
+ } else if (addr == 0xa001) {
+ ncr->states[0] = val;
+ set_irq2_alf3(ncr);
+ return;
+ }
+ if (addr < 0x8000 || addr >= 0x8000 + 0x100)
+ return;
+
+ reg_shift = 1;
+
} else if (isncr(ncr, ncr_fastlane_scsi)) {
+
if (addr >= FASTLANE_HARDBITS) {
if (addr == FASTLANE_HARDBITS) {
int oldstate = ncr->states[0];
return;
addr >>= reg_shift;
addr &= IO_MASK;
+ esp_reg_write(ncr->devobject.lsistate, (addr), val);
+ *reg = addr;
+}
+
+static void ncr9x_io_bput(struct ncr9x_state *ncr, uaecptr addr, uae_u32 val)
+{
+ int reg = -1;
+ ncr9x_io_bput3(ncr, addr, val, ®);
#if NCR_DEBUG > 1
- write_log(_T("ESP write %02X (%08X) %02X %08X\n"), addr, oldaddr, val & 0xff, M68K_GETPC);
+ if (ncr)
+ write_log(_T("ESP write %02X (%08X) %02X %08X\n"), reg & 0xff, addr, val & 0xff, M68K_GETPC);
#endif
- esp_reg_write(ncr->devobject.lsistate, (addr), val);
}
-static uae_u32 ncr9x_io_bget(struct ncr9x_state *ncr, uaecptr addr)
+
+static uae_u32 ncr9x_io_bget3(struct ncr9x_state *ncr, uaecptr addr, int *reg)
{
uae_u8 v = 0xff;
int reg_shift = 2;
if (addr < OKTAGON_ESP_ADDR || addr >= OKTAGON_ESP_ADDR + 0x100)
return 0xff;
reg_shift = 1;
+
+ } else if (isncr(ncr, ncr_alf3_scsi)) {
+
+ if (addr >= 0xd000 && addr < 0xe000) {
+ esp_dma_enable(ncr->devobject.lsistate, 1);
+ v = ncr->data;
+ ncr->data_valid_w = false;
+ return v;
+ } else if (addr == 0xa000) {
+ v = 0;
+ if (ncr->rc->device_settings & 1)
+ v |= 1 << 4;
+ if (ncr->rc->device_settings & 2)
+ v |= 1 << 5;
+ if (ncr->rc->device_settings & 4)
+ v |= 1 << 3;
+ if (ncr->rc->device_settings & 8)
+ v |= 1 << 7;
+ if (ncr->rc->device_settings & 16)
+ v |= 1 << 6;
+ v |= ncr->rc->device_id & 7;
+ return v;
+ } else if (addr == 0xa001) {
+ v = ncr->boardirq ? 1 : 0;
+ if (ncr->rc->device_settings & (1 << 5))
+ v |= 2;
+ return v;
+ }
+ if (addr < 0x8000 || addr >= 0x8000 + 0x100)
+ return 0xff;
+ reg_shift = 1;
+
} else if (isncr(ncr, ncr_fastlane_scsi)) {
if (addr >= FASTLANE_HARDBITS) {
if (addr == FASTLANE_HARDBITS) {
addr >>= reg_shift;
addr &= IO_MASK;
v = esp_reg_read(ncr->devobject.lsistate, (addr));
+ *reg = addr;
+ return v;
+}
+
+static uae_u32 ncr9x_io_bget(struct ncr9x_state *ncr, uaecptr addr)
+{
+ int reg = -1;
+ uae_u8 v = ncr9x_io_bget3(ncr, addr, ®);
#if NCR_DEBUG > 1
- write_log(_T("ESP read %02X (%08X) %02X %08X\n"), addr, oldaddr, v, M68K_GETPC);
+ if (ncr)
+ write_log(_T("ESP read %02X (%08X) %02X %08X\n"), reg & 0xff, addr, v, M68K_GETPC);
#endif
return v;
}
uae_u32 v = val;
#if NCR_DEBUG > 5
- write_log(_T("ncr9x_bget2 %08x %02x %08x\n"), addr, (uae_u8)val, M68K_GETPC);
+ write_log(_T("ncr9x_bput %08x %02x %08x\n"), addr, (uae_u8)val, M68K_GETPC);
#endif
addr &= ncr->board_mask;
return true;
}
+static const uae_u8 alf3_autoconfig[16] = {
+ 0xd1, 0x03, 0x40, 0x00, 0x08, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0xC0, 0x16, 0x68
+};
+
+bool ncr_alf3_autoconfig_init(struct autoconfig_info *aci)
+{
+ struct zfile *z = read_device_from_romconfig(aci->rc, ROMTYPE_ALF3);
+ if (z) {
+ zfile_fread(aci->autoconfig_raw, 128, 1, z);
+ zfile_fclose(z);
+ } else {
+ memcpy(aci->autoconfig_bytes, alf3_autoconfig, 16);
+ aci->autoconfigp = aci->autoconfig_bytes;
+ }
+ if (!aci->doinit) {
+ return true;
+ }
+
+ struct ncr9x_state *ncr = getscsi(aci->rc);
+ if (!ncr)
+ return false;
+
+ xfree(ncr->rom);
+ ncr->rom = NULL;
+ eeprom_free(ncr->eeprom);
+ ncr->eeprom = NULL;
+
+ ncr->enabled = true;
+ memset(ncr->acmemory, 0xff, sizeof ncr->acmemory);
+ ncr->rom_start = 0;
+ ncr->rom_offset = 0;
+ ncr->rom_end = 0x8000;
+ ncr->io_start = 0x8000;
+ ncr->io_end = ncr->io_start + 0x8000;
+ ncr->romisoddonly = true;
+ ncr->bank = &ncr9x_bank_generic;
+
+ ncr->irq6 = (ncr->rc->device_settings & (1 << 5)) == 0;
+
+ ncr->rom = xcalloc(uae_u8, 65536);
+ memset(ncr->rom, 0xff, 65536);
+
+ ncr9x_reset_board(ncr);
+
+ z = read_device_from_romconfig(aci->rc, ROMTYPE_ALF3);
+ if (z) {
+ zfile_fread(ncr->rom, 32768, 1, z);
+ zfile_fclose(z);
+ }
+
+ if (!z) {
+ for (int i = 0; i < 16; i++) {
+ uae_u8 v = alf3_autoconfig[i];
+ if (ncr->rc->autoboot_disabled && i == 0)
+ v &= ~0x10;
+ ew(ncr, i * 4, v);
+ }
+ } else {
+ if (ncr->rc->autoboot_disabled)
+ ncr->rom[0] &= ~0x10;
+ for (int i = 0; i < 128; i++) {
+ ncr->acmemory[i] = ncr->rom[i];
+ }
+ }
+
+ aci->addrbank = ncr->bank;
+ return true;
+}
+
static const uae_u8 dkb_autoconfig[16] = {
0xd2, 0x12, 0x40, 0x00, 0x07, 0xdc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80
};
ncr9x_esp_scsi_init(ncr_oktagon2008_scsi[ci->controller_type_unit], fake2_dma_read, fake2_dma_write, set_irq2_oktagon, 0);
}
+void alf3_add_scsi_unit(int ch, struct uaedev_config_info *ci, struct romconfig *rc)
+{
+ ncr9x_add_scsi_unit(&ncr_alf3_scsi[ci->controller_type_unit], ch, ci, rc);
+ ncr9x_esp_scsi_init(ncr_alf3_scsi[ci->controller_type_unit], fake2_dma_read, fake2_dma_write, set_irq2_alf3, 0);
+}
+
void masoboshi_add_scsi_unit (int ch, struct uaedev_config_info *ci, struct romconfig *rc)
{
ncr9x_add_scsi_unit(&ncr_masoboshi_scsi[ci->controller_type_unit], ch, ci, rc);
return NULL;
}
-#define NEXT_ROM_ID 224
+#define NEXT_ROM_ID 225
#define ALTROM(id,grp,num,size,flags,crc32,a,b,c,d,e) \
{ _T("X"), 0, 0, 0, 0, 0, size, id, 0, 0, flags, (grp << 16) | num, 0, NULL, crc32, a, b, c, d, e },
0xb0225f48, 0x2b170b40, 0x2f60d28c, 0x344fc463, 0x7e99915f, 0x92e0e8f1, NULL, NULL },
{ _T("Profex Electronics HD 3300"), 22, 0, 22, 0, _T("PROFEXHD3300\0"), 8192, 223, 0, 0, ROMTYPE_PROFEX, 0, 0, NULL,
0xfe4bf404, 0xc6c1e465, 0xc05e4794, 0xee76c9e2, 0x94def44d, 0x1c7560a1, NULL, NULL },
+ { _T("Elsat Mega Ram HD"), 1, 0, 1, 0, _T("ELSATHD\0"), 16384, 224, 0, 0, ROMTYPE_ELSATHD, 0, 0, NULL,
+ 0x1b854f6b, 0xc39d6202, 0xccb65f17, 0x63d1835e, 0x19d5b63d, 0x28f1b6a3, NULL, NULL },
+ ALTROMPN(224, 1, 1, 8192, ROMTYPE_ODD | ROMTYPE_8BIT, NULL, 0x3ba56b91, 0xef55760e, 0x8d5a5408, 0x7062f9ab, 0xc63ef067, 0x0b23f108)
+ ALTROMPN(224, 1, 2, 8192, ROMTYPE_EVEN | ROMTYPE_8BIT, NULL, 0x20c2cbb6, 0xb83d7406, 0x6c335a77, 0x0acb30d6, 0xff79a00f, 0x629a6953)
{ _T("CyberStorm MK I 68040"), 0, 0, 0, 0, _T("CSMKI\0"), 32768, 95, 0, 0, ROMTYPE_CB_CSMK1, 0, 0, NULL,
0, 0, 0, 0, 0, 0, NULL, _T("cyberstormmk1_040.rom") },