}
ssw |= fc & MMU_SSW_TM; /* TM = FC */
- regs.wb3_status = write ? 0x80 | (ssw & 0x7f) : 0;
- regs.wb2_status = 0;
switch (size) {
case sz_byte:
case sz_long:
ssw |= MMU_SSW_SIZE_L;
break;
- case 16: // MOVE16
+ }
+
+ regs.wb3_status = write ? 0x80 | (ssw & 0x7f) : 0;
+ regs.wb2_status = 0;
+ if (!write)
+ ssw |= MMU_SSW_RW;
+
+ if (size == 16) { // MOVE16
ssw |= MMU_SSW_SIZE_L; // ?? maybe MMU_SSW_SIZE_CL?
ssw |= MMU_SSW_TT0;
regs.mmu_effective_addr &= ~15;
regs.wb2_address = regs.mmu_effective_addr;
write_log (_T("040 MMU MOVE16 WRITE FAULT!\n"));
}
- break;
}
- if (!write)
- ssw |= MMU_SSW_RW;
-
if (mmu040_movem) {
ssw |= MMU_SSW_CM;
regs.mmu_effective_addr = mmu040_movem_ea;