{
uae_u16 opw1 = (opcode_memory[2] << 8) | (opcode_memory[3] << 0);
uae_u16 opw2 = (opcode_memory[4] << 8) | (opcode_memory[5] << 0);
- if (opc == 0x4e72
- && opw1 == 0xb000
+ if (opc == 0x4a10
+ //&& opw1 == 0xb000
//&& opw2 == 0xf78c
)
printf("");
if (!feature_loop_mode) {
// trace after NOP
if (SPCFLAG_DOTRACE) {
- if (trace_store_pc != 0xffffffff) {
- wprintf(_T(" Stand-alone trace detected twice!\n"));
- abort();
- }
MakeSR();
- trace_store_pc = regs.pc;
- trace_store_sr = regs.sr;
- SPCFLAG_DOTRACE = 0;
+ // store only first
+ if (trace_store_pc == 0xffffffff) {
+ trace_store_pc = regs.pc;
+ trace_store_sr = regs.sr;
+ SPCFLAG_DOTRACE = 0;
+ }
// STOP can only end with exception, fake prefetch here.
if (dp->mnemo == i_STOP) {
regs.ir = get_word_test(regs.pc + 0);
regs.irc = get_word_test(regs.pc + 2);
}
}
+ if (currprefs.cpu_model >= 68020) {
+ regs.ir = get_word_test(regs.pc + 0);
+ regs.irc = get_word_test(regs.pc + 2);
+ }
opc = regs.ir;
continue;
}
pc += handle_specials_preea(opc, pc, dp);
-
uae_u32 srcea = 0xffffffff;
uae_u32 dstea = 0xffffffff;
}
// requested target address but no EA? skip
- if (target_address != 0xffffffff && !isbranchinst(dp)) {
+ if (target_address != 0xffffffff) {
if (srcea != target_address && dstea != target_address) {
memcpy(opcode_memory, oldbytes, sizeof(oldbytes));
continue;
if ((dflags & 1) && target_ea[0] != 0xffffffff && srcaddr != 0xffffffff && srcaddr != target_ea[0]) {
wprintf(_T(" Source address mismatch %08x <> %08x\n"), target_ea[0], srcaddr);
- abort();
+ continue;;
}
if ((dflags & 2) && target_ea[1] != 0xffffffff && dstaddr != target_ea[1]) {
wprintf(_T(" Destination address mismatch %08x <> %08x\n"), target_ea[1], dstaddr);
- abort();
+ continue;;
}
if ((dflags & 1) && target_ea[0] == 0xffffffff && (srcaddr & addressing_mask) >= safe_memory_start - 4 && (srcaddr & addressing_mask) < safe_memory_end + 4) {
}
noaccesshistory--;
- MakeSR();
-
if (SPCFLAG_DOTRACE && test_exception_extra) {
wprintf(_T(" Trace and stored trace at the same time!\n"));
abort();
// did we have trace also active?
if (SPCFLAG_DOTRACE) {
- if (regs.t1 && (test_exception == 5 || test_exception == 6 || test_exception == 7 || (test_exception >= 32 && test_exception <= 47))) {
+ if ((regs.t1 || regs.t0) && (test_exception == 5 || test_exception == 6 || test_exception == 7 || (test_exception >= 32 && test_exception <= 47))) {
test_exception_extra = 9;
} else {
test_exception_extra = 0;
}
- // clear trace
- regs.t0 = 0;
- regs.t1 = 0;
}
if (trace_store_pc != 0xffffffff) {
test_exception_extra = 9 | 0x80;
}
+ MakeSR();
if (!skipped) {
bool storeregs = true;
ccr_done++;
} else {
*dst++ = CT_END_SKIP;
+ last_exception_len = -1;
}
undo_memory(ahist, &ahcnt);
}
memcpy(opcode_memory, oldbytes, sizeof(oldbytes));
test_count = prev_test_count;
subtest_count = prev_subtest_count;
+ last_exception_len = -1;
} else {
full_format_cnt++;
}
; CCR/FPU status flags mode
; 0 = all combinations (32 CCR loops, 256 FPU loops)
; 1 = all zeros and all ones only (2 CCR loops, 32 FPU loops)
+; Xcc type instruction (Bcc, DBcc etc) always forces all combinations mode
feature_flags_mode=1
; SR min interrupt mask
uae_u8 *p = mem;
int offset = 0;
int lines = 0;
- while (lines++ < 10) {
+ while (lines++ < 5) {
int v = 0;
if (!is_valid_test_addr((uae_u32)p) || !is_valid_test_addr((uae_u32)p + 1))
break;
tmpbuffer[0] = 0;
if (!(((uae_u32)code) & 1)) {
v = disasm_instr(code + offset, tmpbuffer);
+ sprintf(outbp, "%08lx ", p);
+ outbp += strlen(outbp);
for (int i = 0; i < v; i++) {
uae_u16 v = (p[i * 2 + 0] << 8) | (p[i * 2 + 1]);
- sprintf(outbp, "%s %08lx %04x", i ? " " : (lines == 0 ? "\t\t" : "\t"), &p[i * 2], v);
+ sprintf(outbp, "%04x ", v);
outbp += strlen(outbp);
}
sprintf(outbp, " %s\n", tmpbuffer);
infoadded = 1;
if (!dooutput)
return;
- sprintf(outbp, "%lu:", testcnt);
- outbp += strlen(outbp);
out_disasm(opcode_memory);
int fpumode = fpu_model && (opcode_memory[0] & 0xf0) == 0xf0;
- if (cpu_lvl >= 2)
- flushcache(cpu_lvl);
-
uae_u32 pc = opcode_memory_addr;
uae_u32 originalopcodeend = 0x4afc4e71;
uae_u8 *opcode_memory_end = (uae_u8*)pc;
}
}
uae_u32 opcodeend = originalopcodeend;
-
int extraccr = 0;
uae_u32 last_pc = opcode_memory_addr;
if ((ccr_mask & ccr) || (ccr == 0)) {
reset_error_vectors();
-
+#if 0
+ volatile int *tn = (volatile int*)0x100;
+ *tn = testcnt;
+#endif
if (cpu_lvl == 1) {
execute_test010(&test_regs);
} else if (cpu_lvl >= 2) {
+ flushcache(cpu_lvl);
if (fpu_model)
execute_testfpu(&test_regs);
else
filecnt++;
}
+ printf("%lu ", testcnt);
printf("S=%ld", supercnt);
for (int i = 0; i < 128; i++) {
if (exceptioncount[i]) {
Tester compatibility (integer instructions only):
-68000: Complete. (Bus errors are not yet verified)
-68010: Not supported yet (Don't have real 68010, at least not yet).
-68020: Almost complete (DIVS.W/DIVS.L V-flag weirdness).
+68000: Complete. Bus errors are only supported partially.
+68010: Partially supported.
+68020: Almost complete (DIV undocumented behavior is not yet known)
68030: Same as 68020.
68040: Almost complete (Weird unaligned MOVE16 behavior which may be board specific).
68060: Same as 68040.
All 3 memory regions (if RAM) are filled with pseudo-random pattern and saved as "lmem.dat", "hmem.dat" and "tmem.dat"
+Use feature_target_src_ea/feature_target_dst_ea=<one or more addresses separated by a comman> if you want generate test set that only uses listed addresses (of course instructions that can have memory source or destination EA are used). Useful for bus and address errors.
+
Usage of Amiga m68k native test program:
Copy all memory dat files, test executable compiled for target platform (currently only Amiga is supported) and data/<cpu model> contents to target system, keeping original directory structure.
}
setpc("srca");
clear_m68k_offset();
+ if (cpu_level >= 2 && cpu_level < 4)
+ printf("\tm68k_areg (regs, 7) -= 4;\n");
if (using_exception_3 && cpu_level >= 2) {
printf("\tif (%s & 1) {\n", getpc);
printf("\t\texception3i (opcode, %s);\n", getpc);
need_endlabel = 1;
}
fill_prefetch_1(0);
- if (cpu_level < 4)
+ if (cpu_level < 2)
printf("\tm68k_areg (regs, 7) -= 4;\n");
if (using_exception_3 && cpu_level <= 1) {
printf("\tif (m68k_areg(regs, 7) & 1) {\n");
genamodedual (curi,
curi->smode, "srcreg", curi->size, "src", 1, GF_AA | (cpu_level < 2 ? GF_NOREFILL : 0),
curi->dmode, "dstreg", curi->size, "offs", 1, GF_AA | (cpu_level < 2 ? GF_NOREFILL : 0));
- //genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_AA | GF_NOREFILL);
- //genamode (curi, curi->dmode, "dstreg", curi->size, "offs", 1, 0, GF_AA | GF_NOREFILL);
printf ("\tuaecptr oldpc = %s;\n", getpc);
addcycles000 (2);
if (using_exception_3 && cpu_level >= 4) {
printf ("\tif (!cctrue (%d)) {\n", curi->cc);
printf("\t");
incpc ("(uae_s32)offs + 2");
+ if (cpu_level >= 2 && cpu_level < 4)
+ genastore("(src - 1)", curi->smode, "srcreg", curi->size, "src");
printf ("\t");
if (using_exception_3 && cpu_level < 4) {
printf("\tif (offs & 1) {\n");
printf("\t");
fill_prefetch_1(0);
printf("\t");
- genastore ("(src - 1)", curi->smode, "srcreg", curi->size, "src");
+ if (cpu_level < 2 || cpu_level >= 4)
+ genastore ("(src - 1)", curi->smode, "srcreg", curi->size, "src");
printf ("\t\tif (src) {\n");
irc2ir ();
add_head_cycs (6);