struct picasso_vidbuf_description *vidinfo = &picasso_vidinfo[monid];
uaecptr bi = trap_get_areg(ctx, 0);
boardinfo = bi;
- int x = (uae_s16)trap_get_word(ctx, bi + PSSO_BoardInfo_MouseX) - state->XOffset;
- int y = (uae_s16)trap_get_word(ctx, bi + PSSO_BoardInfo_MouseY) - state->YOffset;
+ int x = (uae_s16)trap_get_dreg(ctx, 0) - state->XOffset;
+ int y = (uae_s16)trap_get_dreg(ctx, 1) - state->YOffset;
if (vidinfo->splitypos >= 0) {
y += vidinfo->splitypos;
}
#define LANG_DLL_FULL_VERSION_MATCH 1
#if WINUAEPUBLICBETA
-#define WINUAEBETA _T("Beta 19")
+#define WINUAEBETA _T("Beta 20")
#else
#define WINUAEBETA _T("")
#endif
-#define WINUAEDATE MAKEBD(2021, 4, 28)
+#define WINUAEDATE MAKEBD(2021, 5, 16)
//#define WINUAEEXTRA _T("AmiKit Preview")
//#define WINUAEEXTRA _T("Amiga Forever Edition")
TCHAR *ss;
bool npcap = true;
TCHAR sname[MAX_DPATH];
- int isdll;
if (enumerated) {
return enumit (name);
+Beta 20:
+
+- Blitter internal RGA bus pipeline emulation implemented.
+- When blitter was started for the first time and cycle-exact mode: blitter idle time from start of scanline to BLTSIZE write position was not emulated cycle-exactly. Almost harmless previously, now it caused visible problems with statefiles that expected blitter to steal all cycles. Very old bug.
+- Copper didn't stop when both COPJMP1 and COPJMP2 was strobed without active copper DMA. (b18)
+- Copper WAIT wrong special case fixed. (Hotbleeps and EyeQlazer)
+- Blitter register modification while active update. (For example fixes Demo Mix 5 intro / Tommyknockers). Not 100% yet.
+- AGA FMODE bit 14 bitplane scandoubling odd/even scanlines were swapped. (b18)
+- Optimized mode bitplane emulation didn't do anything if scanline's bitplane pointers crossed end of chip ram. Normally never happens but really weird programs or free running bitplane pointers might not have been 100% accurately emulated ("Warning: Bad playfield pointer" message). Ancient bug with ancient comment (probably from pre-0.8 UAE) that this should be fixed someday..
+- Some more UHRES parts implemented. (Yes, this is useless but cycle usage still should match real hardware if UHRES is enabled for some weird reason!)
+- b18 FSINCOS update broke non-softfloat FSINCOS.
+
Beta 19:
- Bitplane max plane limit was calculated before internal aga=true variable was set. Loading AGA statefile forced OCS/ECS limits if FMODE not updated in copper list.