fwrite(data, 1, 4, f);
pl(data, opcode_memory_start - test_memory_start);
fwrite(data, 1, 4, f);
- pl(data, (cpu_lvl << 16) | sr_undefined_mask | (addressing_mask == 0xffffffff ? 0x80000000 : 0) | ((feature_flag_mode & 1) << 30));
+ pl(data, (cpu_lvl << 16) | sr_undefined_mask | (addressing_mask == 0xffffffff ? 0x80000000 : 0) | ((feature_flag_mode & 1) << 30) | (feature_min_interrupt_mask << 20));
fwrite(data, 1, 4, f);
pl(data, currprefs.fpu_model);
fwrite(data, 1, 4, f);
dst = store_fpureg(dst, CT_FPREG + i, cur_fpuregisters[i]);
regs.fp[i].fpx = cur_fpuregisters[i];
}
+ regs.sr = feature_min_interrupt_mask << 8;
for (int opcode = 0; opcode < 65536; opcode++) {
} else {
regs.sr = ((ccr & 1) ? 31 : 0) | sr_mask;
}
+ regs.sr |= feature_min_interrupt_mask << 8;
regs.usp = regs.regs[8 + 7];
regs.isp = test_memory_end - 0x80;
// copy user stack to super stack, for RTE etc support
static uae_u32 opcode_memory_addr;
static uae_u8 *low_memory;
static uae_u8 *high_memory;
-static uae_u32 low_memory_size;
-static uae_u32 high_memory_size;
+static int low_memory_size;
+static int high_memory_size;
static uae_u8 *test_memory;
static uae_u32 test_memory_addr;
static uae_u32 test_memory_size;
static int quit;
static uae_u8 ccr_mask;
static uae_u32 addressing_mask = 0x00ffffff;
+static uae_u32 interrupt_mask;
#ifndef M68K
char *name;
int bit;
};
-static struct srbit srbits[] = {
+static const struct srbit srbits[] = {
{ "T1", 15 },
{ "T0", 14 },
{ "M", 13 },
errors = 0;
memset(®s, 0, sizeof(struct registers));
+ regs.sr = interrupt_mask << 8;
start_test();
} else {
test_regs.sr = (ccr ? 31 : 0);
}
- test_regs.sr |= sr_mask;
+ test_regs.sr |= sr_mask | (interrupt_mask << 8);
uae_u32 test_sr = test_regs.sr;
if (fpumode) {
if (flag_mode == 0) {
opcode_memory_addr = gl(data) + test_memory_addr;
fread(data, 1, 4, f);
lvl = (gl(data) >> 16) & 15;
+ interrupt_mask = (gl(data) >> 20) & 7;
addressing_mask = (gl(data) & 0x80000000) ? 0xffffffff : 0x00ffffff;
flag_mode = (gl(data) >> 30) & 1;
sr_undefined_mask = gl(data) & 0xffff;