Set correct I/N bit when address error starts because of odd exception vector.

diff --git a/cputest.cpp b/cputest.cpp
index 81d1b349eb180c030f1e02b694970b1fd2745a03..0846d9eb1a76677c860aeb05901a1e3276255c41 100644 (file)
--- a/cputest.cpp
+++ b/cputest.cpp
@@ -974,6 +974,8 @@ static void doexcstack2(void)
 
 static void doexcstack(void)
 {
+       bool g1 = generates_group1_exception(regs.ir);
+
        doexcstack2();
        if (cpu_lvl >= 2)
                return;
@@ -1021,6 +1023,12 @@ static void doexcstack(void)
                flags |= 0x10000 | 0x20000;
        }
 
+       // set I/N if original exception was group 1 exception.
+       flags |= 0x20000;
+       if (g1) {
+               flags |= 0x10000;
+       }
+
        exception3_read(regs.ir | flags, test_exception_addr, 1, 2);
 }
 

diff --git a/cputest/cputestgen.ini b/cputest/cputestgen.ini
index b7137416416b58c429d55e1e36dbacda1051ad05..518a326b3cbe9e5a9f61ac7772031b715a343c1b 100644 (file)
--- a/cputest/cputestgen.ini
+++ b/cputest/cputestgen.ini
@@ -202,7 +202,7 @@ mode=rts,rtd,rtr,jsr,bsr,link,unlk,pea
 [test=ODD_EXC]
 enabled=0
 feature_exception_vectors=0x000123
-mode=chk,trap,trapv,divu,divs,orsr
+mode=mv2sr.w,mvusp2r,mvr2usp,illegal,chk,trap,trapv,divu,divs,orsr.w
 
 ; interrupt exception with odd interrupt vectors
 [test=ODD_IRQ]

diff --git a/newcpu.cpp b/newcpu.cpp
index 3a64de3a5d20076dd1fbf02d58d94cc339b858bd..5142c3449302d7985748e192f2a727e99e10ecff 100644 (file)
--- a/newcpu.cpp
+++ b/newcpu.cpp
@@ -2504,6 +2504,7 @@ static void Exception_ce000 (int nr)
        exception_debug (nr);
        MakeSR ();
 
+       bool g1 = generates_group1_exception(regs.ir);
        if (!regs.s) {
                regs.usp = m68k_areg (regs, 7);
                m68k_areg (regs, 7) = regs.isp;
@@ -2616,7 +2617,7 @@ kludge_me_do:
                                regs.ir = nr;
                                exception3_read(regs.ir | 0x20000 | 0x10000, newpc, sz_word, 2);
                        } else {
-                               exception3_read(regs.ir | 0x40000, newpc, sz_word, 2);
+                               exception3_read(regs.ir | 0x40000 | 0x20000 | (g1 ? 0x10000 : 0), newpc, sz_word, 2);
                        }
                } else if (currprefs.cpu_model == 68010) {
                        // offset, not vbr + offset
@@ -2872,13 +2873,17 @@ static void Exception_normal (int nr)
        int sv = regs.s;
        int interrupt;
        int vector_nr = nr;
+       bool g1 = false;
 
        cache_default_data |= CACHE_DISABLE_ALLOCATE;
 
        interrupt = nr >= 24 && nr < 24 + 8;
 
-       if (interrupt && currprefs.cpu_model <= 68010)
-               vector_nr = iack_cycle(nr);
+       if (currprefs.cpu_model <= 68010) {
+               g1 = generates_group1_exception(regs.ir);
+               if (interrupt)
+                       vector_nr = iack_cycle(nr);
+       }
 
        exception_debug (nr);
        MakeSR ();
@@ -3094,7 +3099,7 @@ kludge_me_do:
                                regs.ir = nr;
                                exception3_read(regs.ir | 0x20000 | 0x10000, newpc, sz_word, 2);
                        } else {
-                               exception3_read(regs.ir | 0x40000, newpc, sz_word, 2);
+                               exception3_read(regs.ir | 0x40000 | 0x20000 | (g1 ? 0x10000 : 0), newpc, sz_word, 2);
                        }
                } else if (currprefs.cpu_model == 68010) {
                        regs.t1 = 0;