2820b7

diff --git a/cia.cpp b/cia.cpp
index ad3d76891f29515284b60972bc55111031511225..b1dcbc87657af3a62daa3583c63f11a9c18d209e 100644 (file)
--- a/cia.cpp
+++ b/cia.cpp
@@ -1327,14 +1327,14 @@ static void WriteCIAA (uae_u16 addr, uae_u8 val)
                val &= 0x7f; /* bit 7 is unused */
                if ((val & 1) && !(ciaacra & 1))
                        ciaastarta = CIASTARTCYCLESCRA;
-               if ((val & 0x40) != 0 (ciaacra & 0x40)) {
+               if ((val & 0x40) != (ciaacra & 0x40)) {
+                       /* bleh, Phase5 CPU timed early boot key check fix.. */
                        if (m68k_getpc() >= 0xf00000 && m68k_getpc() < 0xf80000)
                                check_keyboard();
                }
                if ((val & 0x40) == 0 && (ciaacra & 0x40) != 0) {
                        /* todo: check if low to high or high to low only */
                        kblostsynccnt = 0;
-                       /* bleh, Phase5 CPU timed early boot key check fix.. */
 #if KB_DEBUG
                        write_log (_T("KB_ACK %02x->%02x\n"), ciaacra, val);
 #endif

diff --git a/cpuboard.cpp b/cpuboard.cpp
index 65a641aeb1f4bfa8ecbc056c67ff06aaf798558d..9a3ebcfcfbd85d5476c068c9b6471934b278d813 100644 (file)
--- a/cpuboard.cpp
+++ b/cpuboard.cpp
@@ -1331,6 +1331,10 @@ addrbank *cpuboard_autoconfig_init(void)
                earom_size = 131072;
                f0rom_size = 65536;
                zfile_fread(blizzardea_bank.baseaddr, earom_size, 1, autoconfig_rom);
+               if (zfile_needwrite(autoconfig_rom)) {
+                       flashrom_file = autoconfig_rom;
+                       autoconfig_rom = NULL;
+               }
                flashrom = flash_new(blizzardea_bank.baseaddr, earom_size, earom_size, flashrom_file);
                memcpy(blizzardf0_bank.baseaddr, blizzardea_bank.baseaddr + 65536, 65536);
        } else if (is_csmk3() || is_blizzardppc()) {

diff --git a/newcpu.cpp b/newcpu.cpp
index 8a6a7b4b96da7428e1e3d717bca17088aeb25cbc..06911a851c9609d586a08c8279dae355e3667a5e 100644 (file)
--- a/newcpu.cpp
+++ b/newcpu.cpp
@@ -1375,10 +1375,8 @@ static void prefs_changed_cpu (void)
        currprefs.int_no_unimplemented = changed_prefs.int_no_unimplemented;
        currprefs.fpu_no_unimplemented = changed_prefs.fpu_no_unimplemented;
        currprefs.blitter_cycle_exact = changed_prefs.blitter_cycle_exact;
-       currprefs.reset_delay = changed_prefs.reset_delay;
 }
 
-
 static int check_prefs_changed_cpu2(void)
 {
        int changed = 0;
@@ -1407,22 +1405,20 @@ static int check_prefs_changed_cpu2(void)
        return cpu_prefs_changed_flag;
 }
 
-
 void check_prefs_changed_cpu(void)
 {
        if (!config_changed)
                return;
 
-       if (currprefs.cpu_idle != changed_prefs.cpu_idle) {
-               currprefs.cpu_idle = changed_prefs.cpu_idle;
-       }
+       currprefs.cpu_idle = changed_prefs.cpu_idle;
+       currprefs.reset_delay = changed_prefs.reset_delay;
+
        if (check_prefs_changed_cpu2()) {
                set_special(SPCFLAG_MODE_CHANGE);
                reset_frame_rate_hack();
        }
 }
 
-
 void init_m68k (void)
 {
        prefs_changed_cpu ();
@@ -2918,7 +2914,7 @@ static void mmu_op30fake_pmove (uaecptr pc, uae_u32 opcode, uae_u16 next, uaecpt
                siz = 8;
                if (rw) {
                        x_put_long (extra, fake_srp_030 >> 32);
-                       x_put_long (extra + 4, fake_srp_030);
+                       x_put_long (extra + 4, (uae_u32)fake_srp_030);
                } else {
                        fake_srp_030 = (uae_u64)x_get_long (extra) << 32;
                        fake_srp_030 |= x_get_long (extra + 4);
@@ -2929,7 +2925,7 @@ static void mmu_op30fake_pmove (uaecptr pc, uae_u32 opcode, uae_u16 next, uaecpt
                siz = 8;
                if (rw) {
                        x_put_long (extra, fake_crp_030 >> 32);
-                       x_put_long (extra + 4, fake_crp_030);
+                       x_put_long (extra + 4, (uae_u32)fake_crp_030);
                } else {
                        fake_crp_030 = (uae_u64)x_get_long (extra) << 32;
                        fake_crp_030 |= x_get_long (extra + 4);

diff --git a/od-win32/mman.cpp b/od-win32/mman.cpp
index 4e727b1bcc67d811eb8a3fc5033e115b8d47388b..4e19aa0a59b7fe00aab9934bffdb0b26d3971361 100644 (file)
--- a/od-win32/mman.cpp
+++ b/od-win32/mman.cpp
@@ -359,11 +359,12 @@ static int doinit_shm (void)
                if (changed_prefs.jit_direct_compatible_memory) {
                        p96mem_offset = natmem_offset + p96base_offset;
                } else {
+                       // calculate Z3 alignment (argh, I thought only Z2 needed this..)
+                       p96base_offset = (0x40000000 + changed_prefs.z3fastmem_size + changed_prefs.rtgmem_size - 1) & ~(changed_prefs.rtgmem_size - 1);                        
                        // adjust p96mem_offset to beginning of natmem
                        // by subtracting start of original p96mem_offset from natmem_offset
                        if (p96base_offset >= 0x10000000) {
-                               natmem_offset = natmem_offset_allocated - 0x40000000 - (p96base_offset - 0x10000000);
-                               p96base_offset += 0x40000000 - 0x10000000;
+                               natmem_offset = natmem_offset_allocated - p96base_offset;
                                p96mem_offset = natmem_offset + p96base_offset;
                        }
                }

diff --git a/od-win32/resources/winuae.rc b/od-win32/resources/winuae.rc
index 0ebad6097b7ce46b9bcf4721f425d8d46e4d85e7..6585a957566bc0c6a6b97ab90c2cd93bcad9abc8 100644 (file)
--- a/od-win32/resources/winuae.rc
+++ b/od-win32/resources/winuae.rc
@@ -209,7 +209,6 @@ BEGIN
     RTEXT           "Accelerator board memory:",IDC_STATIC,138,257,104,15,SS_CENTERIMAGE
     CONTROL         "",IDC_CPUBOARDMEM,"msctls_trackbar32",TBS_AUTOTICKS | TBS_TOP | WS_TABSTOP,251,253,68,20
     EDITTEXT        IDC_CPUBOARDRAM,326,256,40,12,ES_CENTER | ES_READONLY
-    CTEXT           "Accelerator board emulation is not JIT Direct compatible.",IDC_STATIC,25,238,341,15,SS_CENTERIMAGE
 END
 
 IDD_CPU DIALOGEX 0, 0, 396, 283

diff --git a/od-win32/win32.h b/od-win32/win32.h
index c5697c01e9e8357e05f0a2df235b7b2ea1e80dba..c7c0191a7d2e778711904230c71e1ff11f4d66b2 100644 (file)
--- a/od-win32/win32.h
+++ b/od-win32/win32.h
@@ -20,12 +20,12 @@
 #define LANG_DLL_FULL_VERSION_MATCH 1
 
 #if WINUAEPUBLICBETA
-#define WINUAEBETA _T("6")
+#define WINUAEBETA _T("7")
 #else
 #define WINUAEBETA _T("")
 #endif
 
-#define WINUAEDATE MAKEBD(2014, 7, 28)
+#define WINUAEDATE MAKEBD(2014, 7, 29)
 
 //#define WINUAEEXTRA _T("AmiKit Preview")
 //#define WINUAEEXTRA _T("Amiga Forever Edition")

diff --git a/od-win32/win32_uaenet.cpp b/od-win32/win32_uaenet.cpp
index 87d927cd689294ee37864971993f6f34d55cb072..7ea7a43ec07541d41232567daa16c51c450e25a3 100644 (file)
--- a/od-win32/win32_uaenet.cpp
+++ b/od-win32/win32_uaenet.cpp
@@ -21,6 +21,7 @@
 
 #include "sysdeps.h"
 #include "options.h"
+#include "sana2.h"
 
 #include "threaddep/thread.h"
 #include "win32_uaenet.h"
@@ -280,10 +281,6 @@ void uaenet_enumerate_free (void)
        int i;
 
        for (i = 0; i < MAX_TOTAL_NET_DEVICES; i++) {
-               xfree (tds[i].name);
-               xfree (tds[i].desc);
-               tds[i].name = NULL;
-               tds[i].desc = NULL;
                tds[i].active = 0;
        }
 }

diff --git a/od-win32/win32gui.cpp b/od-win32/win32gui.cpp
index 68a9361b74967d2305b47d2ae1cea8624166da63..5993365055f0eef8cb5a9ff118c0be81a3ef27d2 100644 (file)
--- a/od-win32/win32gui.cpp
+++ b/od-win32/win32gui.cpp
@@ -78,6 +78,7 @@
 #include "driveclick.h"
 #include "scsi.h"
 #include "cpuboard.h"
+#include "sana2.h"
 #ifdef PROWIZARD
 #include "moduleripper.h"
 #endif

diff --git a/od-win32/winuaechangelog.txt b/od-win32/winuaechangelog.txt
index bff519e62904e7762fff3a6452ac03d10eb37af7..6baf1b657e2fcf2ea57f0932b940fb169c2e398f 100644 (file)
--- a/od-win32/winuaechangelog.txt
+++ b/od-win32/winuaechangelog.txt
@@ -18,14 +18,116 @@ Things that may happen in 2015:
 
 - restore only single input target to default.
 
-- New statusline showed disk eject messages even if drive was already empty.
+Beta 7:
+
+- NCR93C94/FAS216 SCSI emulation write didn't work correct and wrote corrupted data, fixed. Added also check
+  that aborts transfer if SCSI chip and DMA controller data directions don't match (should never happen but...)
+- Flash chip emulation didn't emulate all "chip is still erasing" status bits, broke CSMK3/CSPPC/BPCC flasher.
+  Worked only accidentally in older version.
+- SCSI Kit rom checksum data was in wrong position, broke Blizzard 2060 odd/even rom loading.
+- CyberStorm MK2 flash update was not written back to rom file.
+- "JIT Direct compatible Z3 memory mapping" option with RTG enabled worked only in some configurations.
+
+Beta 6:
+
+- Added NCR53C94/FAS216 SCSI chip emulation (from QEMU)
+- Added Blizzard1230IV/Blizzard1260 + Blizzard SCSI Kit IV emulation. SCSI Kit v8.5 ROM added to rom scanner.
+- Added CyberStorm MK1 and CyberStorm MK2 emulation, map rom and SCSI included.
+- Blizzard 2060 (map rom not emulated) and Warp Engine works now.
+- CyberStorm PPC and Blizzard PPC 0xFFF00000 mapping improved, now switches correctly between KS map rom and
+  PPC boot code locations. BPPC now correctly attempts to start flash built-in PPC support code during boot
+  and hangs because PPC won't respond.
+- Added warning message when BlizzardPPC or CyberStormPPC PPC CPU gets booted.
+- Remap UAE Boot ROM (if needed) to secondary backup location if Blizzard PPC is enabled, if MMU emulation is
+  enabled BPPC will remap normal boot ROM backup location causing boot hang.
+- Added CyberStorm MK2 flash rom chip emulation, map rom and disable key support (=HALT4).
+- Added CyberStorm MK2 full 128k rom image support (64k of autoconfig rom and 64k of diag rom)
+- Flash chip emulation compatibility improved, fixed CSMK2 flasher infinite loop.
+- Accelerator memory option now automatically changes CPU board memory if accelerator uses same memory type.
+- Added keyboard hack to help Phase5 boot rom key detection, it still wasn't realiable enough with some boards.
+- Added one second boot delay option to misc panel, allows easy access to boot menus without need to
+  slow CPU emulation speed.
+- Added 'Te' command to debugger, shows expansion autoconfig board information.
+- CPU slot memory region was accidentally removed from mman list, causing random crashes in some JIT configurations.
+- 68040+ more compatible / "cycle-exact" mode cache flush instructions didn't do anything.
+
+About PPC emulation. It is now possible, at least technically, all other pieces are now done (at least partially).
+QEMU has license compatible and apparently very good PPC CPU emulator, including MMU and dynamic translation and
+it is proven to boot at least Linux.
+
+Only need someone who knows QEMU inside out and can create standalone PPC emulator module that is black box
+that only needs few functions: read physical address, write physical address, reset PPC, set interrupt level,
+set CPU parameters. There appears to be some kind of CPU API/class but because it is unstable, internal only API,
+there is no documentation.
+
+Note that I still don't care what happens will happens in PPC side. If/when Blizzard PPC/CyberStorm PPC can run
+some small PPC programs = it is done.
+
+Beta 5:
+
+Big accelerator board emulation update:
+
+Added CyberStorm MK3, CyberStorm PPC and Blizzard PPC. ! There is no PPC CPU ! Technically it emulates board
+with PPC CPU removed. (Which surprisingly does not seem to cause any problems, at least under emulation, real
+hardware may get confused if PPC chip is removed). SCSI fully supported, boot menu works, boot menu options
+can be modified and saved to flash, flash updater works. Map rom should work, including BlizKick.
+
+Boot menu config is saved to flash rom which means selected flash rom will be modified, only use copy of your
+flash rom image (If it is writable, files inside archives are never modified).
+
+You need to be really fast or select slower CPU mode if you want to enter boot menu (ESC key). This needs some
+emulator updates to allow easier way to press keys when starting emulation.
+
+Map ROM is software selectable in boot menu, map rom option in GUI does nothing when using these boards.
+
+Flash ROM images must have following names and must be in ROM directory because checksum based ROM detection can't work:
+- CyberStorm MK3: cyberstormmk3.rom
+- CyberStorm PPC: cyberstormppc.rom (emulates Phase5 version that has 128k flash, DCE 512k flash version not tested)
+- Blizzard PPC: blizzardppc.rom (Note: flash is 512k but second half is only used for config, if rom image
+is 256k (size you get if you simply dump the F0 space from real hardware), it gets extended to 512k after
+onfig save or flash update). ROM images uploaded to the zone.
+
+GUI/config file ROM selection will be added later. Note that real flash rom images also contain some card
+specific information (PPC CPU speed, serial number which also includes card type). This area is blank in rom
+images uploaded to the zone (they are from official flash updater, old serial is kept when flashing). blank
+serial does not seem to cause any problems but some software probably gets confused.
+
+NOTE: Only Blizzards use Accelerator board memory slider, other boards use CPU Board memory slider and Accelerator
+board slider still needs to be set to some non-zero memory amount. (Will be fixed later).
+
+Blizzard PPC seems to have something else in F50000 which may be important. (I only have CyberStorm PPC for
+testing). Blizzard is (and can't be) JIT compatible due to high RAM addresses and RAM mirroring, CyberStorms
+are much more JIT friendly but it is not guaranteed to be safe. Blizzard also does not boot if MMU emulation
+is enabled.
+
 - Added optional FPU emulation that uses softfloat library, another feature not for normal use.
   Full 80-bit FP accuracy, bit-perfect results (not including trigonometric functions), supports FPU
   arithmetic exceptions, much slower (Uses integer algorithms, host FPU is not used).
+- Added mostly unmodified Qemu 53c895a SCSI emulation (originally heavily modified for 53c710 emulation). It is
+  53c770 compatible, 53c770 is used in CyberStorm MK3 and CyberStorm PPC.
+- Some 53c710 updates, Blizzard PPC SCSI driver didn't work.
+- Added simple flash rom emulator.
+- Fastest possible CPU option is now available for cycle-exact modes. CPU internal cycles are not counted,
+  only (mainboard) memory accesses are cycle exact (DMA steals cycles from CPU) in this mode.
+- 68040/060 "cycle-exact" mode is back, emulates only Amiga mainboard memory accesses cycle-exactly, includes
+  instruction(*) cache emulation. Any 32-bit fast ram or cached access is still immediate. (Which is still
+  much closer to real 040/060 than old behavior, 040/060 is heavily bottle-necked when accessing mainboard)
+- 68040/060 "compatible" mode now adds instruction cache emulation.
+- 68030/040/60 MMU mode "more compatible" (68030: adds both instruction and data cache emulation, 68040/060:
+  instruction cache only) and "cycle-exact" modes supported. (more compatible + mainboard access slowed down)
+- 68030: data cache support is temporarily disabled. (Didn't work with MMU for some reasonm)
+- DFx: eject messages appeared in new status bar even if drive was already empty.
+- Right-align status messages in fullscreen mode.
+- A2065 autoconfig was broken (b4)
+- b1 directory filesystem change rewritten again, removed also lots of unneeded complexity from original code.
+- On screen CPU halt message reason code was always 1.
+- Generated virtual RDB (when IDE/SCSI mounting partition hardfile) created empty string for device name.
 - 270b6 "JIT MOVEM used direct mode if memory was direct capable but direct mode was disabled." was wrong
   fix, original code probably was done to work around some JIT indirect bug.. (AmiKit crash during boot
   if JIT is in indirect mode)
 
+*) Instruction cache only? because emulating data cache would not make any useful difference (except to slow
+down emulation), data cache normally does not cache any mainboard addresses anyway.
 
 Beta 4: