_T("x86athdprimary"), _T("AT IDE Primary"), NULL,
NULL, x86_at_hd_init_1, NULL, x86_add_at_hd_unit_1, ROMTYPE_X86_AT_HD1 | ROMTYPE_NOT, 0, 0, BOARD_NONAUTOCONFIG_AFTER_Z2, true,
NULL, 0,
- false, EXPANSIONTYPE_X86_EXPANSION
+ false, EXPANSIONTYPE_X86_EXPANSION | EXPANSIONTYPE_IDE,
},
{
_T("x86athdxt"), _T("XTIDE Universal BIOS HD"), NULL,
NULL, x86_at_hd_init_xt, NULL, x86_add_at_hd_unit_xt, ROMTYPE_X86_XT_IDE | ROMTYPE_NONE, 0, 0, BOARD_NONAUTOCONFIG_AFTER_Z2, true,
NULL, 0,
- false, EXPANSIONTYPE_X86_EXPANSION,
+ false, EXPANSIONTYPE_X86_EXPANSION | EXPANSIONTYPE_IDE,
0, 0, 0, false, NULL,
false, 0, x86_athdxt_settings
},
_T("x86rt1000"), _T("Rancho RT1000"), NULL,
NULL, x86_rt1000_init, NULL, x86_rt1000_add_unit, ROMTYPE_X86_RT1000 | ROMTYPE_NONE, 0, 0, BOARD_NONAUTOCONFIG_AFTER_Z2, true,
NULL, 0,
- false, EXPANSIONTYPE_X86_EXPANSION,
+ false, EXPANSIONTYPE_X86_EXPANSION | EXPANSIONTYPE_SCSI,
0, 0, 0, false, NULL,
false, 0, x86_rt1000_settings
_T("sb_isa"), _T("SoundBlaster ISA (Creative)"), NULL,
NULL, isa_expansion_init, NULL, NULL, ROMTYPE_SBISA | ROMTYPE_NOT, 0, 0, BOARD_NONAUTOCONFIG_BEFORE, true,
NULL, 0,
- false, EXPANSIONTYPE_SOUND,
+ false, EXPANSIONTYPE_X86_EXPANSION | EXPANSIONTYPE_SOUND,
0, 0, 0, false, NULL,
false, 0, sb_isa_settings
},
_T("ne2000_isa"), _T("RTL8019 ISA (NE2000 compatible)"), NULL,
NULL, isa_expansion_init, NULL, NULL, ROMTYPE_NE2KISA | ROMTYPE_NOT, 0, 0, BOARD_NONAUTOCONFIG_BEFORE, true,
NULL, 0,
- false, EXPANSIONTYPE_NET,
+ false, EXPANSIONTYPE_NET | EXPANSIONTYPE_X86_EXPANSION,
0, 0, 0, false, NULL,
false, 0, ne2k_isa_settings
},
#define X86_IO_PORT_DEBUG 0
#define X86_DEBUG_SPECIAL_IO 0
#define FLOPPY_DEBUG 0
+#define EMS_DEBUG 1
#define DEBUG_DMA 0
#define DEBUG_PIT 0
struct x86_bridge *xb = bridges[0];
resetx86();
-
-// CPU_ShutDown(dosbox_sec);
-// CPU_Init(dosbox_sec, xb->dosbox_cpu, xb->dosbox_cpu_arch);
-// CPU_JMP(false, 0xffff, 0, 0);
}
+static void reset_x86_hardware(struct x86_bridge *xb);
static void reset_x86_cpu(struct x86_bridge *xb)
{
write_log(_T("x86 CPU reset\n"));
-
reset_cpu();
- // reset x86 hd controllers
- x86_ide_hd_put(-1, 0, 0);
- x86_rt1000_bput(-1, 0);
}
uint8_t x86_get_jumpers(void)
case IO_CONTROL_REGISTER:
if (!(v & 0x4)) {
xb->x86_reset = true;
+ reset_x86_hardware(xb);
}
if (!(v & 1))
v |= 2;
}
+#define EMS_BANK 0x4000
+#define EMS_MASK 0x3fff
+
static uint8_t mem_read_emsb(uint32_t addr, void *priv)
{
- return ram[addr];
+ uint8_t *p = (uint8_t*)priv;
+ return p[addr & EMS_MASK];
}
static uint16_t mem_read_emsw(uint32_t addr, void *priv)
{
- return ((uint16_t*)&ram[addr])[0];
+ uint8_t *p = (uint8_t*)priv;
+ return ((uint16_t*)&p[addr & EMS_MASK])[0];
}
static uint32_t mem_read_emsl(uint32_t addr, void *priv)
{
- return ((uint32_t*)&ram[addr])[0];
+ uint8_t *p = (uint8_t*)priv;
+ return ((uint32_t*)&p[addr & EMS_MASK])[0];
}
static void mem_write_emsb(uint32_t addr, uint8_t val, void *priv)
{
- ram[addr] = val;
+ uint8_t *p = (uint8_t*)priv;
+ p[addr & EMS_MASK] = val;
}
static void mem_write_emsw(uint32_t addr, uint16_t val, void *priv)
{
- ((uint16_t*)&ram[addr])[0] = val;
+ uint8_t *p = (uint8_t*)priv;
+ ((uint16_t*)&p[addr & EMS_MASK])[0] = val;
}
static void mem_write_emsl(uint32_t addr, uint32_t val, void *priv)
{
- ((uint32_t*)&ram[addr])[0] = val;
+ uint8_t *p = (uint8_t*)priv;
+ ((uint32_t*)&p[addr & EMS_MASK])[0] = val;
}
static uint8_t mem_read_shadowb(uint32_t addr, void *priv)
}
static const uae_u32 shadow_bases[] = { 0xa0000, 0xc0000, 0xd0000, 0xe0000 };
-static const uae_u32 shadow_sizes[] = { 0x8000, 0x4000, 0x4000, 0x8000 };
+static const uae_u32 shadow_sizes[] = { 0x08000, 0x04000, 0x04000, 0x08000 };
static void vlsi_set_mapping(struct x86_bridge *xb)
{
uae_u32 baseaddr;
uae_u32 emsaddr;
if (i >= 0x0c) {
- baseaddr = 0x40000 + (i - 0x0c) * 0x4000;
+ baseaddr = 0x40000 + (i - 0x0c) * EMS_BANK;
} else {
bool emsmap = ((xb->vlsi_regs[0x0b] >> 4) & 1) != 0;
if (emsmap) {
if (i < 0x04)
- baseaddr = 0xa0000 + (i - 0) * 0x4000;
+ baseaddr = 0xa0000 + (i - 0) * EMS_BANK;
else if (i < 0x08)
- baseaddr = 0xd0000 + (i - 4) * 0x4000;
+ baseaddr = 0xd0000 + (i - 4) * EMS_BANK;
else
- baseaddr = 0xb0000 + (i - 8) * 0x4000;
+ baseaddr = 0xb0000 + (i - 8) * EMS_BANK;
} else {
- baseaddr = 0xc0000 + i * 0x4000;
+ baseaddr = 0xc0000 + i * EMS_BANK;
}
}
emsaddr = xb->vlsi_regs_ems[i] << 14;
if (((i < 0x0c && (emsenablebits & (1 << i))) || (i >= 0x0c && emsbackfillenable)) && emsenable) {
- mem_mapping_set_addr(m, baseaddr, 0x4000);
- mem_mapping_set_exec(m, ram + emsaddr);
+ uae_u8 *paddr = ram + emsaddr;
+#if EMS_DEBUG
+ if (!m->enable || m->base != baseaddr || m->exec != paddr)
+ write_log(_T("EMS %06x = %08x (%p)\n"), baseaddr, emsaddr, paddr);
+#endif
+ mem_mapping_set_p(m, paddr);
+ mem_mapping_set_addr(m, baseaddr, EMS_BANK);
+ mem_mapping_set_exec(m, paddr);
} else {
+#if EMS_DEBUG
+ if (m->enable)
+ write_log(_T("EMS %06x = -\n"), baseaddr);
+#endif
mem_mapping_disable(m);
}
}
}
// EMS
for (int i = 0x0; i < 0xc; i++) {
- uae_u32 addr = 0xa0000 + i * 0x4000;
- mem_mapping_add(&xb->ems[i], addr, 0x4000,
+ uae_u32 addr = 0xa0000 + i * EMS_BANK;
+ mem_mapping_add(&xb->ems[i], addr, EMS_BANK,
mem_read_emsb, mem_read_emsw, mem_read_emsl,
mem_write_emsb, mem_write_emsw, mem_write_emsl,
ram + addr, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL, NULL);
}
// EMS backfill
for (int i = 0x0c; i < 0x24; i++) {
- uae_u32 addr = 0x40000 + i * 0x4000;
- mem_mapping_add(&xb->ems[i], addr, 0x4000,
+ uae_u32 addr = 0x40000 + i * EMS_BANK;
+ mem_mapping_add(&xb->ems[i], addr, EMS_BANK,
mem_read_emsb, mem_read_emsw, mem_read_emsl,
mem_write_emsb, mem_write_emsw, mem_write_emsl,
ram + addr, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL, NULL);
xb->sltptr = 0xff;
}
+static void vlsi_reset(struct x86_bridge *xb)
+{
+ memset(xb->vlsi_regs, 0, sizeof xb->vlsi_regs);
+ vlsi_set_ems(xb, true);
+ vlsi_set_mapping(xb);
+}
+
+
static void vlsi_reg_out(struct x86_bridge *xb, int reg, uae_u8 v)
{
int shadowbase = -1;
case 0x0b: // ENSEN1
case 0x0c: // ENSEN2
+#if EMS_DEBUG
write_log(_T("ENSEN%d = %02x\n"), reg == 0x0b ? 1 : 2, v);
+#endif
vlsi_set_ems(xb, true);
vlsi_set_mapping(xb);
break;
case 0xeb:
xb->vlsi_regs_ems[xb->scamp_idx1 & 0x3f] &= 0x00ff;
xb->vlsi_regs_ems[xb->scamp_idx1 & 0x3f] |= v << 8;
- write_log(_T("EMS %d = %04x\n"), xb->vlsi_regs_ems[xb->scamp_idx1 & 0x3f]);
+#if EMS_DEBUG
+ write_log(_T("EMS %02d = %04x\n"), xb->scamp_idx1, xb->vlsi_regs_ems[xb->scamp_idx1 & 0x3f]);
+#endif
vlsi_set_ems(xb, false);
vlsi_set_mapping(xb);
vlsi_autoinc(xb);
// A2386SX only
case 0xe8:
case 0xea:
+ case 0xeb:
case 0xec:
case 0xed:
case 0xee:
// A2386SX only
case 0xe8:
case 0xea:
+ case 0xeb:
case 0xec:
case 0xed:
case 0xee:
void *mouse_ps2_init();
void *mouse_intellimouse_init();
void serial1_init(uint16_t addr, int irq);
+void serial_reset();
static void set_mouse(struct x86_bridge *xb)
{
if (!is_board_enabled(&currprefs, ROMTYPE_X86MOUSE, 0))
return;
struct romconfig *rc = get_device_romconfig(&currprefs, ROMTYPE_X86MOUSE, 0);
+ ps2_mouse_supported = false;
if (rc) {
xb->mouse_port = (rc->device_settings & 3) + 1;
xb->mouse_type = (rc->device_settings >> 2) & 3;
{
case 0:
default:
- ps2_mouse_supported = false;
serial1_init(0x3f8, 4);
+ serial_reset();
xb->mouse_base = mouse_serial_init();
break;
case 1:
return true;
}
+static void reset_x86_hardware(struct x86_bridge *xb)
+{
+ x86_ide_hd_put(-1, 0, 0);
+ x86_rt1000_bput(-1, 0);
+
+#if 0
+ if (xb->type >= TYPE_2386) {
+ vlsi_reset(xb);
+ }
+#endif
+ if (xb->ne2000_isa) {
+ xb->ne2000_isa->reset(xb->ne2000_isa_board_state);
+ }
+
+ serial_reset();
+}
+
+
void x86_map_lfb(int v)
{
struct x86_bridge *xb = bridges[0];