/* todo: check if low to high or high to low only */
kblostsynccnt = 0;
#if KB_DEBUG
- write_log (_T("KB_ACK %02x->%02x\n"), ciaacra, val);
+ write_log (_T("KB_ACK %02x->%02x %08x\n"), ciaacra, val, M68K_GETPC);
#endif
}
ciaacra = val;
/* -- MMU instructions -- */
-void mmu_op30_pmove (uaecptr pc, uae_u32 opcode, uae_u16 next, uaecptr extra)
+bool mmu_op30_pmove (uaecptr pc, uae_u32 opcode, uae_u16 next, uaecptr extra)
{
int preg = (next >> 10) & 31;
int rw = (next >> 9) & 1;
x_put_long (extra, tc_030);
else {
tc_030 = x_get_long (extra);
- mmu030_decode_tc(tc_030);
+ if (mmu030_decode_tc(tc_030))
+ return true;
}
break;
case 0x12: // SRP
} else {
srp_030 = (uae_u64)x_get_long (extra) << 32;
srp_030 |= x_get_long (extra + 4);
- mmu030_decode_rp(srp_030);
+ if (mmu030_decode_rp(srp_030))
+ return true;
}
break;
case 0x13: // CRP
} else {
crp_030 = (uae_u64)x_get_long (extra) << 32;
crp_030 |= x_get_long (extra + 4);
- mmu030_decode_rp(crp_030);
+ if (mmu030_decode_rp(crp_030))
+ return true;
}
break;
case 0x18: // MMUSR
default:
write_log (_T("Bad PMOVE at %08x\n"),m68k_getpc());
op_illg (opcode);
- return;
+ return true;
}
if (!fd && !rw && !(preg==0x18)) {
mmu030_flush_atc_all();
}
tt_enabled = (tt0_030 & TT_ENABLE) || (tt1_030 & TT_ENABLE);
+ return false;
}
-void mmu_op30_ptest (uaecptr pc, uae_u32 opcode, uae_u16 next, uaecptr extra)
+bool mmu_op30_ptest (uaecptr pc, uae_u32 opcode, uae_u16 next, uaecptr extra)
{
mmu030.status = mmusr_030 = 0;
if (!level && a) { /* correct ? */
write_log(_T("PTEST: Bad instruction causing F-line unimplemented instruction exception!\n"));
Exception(11); /* F-line unimplemented instruction exception */
- return;
+ return true;
}
#if MMU030_OP_DBG_MSG
(mmusr_030&MMUSR_INVALID)?1:0, (mmusr_030&MMUSR_MODIFIED)?1:0,
(mmusr_030&MMUSR_TRANSP_ACCESS)?1:0, mmusr_030&MMUSR_NUM_LEVELS_MASK);
#endif
+ return false;
}
-void mmu_op30_pload (uaecptr pc, uae_u32 opcode, uae_u16 next, uaecptr extra)
+bool mmu_op30_pload (uaecptr pc, uae_u32 opcode, uae_u16 next, uaecptr extra)
{
int rw = (next >> 9) & 1;
uae_u32 fc = mmu_op30_helper_get_fc(next);
mmu030_flush_atc_page(extra);
mmu030_table_search(extra, fc, write, 0);
+ return false;
}
-void mmu_op30_pflush (uaecptr pc, uae_u32 opcode, uae_u16 next, uaecptr extra)
+bool mmu_op30_pflush (uaecptr pc, uae_u32 opcode, uae_u16 next, uaecptr extra)
{
uae_u16 mode = (next&0x1C00)>>10;
uae_u32 fc_mask = (uae_u32)(next&0x00E0)>>5;
write_log(_T("PFLUSH ERROR: bad mode! (%i)\n"),mode);
break;
}
+ return false;
}
/* -- Helper function for MMU instructions -- */
#define TC_TID_MASK 0x0000000F
-void mmu030_decode_tc(uae_u32 TC) {
+bool mmu030_decode_tc(uae_u32 TC) {
/* Set MMU condition */
if (TC & TC_ENABLE_TRANSLATION) {
if (mmu030.enabled)
write_log(_T("MMU disabled\n"));
mmu030.enabled = false;
- return;
+ return false;
}
/* Note: 0 = Table A, 1 = Table B, 2 = Table C, 3 = Table D */
write_log(_T("MMU Configuration Exception: Bad value in TC register! (bad page size: %i byte)\n"),
1<<mmu030.translation.page.size);
Exception(56); /* MMU Configuration Exception */
- return;
+ return true;
}
mmu030.translation.page.mask = regs.mmu_page_size - 1;
mmu030.translation.page.imask = ~mmu030.translation.page.mask;
if ((shift-mmu030.translation.page.size)!=0) {
write_log(_T("MMU Configuration Exception: Bad value in TC register! (bad sum)\n"));
Exception(56); /* MMU Configuration Exception */
- return;
+ return true;
}
#if MMU030_REG_DBG_MSG /* enable or disable debugging output */
write_log(_T("TC: Last Table: %c\n"), table_letter[mmu030.translation.last_table]);
write_log(_T("\n"));
#endif
+ return false;
}
#define RP_ZERO_BITS 0x0000FFFC /* These bits in upper longword of RP must be 0 */
-void mmu030_decode_rp(uae_u64 RP) {
+bool mmu030_decode_rp(uae_u64 RP) {
uae_u8 descriptor_type = (RP & RP_DESCR_MASK) >> 32;
if (!descriptor_type) { /* If descriptor type is invalid */
write_log(_T("MMU Configuration Exception: Root Pointer is invalid!\n"));
Exception(56); /* MMU Configuration Exception */
+ return true;
}
+ return false;
#if MMU030_REG_DBG_MSG /* enable or disable debugging output */
uae_u32 table_limit = (RP & RP_LIMIT_MASK) >> 48;
{
uaecptr a;
+
+ // Warn if PPC doing autoconfig and UAE expansion enabled
+ static bool warned;
+ if (!warned && regs.halted < 0) {
+ warned = true;
+ // can't show dialogs from PPC thread, deadlock danger.
+ regs.halted = -2;
+ }
+
filesys_start = expamem_z2_pointer;
map_banks_z2 (&filesys_bank, filesys_start >> 16, 1);
/* 68k code needs to know this. */
#endif
/* Z3 boards last */
- if (currprefs.cpuboard_type == BOARD_WARPENGINE_A4000) {
- card_flags[cardno] = 1;
- card_name[cardno] = _T("Warp Engine");
- card_init[cardno] = expamem_init_warpengine;
- card_map[cardno++] = NULL;
- }
- if (z3fastmem_bank.baseaddr != NULL) {
- z3num = 0;
- card_flags[cardno] = 2 | 1;
- card_name[cardno] = _T("Z3Fast");
- card_init[cardno] = expamem_init_z3fastmem;
- card_map[cardno++] = expamem_map_z3fastmem;
- if (expamem_z3hack(&currprefs))
- map_banks (&z3fastmem_bank, z3fastmem_bank.start >> 16, currprefs.z3fastmem_size >> 16, z3fastmem_bank.allocated);
- if (z3fastmem2_bank.baseaddr != NULL) {
+ if (!currprefs.address_space_24) {
+
+ if (currprefs.cpuboard_type == BOARD_WARPENGINE_A4000) {
+ card_flags[cardno] = 1;
+ card_name[cardno] = _T("Warp Engine");
+ card_init[cardno] = expamem_init_warpengine;
+ card_map[cardno++] = NULL;
+ }
+ if (z3fastmem_bank.baseaddr != NULL) {
+ z3num = 0;
card_flags[cardno] = 2 | 1;
- card_name[cardno] = _T("Z3Fast2");
- card_init[cardno] = expamem_init_z3fastmem2;
- card_map[cardno++] = expamem_map_z3fastmem2;
+ card_name[cardno] = _T("Z3Fast");
+ card_init[cardno] = expamem_init_z3fastmem;
+ card_map[cardno++] = expamem_map_z3fastmem;
if (expamem_z3hack(&currprefs))
- map_banks (&z3fastmem2_bank, z3fastmem2_bank.start >> 16, currprefs.z3fastmem2_size >> 16, z3fastmem2_bank.allocated);
+ map_banks (&z3fastmem_bank, z3fastmem_bank.start >> 16, currprefs.z3fastmem_size >> 16, z3fastmem_bank.allocated);
+ if (z3fastmem2_bank.baseaddr != NULL) {
+ card_flags[cardno] = 2 | 1;
+ card_name[cardno] = _T("Z3Fast2");
+ card_init[cardno] = expamem_init_z3fastmem2;
+ card_map[cardno++] = expamem_map_z3fastmem2;
+ if (expamem_z3hack(&currprefs))
+ map_banks (&z3fastmem2_bank, z3fastmem2_bank.start >> 16, currprefs.z3fastmem2_size >> 16, z3fastmem2_bank.allocated);
+ }
}
- }
- if (z3chipmem_bank.baseaddr != NULL)
- map_banks (&z3chipmem_bank, z3chipmem_bank.start >> 16, currprefs.z3chipmem_size >> 16, z3chipmem_bank.allocated);
+ if (z3chipmem_bank.baseaddr != NULL)
+ map_banks (&z3chipmem_bank, z3chipmem_bank.start >> 16, currprefs.z3chipmem_size >> 16, z3chipmem_bank.allocated);
#ifdef PICASSO96
- if (currprefs.rtgmem_type == GFXBOARD_UAE_Z3 && gfxmem_bank.baseaddr != NULL) {
- card_flags[cardno] = 4 | 1;
- card_name[cardno] = _T("Z3RTG");
- card_init[cardno] = expamem_init_gfxcard_z3;
- card_map[cardno++] = expamem_map_gfxcard_z3;
- }
+ if (currprefs.rtgmem_type == GFXBOARD_UAE_Z3 && gfxmem_bank.baseaddr != NULL) {
+ card_flags[cardno] = 4 | 1;
+ card_name[cardno] = _T("Z3RTG");
+ card_init[cardno] = expamem_init_gfxcard_z3;
+ card_map[cardno++] = expamem_map_gfxcard_z3;
+ }
#endif
#ifdef GFXBOARD
- if (currprefs.rtgmem_type >= GFXBOARD_HARDWARE && gfxboard_is_z3 (currprefs.rtgmem_type)) {
- card_flags[cardno] = 4 | 1;
- card_name[cardno] = _T ("Gfxboard VRAM Zorro III");
- card_init[cardno] = expamem_init_gfxboard_memory;
- card_map[cardno++] = NULL;
- card_flags[cardno] = 1;
- card_name[cardno] = _T ("Gfxboard Registers");
- card_init[cardno] = expamem_init_gfxboard_registers;
- card_map[cardno++] = NULL;
- }
+ if (currprefs.rtgmem_type >= GFXBOARD_HARDWARE && gfxboard_is_z3 (currprefs.rtgmem_type)) {
+ card_flags[cardno] = 4 | 1;
+ card_name[cardno] = _T ("Gfxboard VRAM Zorro III");
+ card_init[cardno] = expamem_init_gfxboard_memory;
+ card_map[cardno++] = NULL;
+ card_flags[cardno] = 1;
+ card_name[cardno] = _T ("Gfxboard Registers");
+ card_init[cardno] = expamem_init_gfxboard_registers;
+ card_map[cardno++] = NULL;
+ }
#endif
#ifdef NCR
- if (cfgfile_board_enabled(&currprefs.a4091rom)) {
- card_flags[cardno] = 1;
- card_name[cardno] = _T("A4091");
- card_init[cardno] = expamem_init_a4091;
- card_map[cardno++] = NULL;
- card_flags[cardno] = 1;
- card_name[cardno] = _T("A4091 #2");
- card_init[cardno] = expamem_init_a4091_2;
- card_map[cardno++] = NULL;
- }
- if (cfgfile_board_enabled(&currprefs.fastlanerom)) {
- card_flags[cardno] = 1;
- card_name[cardno] = _T("Fastlane");
- card_init[cardno] = expamem_init_fastlane;
- card_map[cardno++] = NULL;
- card_flags[cardno] = 1;
- card_name[cardno] = _T("Fastlane #2");
- card_init[cardno] = expamem_init_fastlane_2;
- card_map[cardno++] = NULL;
- }
+ if (cfgfile_board_enabled(&currprefs.a4091rom)) {
+ card_flags[cardno] = 1;
+ card_name[cardno] = _T("A4091");
+ card_init[cardno] = expamem_init_a4091;
+ card_map[cardno++] = NULL;
+ card_flags[cardno] = 1;
+ card_name[cardno] = _T("A4091 #2");
+ card_init[cardno] = expamem_init_a4091_2;
+ card_map[cardno++] = NULL;
+ }
+ if (cfgfile_board_enabled(&currprefs.fastlanerom)) {
+ card_flags[cardno] = 1;
+ card_name[cardno] = _T("Fastlane");
+ card_init[cardno] = expamem_init_fastlane;
+ card_map[cardno++] = NULL;
+ card_flags[cardno] = 1;
+ card_name[cardno] = _T("Fastlane #2");
+ card_init[cardno] = expamem_init_fastlane_2;
+ card_map[cardno++] = NULL;
+ }
#endif
+ }
+
if (cardno > 0 && cardno < MAX_EXPANSION_BOARDS) {
card_flags[cardno] = 0;
card_name[cardno] = _T("Empty");
}
}
-static void addcycles000_nonce(const char *s, const char *sc)
+static void addcycles000_nonces(const char *s, const char *sc)
{
- if (using_simple_cycles)
+ if (using_simple_cycles) {
printf("%scount_cycles += %s * CYCLE_UNIT / 2;\n", s, sc);
+ count_ncycles++;
+ }
+}
+static void addcycles000_nonce(const char *s, int c)
+{
+ if (using_simple_cycles) {
+ printf("%scount_cycles += %d * CYCLE_UNIT / 2;\n", s, c);
+ count_ncycles++;
+ }
+}
+
+static void addcycles000_onlyce (int cycles)
+{
+ if (using_ce) {
+ printf ("\t%s (%d);\n", do_cycles, cycles);
+ }
}
static void addcycles000 (int cycles)
printf ("\t\tm68k_dreg (regs, movem_index1[dmask]) = v;\n");
printf ("\t\tsrca += %d;\n", size);
printf ("\t\tdmask = movem_next[dmask];\n");
- addcycles000_nonce("\t\t", "8");
+ addcycles000_nonce("\t\t", 8);
printf ("\t}\n");
printf ("\twhile (amask) {\n");
printf ("\t\tv = %s (srca) << 16;\n", srcw);
printf ("\t\tm68k_areg (regs, movem_index1[amask]) = v;\n");
printf ("\t\tsrca += %d;\n", size);
printf ("\t\tamask = movem_next[amask];\n");
- addcycles000_nonce("\t\t", "8");
+ addcycles000_nonce("\t\t", 8);
printf ("\t}\n");
} else {
printf ("\twhile (dmask) {\n");
printf ("\t\tm68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)%s (srca);\n", srcw);
printf ("\t\tsrca += %d;\n", size);
printf ("\t\tdmask = movem_next[dmask];\n");
- addcycles000_nonce("\t\t", "4");
+ addcycles000_nonce("\t\t", 4);
printf ("\t}\n");
printf ("\twhile (amask) {\n");
printf ("\t\tm68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)%s (srca);\n", srcw);
printf ("\t\tsrca += %d;\n", size);
printf ("\t\tamask = movem_next[amask];\n");
- addcycles000_nonce("\t\t", "4");
+ addcycles000_nonce("\t\t", 4);
printf ("\t}\n");
}
printf ("\t%s (srca);\n", srcw); // and final extra word fetch that goes nowhere..
printf ("\t\t%s (srca, m68k_areg (regs, movem_index2[amask]) >> 16);\n", dstw);
printf ("\t\t%s (srca + 2, m68k_areg (regs, movem_index2[amask]));\n", dstw);
printf ("\t\tamask = movem_next[amask];\n");
- addcycles000_nonce("\t\t", "8");
+ addcycles000_nonce("\t\t", 8);
printf ("\t}\n");
printf ("\twhile (dmask) {\n");
printf ("\t\tsrca -= %d;\n", size);
printf ("\t\t%s (srca, m68k_dreg (regs, movem_index2[dmask]) >> 16);\n", dstw);
printf ("\t\t%s (srca + 2, m68k_dreg (regs, movem_index2[dmask]));\n", dstw);
printf ("\t\tdmask = movem_next[dmask];\n");
- addcycles000_nonce("\t\t", "8");
+ addcycles000_nonce("\t\t", 8);
printf ("\t}\n");
printf ("\tm68k_areg (regs, dstreg) = srca;\n");
} else {
printf ("\t\t%s (srca + 2, m68k_dreg (regs, movem_index1[dmask]));\n", dstw);
printf ("\t\tsrca += %d;\n", size);
printf ("\t\tdmask = movem_next[dmask];\n");
- addcycles000_nonce("\t\t", "8");
+ addcycles000_nonce("\t\t", 8);
printf ("\t}\n");
printf ("\twhile (amask) {\n");
printf ("\t\t%s (srca, m68k_areg (regs, movem_index1[amask]) >> 16);\n", dstw);
printf ("\t\t%s (srca + 2, m68k_areg (regs, movem_index1[amask]));\n", dstw);
printf ("\t\tsrca += %d;\n", size);
printf ("\t\tamask = movem_next[amask];\n");
- addcycles000_nonce("\t\t", "8");
+ addcycles000_nonce("\t\t", 8);
printf ("\t}\n");
}
} else {
printf ("\t\tsrca -= %d;\n", size);
printf ("\t\t%s (srca, m68k_areg (regs, movem_index2[amask]));\n", dstw);
printf ("\tamask = movem_next[amask];\n");
- addcycles000_nonce("\t\t", "4");
+ addcycles000_nonce("\t\t", 4);
printf ("\t}\n");
printf ("\twhile (dmask) {\n");
printf ("\t\tsrca -= %d;\n", size);
printf ("\t\t%s (srca, m68k_dreg (regs, movem_index2[dmask]));\n", dstw);
printf ("\t\tdmask = movem_next[dmask];\n");
- addcycles000_nonce("\t\t", "4");
+ addcycles000_nonce("\t\t", 4);
printf ("\t}\n");
printf ("\tm68k_areg (regs, dstreg) = srca;\n");
} else {
printf ("\t\t%s (srca, m68k_dreg (regs, movem_index1[dmask]));\n", dstw);
printf ("\t\tsrca += %d;\n", size);
printf ("\t\tdmask = movem_next[dmask];\n");
- addcycles000_nonce("\t\t", "4");
+ addcycles000_nonce("\t\t", 4);
printf ("\t}\n");
printf ("\twhile (amask) {\n");
printf ("\t\t%s (srca, m68k_areg (regs, movem_index1[amask]));\n", dstw);
printf ("\t\tsrca += %d;\n", size);
printf ("\t\tamask = movem_next[amask];\n");
- addcycles000_nonce("\t\t", "4");
+ addcycles000_nonce("\t\t", 4);
printf ("\t}\n");
}
}
addcycles000_3 ("\t\t");
printf ("\t}\n");
}
- addcycles000_nonce("\t", "2 * ccnt");
+ addcycles000_nonces("\t", "2 * ccnt");
count_cycles += c;
count_ncycles++;
}
if (curi->mnemo != i_BTST) {
if (using_ce)
printf ("\tif (src > 15) %s (2);\n", do_cycles);
- addcycles000_nonce("\tif (src > 15) ", "2");
+ addcycles000_nonce("\tif (src > 15) ", 2);
count_ncycles++;
}
}
genamode (curi, curi->smode, "srcreg", sz_word, "src", 1, 0, 0);
if (curi->size == sz_byte) {
// MOVE TO CCR
- addcycles000 (6);
+ addcycles000 (4);
printf ("\tMakeSR ();\n\tregs.sr &= 0xFF00;\n\tregs.sr |= src & 0xFF;\n");
} else {
// MOVE TO SR
- addcycles000 (6);
+ addcycles000 (4);
printf ("\tregs.sr = src;\n");
}
makefromsr ();
printf ("\t\tgoto %s;\n", endlabelstr);
printf ("\t}\n");
sync_m68k_pc ();
+ addcycles000 (2);
irc2ir ();
fill_prefetch_2 ();
- printf ("\tgoto %s;\n", endlabelstr);
need_endlabel = 1;
+ goto bccl_not68020;
} else {
if (next_cpu_level < 1)
next_cpu_level = 1;
fill_prefetch_full_000 ();
}
insn_n_cycles = curi->size == sz_byte ? 8 : 12;
+bccl_not68020:
break;
case i_LEA:
if (curi->smode == Ad8r || curi->smode == PC8r)
add_head_cycs (6);
fill_prefetch_1 (2);
fill_prefetch_full_020 ();
- returncycles ("\t\t\t", 12);
+ returncycles ("\t\t\t", 10);
printf ("\t\t}\n");
add_head_cycs (10);
printf ("\t} else {\n");
- addcycles000 (2);
+ addcycles000_onlyce(2);
+ addcycles000_nonce("\t\t", 2);
printf ("\t}\n");
pop_ins_cnt();
setpc ("oldpc + %d", m68k_pc_offset);
if (using_ce)
printf ("\tint cycles = val ? 2 : 0;\n");
addcycles000_3 ("\t");
- addcycles000_nonce("\t", "val ? 2 : 0");
+ addcycles000_nonces("\t", "(val ? 2 : 0)");
}
genastore ("val", curi->smode, "srcreg", curi->size, "src");
break;
printf ("\t\tint cycles = (getDivu68kCycles((uae_u32)dst, (uae_u16)src)) - 4;\n");
addcycles000_3 ("\t\t");
}
- addcycles000_nonce("\t\t", "(getDivu68kCycles((uae_u32)dst, (uae_u16)src)) - 4");
+ addcycles000_nonces("\t\t", "(getDivu68kCycles((uae_u32)dst, (uae_u16)src)) - 4");
fill_prefetch_next ();
/* The N flag appears to be set each time there is an overflow.
* Weird. but 68020 only sets N when dst is negative.. */
printf ("\t\tint cycles = (getDivs68kCycles((uae_s32)dst, (uae_s16)src)) - 4;\n");
addcycles000_3 ("\t\t");
}
- addcycles000_nonce("\t\t", "(getDivs68kCycles((uae_s32)dst, (uae_s16)src)) - 4");
+ addcycles000_nonces("\t\t", "(getDivs68kCycles((uae_s32)dst, (uae_s16)src)) - 4");
fill_prefetch_next ();
printf ("\tif (dst == 0x80000000 && src == -1) {\n");
printf ("\t\tSET_VFLG (1);\n");
printf ("\t\tif (src & 1) cycles += 2;\n");
addcycles000_3 ("\t");
}
- addcycles000_nonce("\tfor(bits = 0; bits < 16 && src; bits++, src >>= 1)\n\t\tif (src & 1) ", "2");
+ addcycles000_nonce("\tfor(bits = 0; bits < 16 && src; bits++, src >>= 1)\n\t\tif (src & 1) ", 2);
genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
sync_m68k_pc ();
count_cycles += 38 - 4;
printf ("\t\tif ((usrc & 3) == 1 || (usrc & 3) == 2) cycles += 2;\n");
addcycles000_3 ("\t");
}
- addcycles000_nonce("\tusrc = ((uae_u32)src) << 1;\n\tfor(bits = 0; bits < 16 && usrc; bits++, usrc >>= 1)\n\t\tif ((usrc & 3) == 1 || (usrc & 3) == 2) ", "2");
+ addcycles000_nonce("\tusrc = ((uae_u32)src) << 1;\n\tfor(bits = 0; bits < 16 && usrc; bits++, usrc >>= 1)\n\t\tif ((usrc & 3) == 1 || (usrc & 3) == 2) ", 2);
genastore ("newv", curi->dmode, "dstreg", sz_long, "dst");
count_cycles += 38 - 4;
count_ncycles++;
genastore ("src", curi->smode, "srcreg", curi->size, "src");
printf ("\t} else {\n");
printf ("\t\t%s (4);\n", do_cycles);
- addcycles000_nonce("\t\t", "4");
+ addcycles000_nonce("\t\t", 4);
printf ("\t}\n");
}
break;
else
genamode (curi, curi->smode, "srcreg", curi->size, "extra", 0, 0, 0);
sync_m68k_pc ();
- printf ("\tmmu_op30 (pc, opcode, extra, extraa);\n");
+ if (using_ce020 || using_prefetch_020) {
+ printf ("\tif (mmu_op30 (pc, opcode, extra, extraa)) goto %s;\n", endlabelstr);
+ need_endlabel = 1;
+ } else {
+ printf ("\tmmu_op30 (pc, opcode, extra, extraa);\n");
+ }
break;
default:
term ();
uae_u32 REGPARAM3 get_disp_ea_020_mmu030 (uae_u32 base, int idx) REGPARAM;
void mmu030_page_fault(uaecptr addr, bool read, int flags, uae_u32 fc);
-void mmu_op30_pmove (uaecptr pc, uae_u32 opcode, uae_u16 next, uaecptr extra);
-void mmu_op30_ptest (uaecptr pc, uae_u32 opcode, uae_u16 next, uaecptr extra);
-void mmu_op30_pload (uaecptr pc, uae_u32 opcode, uae_u16 next, uaecptr extra);
-void mmu_op30_pflush (uaecptr pc, uae_u32 opcode, uae_u16 next, uaecptr extra);
+bool mmu_op30_pmove (uaecptr pc, uae_u32 opcode, uae_u16 next, uaecptr extra);
+bool mmu_op30_ptest (uaecptr pc, uae_u32 opcode, uae_u16 next, uaecptr extra);
+bool mmu_op30_pload (uaecptr pc, uae_u32 opcode, uae_u16 next, uaecptr extra);
+bool mmu_op30_pflush (uaecptr pc, uae_u32 opcode, uae_u16 next, uaecptr extra);
uae_u32 mmu_op30_helper_get_fc(uae_u16 next);
} TT_info;
TT_info mmu030_decode_tt(uae_u32 TT);
-void mmu030_decode_tc(uae_u32 TC);
-void mmu030_decode_rp(uae_u64 RP);
+bool mmu030_decode_tc(uae_u32 TC);
+bool mmu030_decode_rp(uae_u64 RP);
int mmu030_logical_is_in_atc(uaecptr addr, uae_u32 fc, bool write);
void mmu030_atc_handle_history_bit(int entry_num);
NUMSG_KS68EC020, NUMSG_KS68020, NUMSG_KS68030,
NUMSG_ROMNEED, NUMSG_EXPROMNEED, NUMSG_NOZLIB, NUMSG_STATEHD,
NUMSG_NOCAPS, NUMSG_OLDCAPS, NUMSG_KICKREP, NUMSG_KICKREPNO,
- NUMSG_KS68030PLUS, NUMSG_NO_PPC
+ NUMSG_KS68030PLUS, NUMSG_NO_PPC, NUMSG_UAEBOOTROM_PPC
} notify_user_msg;
extern bool is_keyboardreset(void);
extern void mmu_op (uae_u32, uae_u32);
-extern void mmu_op30 (uaecptr, uae_u32, uae_u16, uaecptr);
+extern bool mmu_op30 (uaecptr, uae_u32, uae_u16, uaecptr);
extern void fpuop_arithmetic(uae_u32, uae_u16);
extern void fpuop_dbcc(uae_u32, uae_u16);
if (p->cpu_frequency == 1000000)
p->cpu_frequency = 0;
- if (p->cpu_model >= 68030 && p->address_space_24) {
- error_log (_T("24-bit address space is not supported with 68030/040/060 configurations."));
+ if (p->cpu_model >= 68040 && p->address_space_24) {
+ error_log (_T("24-bit address space is not supported with 68040/060 configurations."));
p->address_space_24 = 0;
}
if (p->cpu_model < 68020 && p->fpu_model && (p->cpu_compatible || p->cpu_cycle_exact)) {
#ifndef NATMEM_OFFSET
-uae_u8 *mapped_malloc (size_t s, const TCHAR *file)
+bool mapped_malloc (addrbank *ab)
{
- return xmalloc (uae_u8, s);
+ ab->startmask = ab->start;
+ ab->baseaddr = xcalloc (uae_u8, ab->allocated + 4);
+ return ab->baseaddr != NULL;
}
-void mapped_free (uae_u8 *p)
+void mapped_free (addrbank *ab)
{
- xfree (p);
+ xfree(ab->baseaddr);
+ ab->baseaddr = NULL;
}
#else
shm_start = y;
}
-#define MAPPED_MALLOC_DEBUG 1
+#define MAPPED_MALLOC_DEBUG 0
bool mapped_malloc (addrbank *ab)
{
regs.address_space_mask = 0xffffffff;
if (currprefs.cpu_compatible) {
- if (currprefs.address_space_24 && currprefs.cpu_model >= 68030)
+ if (currprefs.address_space_24 && currprefs.cpu_model >= 68040)
currprefs.address_space_24 = false;
}
m68k_interrupt_delay = false;
regs.memory_waitstate_cycles = 0;
if (currprefs.m68k_speed < 0 || cycles_mult == 0)
return cycles + mc;
- cpu_cycles *= cycles_mult;
- cpu_cycles /= CYCLES_DIV;
- return cpu_cycles + mc;
+ cycles *= cycles_mult;
+ cycles /= CYCLES_DIV;
+ return cycles + mc;
}
void REGPARAM2 MakeSR (void)
#ifdef CPUEMU_0
-static void mmu_op30fake_pmove (uaecptr pc, uae_u32 opcode, uae_u16 next, uaecptr extra)
+static bool mmu_op30fake_pmove (uaecptr pc, uae_u32 opcode, uae_u16 next, uaecptr extra)
{
int mode = (opcode >> 3) & 7;
+ int rreg = opcode & 7;
int preg = (next >> 10) & 31;
int rw = (next >> 9) & 1;
int fd = (next >> 8) & 1;
uae_u32 otc = fake_tc_030;
int siz;
- // Dn, An, (An)+, -(An), abs and indirect
- if (mode == 0 || mode == 1 || mode == 3 || mode == 4 || mode >= 6) {
+ // Dn, An, (An)+, -(An), immediate and PC-relative not allowed
+ if (mode == 0 || mode == 1 || mode == 3 || mode == 4 || mode == 6 || (mode == 7 && rreg > 1)) {
op_illg (opcode);
- return;
+ return true;
}
switch (preg)
if (!reg) {
op_illg (opcode);
- return;
+ return true;
}
#if MMUOP_DEBUG > 0
{
a3000_fakekick (fake_tc_030 & 0x80000000);
}
}
+ return false;
}
-static void mmu_op30fake_ptest (uaecptr pc, uae_u32 opcode, uae_u16 next, uaecptr extra)
+static bool mmu_op30fake_ptest (uaecptr pc, uae_u32 opcode, uae_u16 next, uaecptr extra)
{
#if MMUOP_DEBUG > 0
TCHAR tmp[10];
((next >> 9) & 1) ? 'W' : 'R', (next & 15), extra, (next >> 10) & 7, tmp, pc);
#endif
fake_mmusr_030 = 0;
+ return false;
}
-static void mmu_op30fake_pflush (uaecptr pc, uae_u32 opcode, uae_u16 next, uaecptr extra)
+static bool mmu_op30fake_pflush (uaecptr pc, uae_u32 opcode, uae_u16 next, uaecptr extra)
{
int mode = (opcode >> 3) & 7;
- int reg = opcode & 7;
+ int rreg = opcode & 7;
int flushmode = (next >> 10) & 7;
int fc = next & 31;
int mask = (next >> 5) & 3;
switch (flushmode)
{
case 6:
- // Dn, An, (An)+, -(An), abs and indirect
- if (mode == 0 || mode == 1 || mode == 3 || mode == 4 || mode >= 6) {
+ // Dn, An, (An)+, -(An), immediate and PC-relative not allowed
+ if (mode == 0 || mode == 1 || mode == 3 || mode == 4 || mode == 6 || (mode == 7 && rreg > 1)) {
op_illg (opcode);
- return;
+ return true;
}
_stprintf (fname, _T("FC=%x MASK=%x EA=%08x"), fc, mask, 0);
break;
break;
default:
op_illg (opcode);
- return;
+ return true;
}
#if MMUOP_DEBUG > 0
write_log (_T("PFLUSH %s PC=%08X\n"), fname, pc);
#endif
+ return false;
}
// 68030 (68851) MMU instructions only
-void mmu_op30 (uaecptr pc, uae_u32 opcode, uae_u16 extra, uaecptr extraa)
+bool mmu_op30 (uaecptr pc, uae_u32 opcode, uae_u16 extra, uaecptr extraa)
{
if (currprefs.mmu_model) {
- if (extra & 0x8000)
- mmu_op30_ptest (pc, opcode, extra, extraa);
- else if ((extra&0xE000)==0x2000 && (extra & 0x1C00))
- mmu_op30_pflush (pc, opcode, extra, extraa);
- else if ((extra&0xE000)==0x2000 && !(extra & 0x1C00))
- mmu_op30_pload (pc, opcode, extra, extraa);
- else
- mmu_op30_pmove (pc, opcode, extra, extraa);
- return;
+ if (extra & 0x8000) {
+ return mmu_op30_ptest (pc, opcode, extra, extraa);
+ } else if ((extra&0xE000)==0x2000 && (extra & 0x1C00)) {
+ return mmu_op30_pflush (pc, opcode, extra, extraa);
+ } else if ((extra&0xE000)==0x2000 && !(extra & 0x1C00)) {
+ return mmu_op30_pload (pc, opcode, extra, extraa);
+ } else {
+ return mmu_op30_pmove (pc, opcode, extra, extraa);
+ }
+ return false;
}
int type = extra >> 13;
case 0:
case 2:
case 3:
- mmu_op30fake_pmove (pc, opcode, extra, extraa);
+ return mmu_op30fake_pmove (pc, opcode, extra, extraa);
break;
case 1:
- mmu_op30fake_pflush (pc, opcode, extra, extraa);
+ return mmu_op30fake_pflush (pc, opcode, extra, extraa);
break;
case 4:
- mmu_op30fake_ptest (pc, opcode, extra, extraa);
+ return mmu_op30fake_ptest (pc, opcode, extra, extraa);
break;
default:
op_illg (opcode);
+ return true;
break;
}
}
}
#define PPC_HALTLOOP_SCANLINES 25
-// ppc_cpu_idle
+// ppc_cpu_idle
// 0 = busy
// 1-9 = wait, levels
// 10 = max wait
int rpt_scanline = read_processor_time();
int rpt_end = rpt_scanline + vsynctimeline;
+ // See expansion handling.
+ // Dialog must be opened from main thread.
+ if (regs.halted == -2) {
+ regs.halted = -1;
+ notify_user (NUMSG_UAEBOOTROM_PPC);
+ }
+
if (currprefs.ppc_cpu_idle) {
int maxlines = 100 - (currprefs.ppc_cpu_idle - 1) * 10;
if (isfocus () && !istest) {
if (did->buttons >= 3 && (rm->usButtonFlags & RI_MOUSE_MIDDLE_BUTTON_DOWN)) {
if (currprefs.win32_middle_mouse) {
- if (isfullscreen () != 0 && currprefs.win32_minimize_inactive)
+ if ((isfullscreen() < 0 && currprefs.win32_minimize_inactive) || isfullscreen() > 0)
minimizewindow ();
if (mouseactive)
setmouseactive (0);
}
}
if (!istest && isfocus () && currprefs.win32_middle_mouse && dimofs == DIMOFS_BUTTON2 && state) {
- if (isfullscreen () != 0 && currprefs.win32_minimize_inactive)
+ if ((isfullscreen() < 0 && currprefs.win32_minimize_inactive) || isfullscreen() > 0)
minimizewindow ();
if (mouseactive)
setmouseactive (0);
#define IDS_ALWAYS_ON 402
#define IDS_DISPLAY_ATTRIBUTES 403
#define IDS_NUMSG_NO_PPC 404
+#define IDS_NUMSG_UAEBOOTROM_PCC 405
#define IDS_QS_MODELS 1000
#define IDS_QS_MODEL_A500 1001
#define IDS_QS_MODEL_A500P 1002
IDS_FILTER_3D_EXTRA "Point/Bilinear\nScanline opacity\nScanline level\n"
IDS_ALWAYS_ON "Always on"
IDS_DISPLAY_ATTRIBUTES "Brightness\nContrast\nGamma"
- IDS_NUMSG_NO_PPC "PPC CPU was started but PPC CPU emulation core plugin was not found."
+ IDS_NUMSG_NO_PPC "PPC CPU was started but PPC CPU emulation core plugin was not found. Download available from http://www.winuae.net/"
+ IDS_NUMSG_UAEBOOTROM_PCC
+ "PPC native OS booted with UAE boot ROM active. UAE expansions are not hardware emulated and are not PPC compatible. (UAE HD controller, uaescsi.device, uaeserial, bsdsocket and so on..)"
END
#endif // English resources
#define LANG_DLL_FULL_VERSION_MATCH 1
#if WINUAEPUBLICBETA
-#define WINUAEBETA _T("26")
+#define WINUAEBETA _T("27")
#else
#define WINUAEBETA _T("")
#endif
-#define WINUAEDATE MAKEBD(2014, 12, 4)
+#define WINUAEDATE MAKEBD(2014, 12, 8)
//#define WINUAEEXTRA _T("AmiKit Preview")
//#define WINUAEEXTRA _T("Amiga Forever Edition")
BOOL cpu_based_enable = FALSE;
ew (hDlg, IDC_SPEED, !workprefs.cpu_cycle_exact);
- ew (hDlg, IDC_COMPATIBLE24, workprefs.cpu_model <= 68020);
+ ew (hDlg, IDC_COMPATIBLE24, workprefs.cpu_model <= 68030);
//ew (hDlg, IDC_CS_HOST, !workprefs.cpu_cycle_exact);
//ew (hDlg, IDC_CS_68000, !workprefs.cpu_cycle_exact);
//ew (hDlg, IDC_CS_ADJUSTABLE, !workprefs.cpu_cycle_exact);
workprefs.fpu_model = newfpu == 0 ? 0 : (newfpu == 2 ? 68882 : 68881);
break;
case 68030:
- workprefs.address_space_24 = 0;
+ if (newcpu != oldcpu)
+ workprefs.address_space_24 = 0;
workprefs.fpu_model = newfpu == 0 ? 0 : (newfpu == 2 ? 68882 : 68881);
workprefs.mmu_model = ischecked (hDlg, IDC_MMUENABLE) ? 68030 : 0;
break;
*flags |= MB_SETFOREGROUND;
return 0;
}
- *hwnd = hAmigaWnd;
+ *hwnd = hMainWnd;
if (isfullscreen () <= 0)
return 0;
+ *hwnd = hAmigaWnd;
flipgui (true);
*flags |= MB_SETFOREGROUND;
*flags |= MB_TOPMOST;
int flipflop = 0;
int fullscreen = 0;
int focuso = isfocus ();
- DWORD flags = MB_OK | MB_TASKMODAL;
+ DWORD flags = MB_OK;
HWND hwnd;
va_start (parms, format);
if (flipflop)
ShowWindow (hAmigaWnd, SW_MINIMIZE);
}
+ if (hwnd == NULL)
+ flags |= MB_TASKMODAL;
write_log (msg);
if (msg[_tcslen (msg) - 1] != '\n')
NUMSG_KICKREPNO, IDS_NUMSG_KICKREPNO,
NUMSG_KS68030PLUS, IDS_NUMSG_KS68030PLUS,
NUMSG_NO_PPC, IDS_NUMSG_NO_PPC,
+ NUMSG_UAEBOOTROM_PPC, IDS_NUMSG_UAEBOOTROM_PCC,
-1
};
- restore only single input target to default.
+Beta 27: (RC2)
+
+- Added compatibility warning message if PPC CPU (and m68k is stopped) configures UAE filesystem
+ autoconfig board ("UAE" controller that is needed by uaehf.device bsdsocket, uaescsi and so on)
+- Added download url to no ppc plugin detected message.
+- Minimize when inactive option should be ignored if mode is fullscreen. Only uncapturing mouse in
+ real fullscreen mode makes no sense. (b24)
+- 68000 MOVE to CCR/SR idle cycle count is 4 cycles, not 6.
+- 68000 prefetch mode ("more compatible") DBcc cycle counting fixed.
+- 68030 prefetch/"cycle-exact" mode MMU instruction exception prefetch fix. (Same as 280b1 for FPU)
+- 68030 "fake" MMU (MMU emulation not enabled = MMU instructions do nothing), absolute address
+ (xxx.w and xxx.l) addressing modes were marked incorrectly as invalid.
+- Strange immediate TST variant (TST.x #z) is valid instruction if 68020+.
+- Allow 24-bit address space with 68030 CPU. (Not going to touch other CPUs just yet)
+
+Beta 26: (RC1, Official release date deadline is mid december)
+
+- Bumped version to 3.0.
+- Directory filesystem statefile support didn't save open file's full path correctly if path was deeper than
+ 2 levels from root. (Bug since directory statefile support was implemented)
+- Z3 mapping mode = automatic: select always real mode if JIT is disabled.
+- Added picassoiv_rom_file config file entry, if you want to use different versions or custom path.
+- Off by one error in internal buffer calculation, display was shifted by 1 vertical pixel, hiding
+ first line if window size was small enough but still big enough to fit all vertical lines.
+- 68000 JMP (d8,An/PC,Xn) didn't include extra 4 cycle idle time. (Documentation says 3 read cycles which
+ is incorrect, correct sequence is 4 idle cycles + 2 idle cycles + prefetch + prefetch)
+
Beta 25:
- Added 1M/0.5M+0.5M chip/slow ram option checkbox to Advanced Chipset (for example in rev6 A500 it is JP2
- Map Chip RAM mirror at 0x01000000 in A2620/A2630 config, to prevent A26x0 built-in monitor program detecting
huge ram expansion at 0x01000000.
- uaenet.device + slirp combination was broken (probably has always been).
-- uaegfx modeid space increased, reduces modeid conflicts if host os has huge amount of modes.
+- uaegfx modeid space increased, reduces modeid conflicts if host os has huge amount of resolutions (>~80).
- Debugger does not anymore exit stopped CPU state (STOP instruction) after exiting debugger.
- "SCSI (Auto)" priorities changed: mainboard built-in first, then accelerator board, expansions last. (Expansions
was first previously)
- 0 0 2
0100 1010 zzss sSSS:000:-NZ00:-----:10: TST.z s[!Areg,Dreg,PC16,PC8r,Immd]
- 0 0 2 fea
-0100 1010 zzss sSSS:200:-NZ00:-----:10: TST.z s[Areg,PC16,PC8r]
+0100 1010 zzss sSSS:200:-NZ00:-----:10: TST.z s[Areg,PC16,PC8r,Immd]
- 0 0 2 fea
0100 1010 11dd dDDD:000:?????:?????:30: TAS.B d[Dreg]
- 0 0 2