Removed FIXED registers from the alpha register class. Updated some

.cvsignore files.

diff --git a/.cvsignore b/.cvsignore
index 9ba7e9bd2ff803174abe9402332823117150dcaa..2980f623f54b9dfa350659716b0b3619f0f9779b 100644 (file)
--- a/.cvsignore
+++ b/.cvsignore
@@ -14,3 +14,6 @@ stamp-h.in
 libtool
 ltconfig
 ltmain.sh
+autom4te.cache
+stamp-h1
+ylwrap

diff --git a/ChangeLog b/ChangeLog
index a0d8503383f14aa60351a4058f6dd25a0aa88649..2fc546fe12ce05a4a7f13f23bf284058cdcabeca 100644 (file)
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,11 @@
+2007-01-04  Thomas Cort  <linuxgeek@gmail.com>
+
+       * jit/jit-rules-alpha.c: register class should not include FIXED
+       registers.
+
+       * .cvsignore, tools/.cvsignore, tutorial/.cvsignore: updated
+       the .cvsignore files to ignore some generated files.
+
 2007-01-03  Thomas Cort  <linuxgeek@gmail.com>
 
        * jit/jit-rules-alpha.c: initialize alpha register classes.

diff --git a/jit/jit-rules-alpha.c b/jit/jit-rules-alpha.c
index c21096e922290bfce92f87e795a5413c00c1b2ff..f2189ad6a3ca9f92f7034b5dab19d4378344ce96 100644 (file)
--- a/jit/jit-rules-alpha.c
+++ b/jit/jit-rules-alpha.c
@@ -107,24 +107,16 @@ static _jit_regclass_t *alpha_freg;
  * some ARM cores have floating-point registers.
  */
 void _jit_init_backend(void) {
-       alpha_reg = _jit_regclass_create("reg", JIT_REG_WORD | JIT_REG_LONG, 32,
-                ALPHA_R0,  ALPHA_R1,  ALPHA_R2,  ALPHA_R3,  ALPHA_R4,
-                ALPHA_R5,  ALPHA_R6,  ALPHA_R7,  ALPHA_R8,  ALPHA_R9, 
-               ALPHA_R10, ALPHA_R11, ALPHA_R12, ALPHA_R13, ALPHA_R14,
-               ALPHA_R15, ALPHA_R16, ALPHA_R17, ALPHA_R18, ALPHA_R19,
-               ALPHA_R20, ALPHA_R21, ALPHA_R22, ALPHA_R23, ALPHA_R24,
-               ALPHA_R25, ALPHA_R26, ALPHA_R27, ALPHA_R28, ALPHA_R29,
-               ALPHA_R30, ALPHA_R31
+       alpha_reg = _jit_regclass_create("reg", JIT_REG_WORD | JIT_REG_LONG, 18,
+               ALPHA_T0, ALPHA_T1, ALPHA_T2, ALPHA_T3,  ALPHA_T4,  ALPHA_T5,
+               ALPHA_T6, ALPHA_T7, ALPHA_T8, ALPHA_T9, ALPHA_T10, ALPHA_T11,
+               ALPHA_S0, ALPHA_S1, ALPHA_S2, ALPHA_S3,  ALPHA_S4,  ALPHA_S5
        );
 
-       alpha_freg = _jit_regclass_create("freg", JIT_REG_FLOAT32 | JIT_REG_FLOAT64 | JIT_REG_NFLOAT, 32,
-                ALPHA_F0,  ALPHA_F1,  ALPHA_F2,  ALPHA_F3,  ALPHA_F4,
-                ALPHA_F5,  ALPHA_F6,  ALPHA_F7,  ALPHA_F8,  ALPHA_F9, 
-               ALPHA_F10, ALPHA_F11, ALPHA_F12, ALPHA_F13, ALPHA_F14,
-               ALPHA_F15, ALPHA_F16, ALPHA_F17, ALPHA_F18, ALPHA_F19,
-               ALPHA_F20, ALPHA_F21, ALPHA_F22, ALPHA_F23, ALPHA_F24,
-               ALPHA_F25, ALPHA_F26, ALPHA_F27, ALPHA_F28, ALPHA_F29,
-               ALPHA_F30, ALPHA_F31
+       alpha_freg = _jit_regclass_create("freg", JIT_REG_FLOAT32 | JIT_REG_FLOAT64 | JIT_REG_NFLOAT, 8,
+               ALPHA_FS0, ALPHA_FS1, ALPHA_FS2, ALPHA_FS3, ALPHA_FS4,
+               ALPHA_FS5, ALPHA_FS6, ALPHA_FS7, ALPHA_FT0, ALPHA_FT1,
+               ALPHA_FT2, ALPHA_FT3, ALPHA_FT4, ALPHA_FT5
        );
 }
 

diff --git a/tools/.cvsignore b/tools/.cvsignore
index 95a54f57fc11562619342bf9bf4d90a6d4dfa255..3ec2e02252b5131151aabf5e27f54c9ab5eab7c9 100644 (file)
--- a/tools/.cvsignore
+++ b/tools/.cvsignore
@@ -6,8 +6,13 @@ gen-apply
 gen-apply.exe
 gen-sel
 gen-sel.exe
+gen-rules
+gen-rules.exe
 *.lo
 *.la
 gen-sel-parser.c
 gen-sel-parser.h
 gen-sel-scanner.c
+gen-rules-parser.c
+gen-rules-parser.h
+gen-rules-scanner.c

diff --git a/tutorial/.cvsignore b/tutorial/.cvsignore
index 0bc6365f85be338ff403bcbec944af4d1317ee07..805548d61d37a0f00e1613492f72e17d70c8e98e 100644 (file)
--- a/tutorial/.cvsignore
+++ b/tutorial/.cvsignore
@@ -7,5 +7,6 @@ t1
 t2
 t3
 t4
+t5
 *.lo
 *.la