static void do_trace(void)
{
- if (regs.t0 && currprefs.cpu_model >= 68020) {
+ regs.trace_pc = regs.pc;
+ if (regs.t0 && !regs.t1 && currprefs.cpu_model >= 68020) {
// this is obsolete
return;
}
SR-modifying instructions (including STOP). */
SPCFLAG_TRACE = 0;
}
- // Stop SR-modification does not generate T0
+ // STOP SR-modification does not generate T0
// If this SR modification set Tx bit, no trace until next instruction.
if ((oldt0 && t0trace && currprefs.cpu_model >= 68020) || oldt1) {
// Always trace if Tx bits were already set, even if this SR modification cleared them.
{
SPCFLAG_TRACE = 0;
SPCFLAG_DOTRACE = 0;
- if (regs.t1 && !regs.t0) {
+ if (regs.t1) {
/* trace stays pending if exception is div by zero, chk,
* trapv or trap #x
*/
void check_t0_trace(void)
{
- if (regs.t0 && currprefs.cpu_model >= 68020) {
+ if (regs.t0 && !regs.t1 && currprefs.cpu_model >= 68020) {
SPCFLAG_TRACE = 0;
SPCFLAG_DOTRACE = 1;
}
test_exception_addr = m68k_getpci();
test_exception_opcode = -1;
- bool t0 = currprefs.cpu_model >= 68020 && regs.t0;
+ bool t0 = currprefs.cpu_model >= 68020 && regs.t0 && !regs.t1;
// check T0 trace
if (t0) {
activate_trace();
}
}
- if (dp->mnemo == i_TAS && low_memory_accessed) {
+ // Amiga Chip ram does not support TAS or MOVE16
+ if ((dp->mnemo == i_TAS || dp->mnemo == i_MOVE16) && low_memory_accessed) {
test_exception = -1;
break;
}
#endif
- int lvl = cpu_lvl;
- if (lvl == 3) {
- lvl = 2;
- } else if (lvl == 5) {
+ if (cpu_lvl == 5) {
#ifdef M68K
// Overwrite MOVEC to/from MSP
// with NOPs if 68060
return 0;
}
- sprintf(path + strlen(path), "%lu/", 68000 + (lvl == 5 ? 6 : lvl) * 10);
-
strcpy(opcode, argv[1]);
check_undefined_sr = 1;
ccr_mask = ~getparamval(next);
i++;
}
+ } else if (!_stricmp(s, "68000")) {
+ cpu_lvl = 0;
+ } else if (!_stricmp(s, "68010")) {
+ cpu_lvl = 1;
+ } else if (!_stricmp(s, "68020")) {
+ cpu_lvl = 2;
+ } else if (!_stricmp(s, "68030")) {
+ cpu_lvl = 3;
+ } else if (!_stricmp(s, "68040")) {
+ cpu_lvl = 4;
+ } else if (!_stricmp(s, "68060")) {
+ cpu_lvl = 5;
}
}
+ sprintf(path + strlen(path), "%lu/", 68000 + (cpu_lvl == 5 ? 6 : cpu_lvl) * 10);
+
low_memory_size = -1;
low_memory_temp = load_file(path, "lmem.dat", NULL, &low_memory_size, 0);
high_memory_size = -1;
printf ("\tMakeSR ();\n\tregs.sr &= 0xFF00;\n\tregs.sr |= src & 0xFF;\n");
} else {
// MOVE TO SR
+ printf("\tcheck_t0_trace();\n");
addcycles000 (4);
printf ("\tregs.sr = src;\n");
}
uae_u16 opcode;
uae_u32 instruction_pc;
uae_u32 instruction_pc_user_exception;
+ uae_u32 trace_pc;
uae_u16 irc, ir, db;
volatile uae_atomic spcflags;
static void exception_check_trace (int nr)
{
unset_special (SPCFLAG_TRACE | SPCFLAG_DOTRACE);
- if (regs.t1 && !regs.t0) {
+ if (regs.t1) {
/* trace stays pending if exception is div by zero, chk,
* trapv or trap #x
*/
void REGPARAM2 Exception_cpu(int nr)
{
- bool t0 = currprefs.cpu_model >= 68020 && regs.t0;
+ bool t0 = currprefs.cpu_model >= 68020 && regs.t0 && !regs.t1;
ExceptionX (nr, -1);
// check T0 trace
if (t0) {
static void do_trace (void)
{
- if (regs.t0 && currprefs.cpu_model >= 68020) {
+ // need to store PC because of branch instructions
+ regs.trace_pc = regs.pc;
+ if (regs.t0 && !regs.t1 && currprefs.cpu_model >= 68020) {
// this is obsolete
return;
}
void check_t0_trace(void)
{
- if (regs.t0 && currprefs.cpu_model >= 68020) {
+ if (regs.t0 && !regs.t1 && currprefs.cpu_model >= 68020) {
unset_special (SPCFLAG_TRACE);
set_special (SPCFLAG_DOTRACE);
}
void Exception_build_stack_frame_common(uae_u32 oldpc, uae_u32 currpc, uae_u32 ssw, int nr)
{
if (nr == 5 || nr == 6 || nr == 7 || nr == 9) {
+ if (nr == 9)
+ oldpc = regs.trace_pc;
if (currprefs.cpu_model <= 68010)
Exception_build_stack_frame(oldpc, currpc, regs.mmu_ssw, nr, 0x0);
else