#define ROM_VECTOR 0x2000
#define ROM_OFFSET 0x2000
-#define ROM_SIZE 16384
-#define ROM_MASK (ROM_SIZE - 1)
/* SuperDMAC CNTR bits. */
-#define SCNTR_TCEN (1<<5)
-#define SCNTR_PREST (1<<4)
-#define SCNTR_PDMD (1<<3)
-#define SCNTR_INTEN (1<<2)
-#define SCNTR_DDIR (1<<1)
-#define SCNTR_IO_DX (1<<0)
+#define SCNTR_TCEN (1<<5)
+#define SCNTR_PREST (1<<4)
+#define SCNTR_PDMD (1<<3)
+#define SCNTR_INTEN (1<<2)
+#define SCNTR_DDIR (1<<1)
+#define SCNTR_IO_DX (1<<0)
/* DMAC CNTR bits. */
-#define CNTR_TCEN (1<<7)
-#define CNTR_PREST (1<<6)
-#define CNTR_PDMD (1<<5)
-#define CNTR_INTEN (1<<4)
-#define CNTR_DDIR (1<<3)
+#define CNTR_TCEN (1<<7)
+#define CNTR_PREST (1<<6)
+#define CNTR_PDMD (1<<5)
+#define CNTR_INTEN (1<<4)
+#define CNTR_DDIR (1<<3)
/* ISTR bits. */
-#define ISTR_INTX (1<<8)
-#define ISTR_INT_F (1<<7)
-#define ISTR_INTS (1<<6)
-#define ISTR_E_INT (1<<5)
-#define ISTR_INT_P (1<<4)
-#define ISTR_UE_INT (1<<3)
-#define ISTR_OE_INT (1<<2)
-#define ISTR_FF_FLG (1<<1)
-#define ISTR_FE_FLG (1<<0)
+#define ISTR_INTX (1<<8) /* XT/AT Interrupt pending */
+#define ISTR_INT_F (1<<7) /* Interrupt Follow */
+#define ISTR_INTS (1<<6) /* SCSI Peripheral Interrupt */
+#define ISTR_E_INT (1<<5) /* End-Of-Process Interrupt */
+#define ISTR_INT_P (1<<4) /* Interrupt Pending */
+#define ISTR_UE_INT (1<<3) /* Under-Run FIFO Error Interrupt */
+#define ISTR_OE_INT (1<<2) /* Over-Run FIFO Error Interrupt */
+#define ISTR_FF_FLG (1<<1) /* FIFO-Full Flag */
+#define ISTR_FE_FLG (1<<0) /* FIFO-Empty Flag */
/* wd register names */
#define WD_OWN_ID 0x00
#define PHS_MESS_OUT 0x06
#define PHS_MESS_IN 0x07
-
static int configured;
static uae_u8 dmacmemory[100];
static uae_u8 *rom;
+static int rombankswitcher, rombank;
+static int rom_size, rom_mask;
static uae_u32 dmac_istr, dmac_cntr;
static uae_u32 dmac_dawr;
static int superdmac;
static int scsiirqdelay;
+static int wd33c93a = 1;
struct scsi_data *scsis[8];
}
}
+static void doscsiirq(void)
+{
+ uae_int_requested |= 2;
+#if A2091_DEBUG > 2 || A3000_DEBUG > 2
+ write_log("Interrupt\n");
+#endif
+}
+
static void INT2(int quick)
{
int irq = 0;
dmac_istr |= ISTR_INTS;
if (isirq()) {
if (quick)
- uae_int_requested |= 2;
+ doscsiirq();
else
scsiirqdelay = 2;
}
{
if (scsiirqdelay == 1) {
scsiirqdelay = 0;
- uae_int_requested |= 2;
-#if A2091_DEBUG > 2 || A3000_DEBUG > 2
- write_log("Interrupt\n");
-#endif
+ doscsiirq();
return;
}
if (scsiirqdelay > 1)
{
wdregs[WD_SCSI_STATUS] = status;
auxstatus |= 0x80;
+#if WD33C93_DEBUG > 0
+ write_log("%s STATUS=%02X\n", WD33C93, status);
+#endif
if (!currprefs.cs_a2091 && currprefs.cs_mbdmac != 1)
return;
INT2(quick);
#if WD33C93_DEBUG > 0
write_log("* %s select and transfer, phase=%02X\n", WD33C93, phase);
#endif
+ SCSIID->buffer[0] = 0;
if (phase >= 0x46) {
phase = 0x50;
wdregs[WD_TARGET_LUN] = SCSIID->status;
+ SCSIID->buffer[0] = SCSIID->status;
}
wdregs[WD_COMMAND_PHASE] = phase;
wd_phase = CSR_XFER_DONE | PHS_MESS_IN;
- SCSIID->buffer[0] = 0;
set_status(wd_phase, 1);
}
if (currprefs.cs_cdtvscsi)
cdtv_getdmadata(&dmac_acr);
if (SCSIID->direction == 0) {
- write_log("%s DMA but no data!?\n");
+ write_log("%s DMA but no data!?\n", WD33C93);
} else if (SCSIID->direction < 0) {
for (;;) {
uae_u8 v;
static void wd_do_transfer_out(void)
{
#if WD33C93_DEBUG > 0
- write_log("%s SCSI O %d/%d %s\n", WD33C93, wd_dataoffset, wd_tc, scsitostring());
+ write_log("%s SCSI O [%02X] %d/%d %s\n", WD33C93, wdregs[WD_COMMAND_PHASE], wd_dataoffset, wd_tc, scsitostring());
#endif
if (wdregs[WD_COMMAND_PHASE] == 0x11) {
wdregs[WD_COMMAND_PHASE] = 0x20;
static void wd_do_transfer_in(void)
{
#if WD33C93_DEBUG > 0
- write_log("%s SCSI I %d/%d %s\n", WD33C93, wd_dataoffset, wd_tc, scsitostring());
+ write_log("%s SCSI I [%02X] %d/%d %s\n", WD33C93, wdregs[WD_COMMAND_PHASE], wd_dataoffset, wd_tc, scsitostring());
#endif
wd_dataoffset = 0;
- if (wdregs[WD_COMMAND_PHASE] == 0x3f) {
+ if (wdregs[WD_COMMAND_PHASE] >= 0x36 && wdregs[WD_COMMAND_PHASE] < 0x47) {
wdregs[WD_COMMAND_PHASE] = 0x47;
wd_phase = CSR_XFER_DONE | PHS_STATUS;
} else if (wdregs[WD_COMMAND_PHASE] == 0x47) {
SCSIID->direction = 0;
}
+
+static void wd_cmd_sel_xfer_atn(void)
+{
+ int i, tmp_tc;
+
+ tmp_tc = wdregs[WD_TRANSFER_COUNT_LSB] | (wdregs[WD_TRANSFER_COUNT] << 8) | (wdregs[WD_TRANSFER_COUNT_MSB] << 16);
+#if WD33C93_DEBUG > 0
+ write_log("* %s select and transfer with atn, PHASE=%02X TC=%d\n", WD33C93, wdregs[WD_COMMAND_PHASE], tmp_tc);
+#endif
+ if (wdregs[WD_COMMAND] & 0x80)
+ wd_tc = 1;
+ SCSIID->buffer[0] = 0;
+ if (!SCSIID) {
+ set_status(CSR_TIMEOUT, 0);
+ return;
+ }
+ SCSIID->direction = 0;
+ if (wdregs[WD_COMMAND_PHASE] <= 0x30) {
+ wd_tc = 6;
+ wd_dataoffset = 0;
+ scsi_start_transfer(SCSIID, 6);
+ for (i = 0; i < wd_tc; i++) {
+ uae_u8 b = wdregs[3 + i];
+ wd_data[i] = b;
+ scsi_send_data(SCSIID, b);
+ wd_dataoffset++;
+ }
+ // command
+ SCSIID->direction = (wdregs[WD_SOURCE_ID] & 0x20) ? 1 : -1;
+ wdregs[WD_COMMAND_PHASE] = 0x30;
+ wd_do_transfer_out();
+ wdregs[WD_COMMAND_PHASE] = 0x36;
+ }
+ if (wdregs[WD_COMMAND_PHASE] <= 0x41) {
+ wd_tc = tmp_tc;
+ wd_dataoffset = 0;
+ wdregs[WD_COMMAND_PHASE] = 0x45;
+ if (wd_tc == 0) {
+ if (SCSIID->direction != 0 && SCSIID->status == 0) {
+ wd_phase = CSR_UNEXP;
+ if (SCSIID->direction < 0)
+ wd_phase |= PHS_DATA_IN;
+ else
+ wd_phase |= PHS_DATA_OUT;
+ set_status(wd_phase, 1);
+ return;
+ }
+ }
+ if ((wdregs[WD_CONTROL] >> 5) == 4) {
+ if (wd_phase == (CSR_XFER_DONE | PHS_DATA_IN))
+ do_dma();
+ else if(wd_phase == (CSR_XFER_DONE | PHS_DATA_OUT))
+ do_dma();
+ }
+
+ }
+ wdregs[WD_COMMAND_PHASE] = 0x60;
+ wdregs[WD_TARGET_LUN] = SCSIID->status;
+ SCSIID->buffer[0] = SCSIID->status;
+ wd_phase = CSR_SEL_XFER_DONE;
+ set_status(wd_phase, 0);
+}
+
+
static void wd_cmd_trans_info(void)
{
if (wdregs[WD_COMMAND_PHASE] == 0x47)
wd_tc = 1;
wd_dataoffset = 0;
#if WD33C93_DEBUG > 0
- write_log("* %s transfer info phase=%02x len=%d dma=%d\n", WD33C93, wdregs[WD_COMMAND_PHASE], wd_tc, wdregs[WD_CONTROL] >> 6);
+ write_log("* %s transfer info phase=%02x len=%d dma=%d\n", WD33C93, wdregs[WD_COMMAND_PHASE], wd_tc, wdregs[WD_CONTROL] >> 5);
#endif
scsi_start_transfer(SCSIID, wd_tc);
- if ((wdregs[WD_CONTROL] >> 6) == 2) {
+ if (wdregs[WD_COMMAND_PHASE] >= 0x36 && wdregs[WD_COMMAND_PHASE] <= 0x3f)
+ wdregs[WD_COMMAND_PHASE] = 0x45;
+ if ((wdregs[WD_CONTROL] >> 5) == 4) {
do_dma();
if (SCSIID->direction < 0)
wd_do_transfer_in();
static void wd_cmd_sel_atn(void)
{
#if WD33C93_DEBUG > 0
- write_log("* %s select with atn, ID=%d\n", WD33C93, wdregs[WD_DESTINATION_ID]);
+ write_log("* %s select with atn, ID=%d\n", WD33C93, wdregs[WD_DESTINATION_ID] & 0x7);
#endif
wd_phase = 0;
wdregs[WD_COMMAND_PHASE] = 0;
static void wd_cmd_reset(void)
{
+ int i;
+
#if WD33C93_DEBUG > 0
write_log("%s reset\n", WD33C93);
#endif
- set_status(1, 0);
+ for (i = 1; i < 0x16; i++)
+ wdregs[i] = 0;
+ wdregs[0x18] = 0;
+ if (!wd33c93a)
+ wdregs[0] &= ~(0x08 | 0x10);
+ set_status((wdregs[0] & 0x10) ? 1 : 0, 1);
}
static void wd_cmd_abort(void)
void wdscsi_put(uae_u8 d)
{
#if WD33C93_DEBUG > 1
- if (sasr != WD_DATA)
+ if (WD33C93_DEBUG > 3 || sasr != WD_DATA)
write_log("W %s REG %02.2X (%d) = %02.2X (%d) PC=%08X\n", WD33C93, sasr, sasr, d, d, M68K_GETPC);
#endif
if (!writeonlyreg(sasr))
wd_used = 1;
write_log("%s in use\n", WD33C93);
}
- if (sasr == WD_DATA) {
+ if (sasr == WD_COMMAND_PHASE) {
+#if WD33C93_DEBUG > 0
+ write_log("%s PHASE=%02X\n", WD33C93, d);
+#endif
+ } else if (sasr == WD_DATA) {
if (wd_dataoffset < sizeof wd_data)
wd_data[wd_dataoffset] = wdregs[sasr];
wd_dataoffset++;
case WD_CMD_SEL_ATN:
wd_cmd_sel_atn();
break;
+ case WD_CMD_SEL_ATN_XFER:
+ wd_cmd_sel_xfer_atn();
+ break;
case WD_CMD_SEL_XFER:
wd_cmd_sel_xfer();
break;
}
incsasr(0);
#if WD33C93_DEBUG > 1
- if (osasr != WD_DATA)
+ if (WD33C93_DEBUG > 3 || osasr != WD_DATA)
write_log("R %s REG %02.2X (%d) = %02.2X (%d) PC=%08X\n", WD33C93, osasr, osasr, v, v, M68K_GETPC);
#endif
return v;
if (addr < 0x40)
return dmacmemory[addr];
if (addr >= ROM_OFFSET) {
- //write_log("%08x %08x\n", addr, M68K_GETPC);
- if (rom)
- return rom[addr & ROM_MASK];
+ if (rom) {
+ int off = addr & rom_mask;
+ if (rombankswitcher && (addr & 0xffe0) == ROM_OFFSET)
+ rombank = (addr & 0x02) >> 1;
+ off += rombank * rom_size;
+ return rom[off];
+ }
return 0;
}
case 0xa3:
case 0xa5:
case 0xa7:
+ case 0xc1:
+ case 0xc3:
+ case 0xc5:
+ case 0xc7:
v = 0xff;
break;
case 0xe0:
#endif
b &= 0xff;
addr &= 65535;
- if (addr == 0x48) {
+ if (addr == 0x48 && !configured) {
map_banks (&dmaca2091_bank, b, 0x10000 >> 16, 0x10000);
- write_log ("A590/A2091 autoconfigured at %02.2X0000\n", b);
+ write_log ("A590/A2091 Z2 autoconfigured at %02.2X0000\n", b);
configured = 1;
expamem_next();
return;
}
- if (addr == 0x4c) {
+ if (addr == 0x4c && !configured) {
write_log ("A590/A2091 DMAC AUTOCONFIG SHUT-UP!\n");
configured = 1;
expamem_next();
#endif
addr &= 65535;
if (addr >= ROM_OFFSET)
- v = (rom[addr & ROM_MASK] << 8) | rom[(addr + 1) & ROM_MASK];
+ v = (rom[addr & rom_mask] << 8) | rom[(addr + 1) & rom_mask];
return v;
}
static uae_u32 REGPARAM2 dmac_lgeti (uaecptr addr)
dmac_stop_dma();
break;
case 0x41:
- if ((mode & 0x10) || ((mode & 0x70) > 0x10 && (mode & 0x0f) == 1))
+ if (mode & 0x10)
sasr = val;
break;
case 0x49:
sasr = val;
break;
case 0x43:
- wdscsi_put(val);
+ if (mode & 0x10)
+ wdscsi_put(val);
+ else
+ sasr = val;
break;
}
}
int addscsi(int ch, char *path, int blocksize, int readonly,
char *devname, int sectors, int surfaces, int reserved,
- int bootpri, char *filesys)
+ int bootpri, char *filesys, int scsi_level)
{
struct hd_hardfiledata *hfd;
freescsi(scsis[ch]);
hfd = xcalloc(sizeof(struct hd_hardfiledata), 1);
if (!hdf_hd_open(hfd, path, blocksize, readonly, devname, sectors, surfaces, reserved, bootpri, filesys))
return 0;
- hfd->ansi_version = 2;
+ hfd->ansi_version = scsi_level;
scsis[ch] = scsi_alloc(ch, hfd);
return scsis[ch] ? 1 : 0;
}
+static void freenativescsi(void)
+{
+ int i;
+ for (i = 0; i < 7; i++) {
+ freescsi(scsis[i]);
+ scsis[i] = NULL;
+ }
+}
+
static void addnativescsi(void)
{
int i, j;
int types[MAX_TOTAL_DEVICES];
struct device_info dis[MAX_TOTAL_DEVICES];
+ freenativescsi();
i = 0;
while (i < MAX_TOTAL_DEVICES) {
types[i] = -1;
char *devname, int sectors, int surfaces, int reserved,
int bootpri, char *filesys)
{
- return addscsi(ch, path, blocksize, readonly, devname, sectors, surfaces, reserved, bootpri, filesys);
+ return addscsi(ch, path, blocksize, readonly, devname, sectors, surfaces, reserved, bootpri, filesys, 2);
}
void a3000scsi_reset(void)
void a3000scsi_free(void)
{
- int i;
- for (i = 0; i < 7; i++)
- freescsi(scsis[i]);
+ freenativescsi();
}
int a2091_add_scsi_unit(int ch, char *path, int blocksize, int readonly,
char *devname, int sectors, int surfaces, int reserved,
int bootpri, char *filesys)
{
- return addscsi(ch, path, blocksize, readonly, devname, sectors, surfaces, reserved, bootpri, filesys);
+ return addscsi(ch, path, blocksize, readonly, devname, sectors, surfaces, reserved, bootpri, filesys, 1);
}
void a2091_free (void)
{
- int i;
- for (i = 0; i < 7; i++)
- freescsi(scsis[i]);
+ freenativescsi();
xfree(rom);
rom = NULL;
}
void a2091_init (void)
{
struct zfile *z;
- int roms[4];
+ int roms[5];
struct romlist *rl;
configured = 0;
ew (0x28, ROM_VECTOR >> 8);
ew (0x2c, ROM_VECTOR);
+ ew (0x18, 0x00); /* ser.no. Byte 0 */
+ ew (0x1c, 0x00); /* ser.no. Byte 1 */
+ ew (0x20, 0x00); /* ser.no. Byte 2 */
+ ew (0x24, 0x00); /* ser.no. Byte 3 */
+
roms[0] = 55;
roms[1] = 54;
roms[2] = 53;
- roms[3] = -1;
+ roms[3] = 56;
+ roms[4] = -1;
+ //roms[0] = 56;
+ rombankswitcher = 0;
+ rombank = 0;
rl = getromlistbyids(roms);
if (rl) {
write_log("A590/A2091 BOOT ROM '%s' %d.%d ", rl->path, rl->rd->ver, rl->rd->rev);
z = zfile_fopen(rl->path, "rb");
if (z) {
- write_log("loaded\n");
- rom = xmalloc (ROM_SIZE);
- zfile_fread (rom, ROM_SIZE, 1, z);
+ if (rl->rd->id == 56) {
+ int i;
+ rom_size = 32768;
+ rombankswitcher = 1;
+ rom = xmalloc (rom_size * 2);
+ for (i = 0; i < rom_size; i++)
+ zfile_fread(rom + i * 2, 1, 1, z);
+ } else {
+ rom_size = 16384;
+ rom = xmalloc (rom_size);
+ zfile_fread (rom, rom_size, 1, z);
+ }
zfile_fclose(z);
+ rom_mask = rom_size - 1;
+ write_log("loaded\n");
} else {
write_log("failed to load\n");
}
char *devname, int sectors, int surfaces, int reserved,
int bootpri, char *filesys)
{
- return addscsi(ch, path, blocksize, readonly, devname, sectors, surfaces, reserved, bootpri, filesys);
+ return addscsi(ch, path, blocksize, readonly, devname, sectors, surfaces, reserved, bootpri, filesys, 1);
}
void cdtv_free (void)
}
}
if (*p == 0 || *p == ';') {
- rl = getrombyident(ver, rev, subver, subrev, modelp, round);
+ rl = getromlistbyident(ver, rev, subver, subrev, modelp, round);
if (rl) {
for (i = 0; rl[i]; i++) {
if (round) {
void check_prefs_changed_comp (void)
{
+ static int cachesize_prev, comptrust_prev, compforce_prev;
+
currprefs.comptrustbyte = changed_prefs.comptrustbyte;
currprefs.comptrustword = changed_prefs.comptrustword;
currprefs.comptrustlong = changed_prefs.comptrustlong;
currprefs.compfpu = changed_prefs.compfpu;
currprefs.fpu_strict = changed_prefs.fpu_strict;
- if (currprefs.cachesize!=changed_prefs.cachesize) {
+ if (currprefs.cachesize != changed_prefs.cachesize) {
+ if (currprefs.cachesize == 0 && changed_prefs.cachesize && cachesize_prev) {
+ changed_prefs.comptrustbyte = currprefs.comptrustbyte = comptrust_prev;
+ changed_prefs.comptrustword = currprefs.comptrustword = comptrust_prev;
+ changed_prefs.comptrustlong = currprefs.comptrustlong = comptrust_prev;
+ changed_prefs.comptrustnaddr = currprefs.comptrustnaddr = comptrust_prev;
+ changed_prefs.compforcesettings = currprefs.compforcesettings = compforce_prev;
+ } else if (currprefs.cachesize && changed_prefs.cachesize == 0) {
+ comptrust_prev = currprefs.comptrustbyte;
+ compforce_prev = currprefs.compforcesettings;
+ cachesize_prev = currprefs.cachesize;
+ }
currprefs.cachesize = changed_prefs.cachesize;
alloc_cache();
}
static int test_copper_dangerous (unsigned int address)
{
- if ((address & 0x1fe) < (copcon & 2 ? ((currprefs.chipset_mask & CSMASK_AGA) ? 0 : 0x40u) : 0x80u)) {
+ if ((address & 0x1fe) < ((copcon & 2) ? ((currprefs.chipset_mask & CSMASK_AGA) ? 0 : 0x40u) : 0x80u)) {
cop_state.state = COP_stop;
copper_enabled_thisline = 0;
unset_special (®s, SPCFLAG_COPPER);
return 0;
}
+static int custom_wput_copper(int hpos, uaecptr addr, uae_u32 value, int noget)
+{
+ debug_wputpeek (0xdff000 + (cop_state.saved_i1 & 0x1fe), cop_state.saved_i2);
+ return custom_wput_1 (hpos, addr, value, noget);
+}
+
static void perform_copper_write (int old_hpos)
{
unsigned int address = cop_state.saved_i1 & 0x1FE;
cop_state.ip = cop2lc;
cop_state.state = COP_strobe_delay;
} else {
- custom_wput_1 (old_hpos, cop_state.saved_i1, cop_state.saved_i2, 0);
+ custom_wput_copper (old_hpos, cop_state.saved_i1, cop_state.saved_i2, 0);
cop_state.last_write = cop_state.saved_i1;
cop_state.last_write_hpos = old_hpos;
old_hpos++;
decide_fetch (hpos);
decide_blitter (hpos);
v = last_custom_value;
- r = custom_wput_1 (hpos, addr, v, 1);
+ r = custom_wput_copper (hpos, addr, v, 1);
}
return v;
}
#endif
return ((uae_u32)custom_wget (addr) << 16) | custom_wget (addr + 2);
}
-
static int REGPARAM2 custom_wput_1 (int hpos, uaecptr addr, uae_u32 value, int noget)
{
addr &= 0x1FE;
" g [<address>] Start execution at the current address or <address>\n"
" c Dump state of the CIA, disk drives and custom registers\n"
" r Dump state of the CPU\n"
+ " r <reg> <value> Modify CPU registers (Dx,Ax,USP,ISP,VBR,...)\n"
" m <address> [<lines>] Memory dump starting at <address>\n"
" m r<register> Memory dump starting at <register>\n"
" d <address> [<lines>] Disassembly starting at <address>\n"
if (memwatch_func (addr, 2, 1, &v))
debug_mem_banks[off]->bput(addr, v);
}
-
static int REGPARAM2 debug_check (uaecptr addr, uae_u32 size)
{
return debug_mem_banks[munge24 (addr) >> 16]->check (addr, size);
{
return debug_mem_banks[munge24 (addr) >> 16]->xlateaddr (addr);
}
+void debug_putlpeek(uaecptr addr, uae_u32 v)
+{
+ if (!memwatch_enabled)
+ return;
+ memwatch_func (addr, 2, 4, &v);
+}
+void debug_wputpeek(uaecptr addr, uae_u32 v)
+{
+ if (!memwatch_enabled)
+ return;
+ memwatch_func (addr, 2, 2, &v);
+}
+void debug_bputpeek(uaecptr addr, uae_u32 v)
+{
+ if (!memwatch_enabled)
+ return;
+ memwatch_func (addr, 2, 1, &v);
+}
+void debug_bgetpeek (uaecptr addr, uae_u32 v)
+{
+ uae_u32 vv = v;
+ if (!memwatch_enabled)
+ return;
+ memwatch_func (addr, 1, 1, &vv);
+}
+void debug_wgetpeek (uaecptr addr, uae_u32 v)
+{
+ uae_u32 vv = v;
+ if (!memwatch_enabled)
+ return;
+ memwatch_func (addr, 1, 2, &vv);
+}
+void debug_lgetpeek (uaecptr addr, uae_u32 v)
+{
+ uae_u32 vv = v;
+ if (!memwatch_enabled)
+ return;
+ memwatch_func (addr, 1, 4, &vv);
+}
static void deinitialize_memwatch (void)
{
memwatch_dump (num);
}
+static void writeintoreg (char **c)
+{
+ char cc, cc2;
+
+ ignore_ws(c);
+ cc = toupper(*c[0]);
+ cc2 = toupper(*c[1]);
+ if ((cc == 'D' || cc == 'A') && cc2 >= '0' && cc2 <= '7') {
+
+
+ }
+}
+
+
static void writeintomem (char **c)
{
uae_u32 addr = 0;
uae_u32 v;
char parm[10];
char c1, c2;
+ int i;
if (!next_string (inptr, parm, sizeof (parm), 1))
return;
c1 = toupper (parm[0]);
- c2 = toupper (parm[1]);
+ c2 = 99;
if (c1 == 'A' || c1 == 'D' || c1 == 'P') {
- if (!isdigit (c2))
- return;
- c2 -= '0';
+ c2 = toupper (parm[1]);
+ if (isdigit (c2))
+ c2 -= '0';
+ else
+ c2 = 99;
}
v = readhex (inptr);
- if (c1 == 'A')
+ if (c1 == 'A' && c2 < 8)
regs.regs[8 + c2] = v;
- else if (c1 == 'D')
+ else if (c1 == 'D' && c2 < 8)
regs.regs[c2] = v;
else if (c1 == 'P' && c2 == 0)
regs.irc = v;
else if (c1 == 'P' && c2 == 1)
regs.ir = v;
- else if (!strcmp (parm, "VBR"))
- regs.vbr = v;
- else if (!strcmp (parm, "USP")) {
- regs.usp = v;
- MakeFromSR (®s);
- } else if (!strcmp (parm, "ISP")) {
- regs.isp = v;
- MakeFromSR (®s);
- } else if (!strcmp (parm, "MSP")) {
- regs.msp = v;
- MakeFromSR (®s);
- } else if (!strcmp (parm, "SR")) {
+ else if (!strcmp (parm, "SR")) {
regs.sr = v;
MakeFromSR (®s);
} else if (!strcmp (parm, "CCR")) {
- regs.sr = (regs.sr & ~15) | (v & 15);
+ regs.sr = (regs.sr & ~31) | (v & 31);
MakeFromSR (®s);
+ } else if (!strcmp (parm, "PC")) {
+ m68k_setpc(®s, v);
+ fill_prefetch_slow(®s);
+ } else {
+ for (i = 0; m2cregs[i].regname; i++) {
+ if (!strcmp (parm, m2cregs[i].regname))
+ val_move2c2 (m2cregs[i].regno, v);
+ }
}
}
dump_vectors (addr);
break;
case 'e': dump_custom_regs (tolower(*inptr) == 'a'); break;
- case 'r': if (more_params(&inptr))
+ case 'r':
+ {
+ if (more_params(&inptr))
m68k_modify (&inptr);
else
m68k_dumpstate (stdout, &nextpc);
+ }
break;
case 'D': deepcheatsearch (&inptr); break;
case 'C': cheatsearch (&inptr); break;
static void addhistory(void)
{
uae_u32 pc = m68k_getpc(®s);
- if (pc >= 0xf00000 && pc <= 0xffffff)
+ if (!notinrom())
return;
history[lasthist] = regs;
history[lasthist].pc = m68k_getpc(®s);
if (skipaddr_doskip) {
if (skipaddr_start == pc)
bp = 1;
- if ((processptr || processname) && !notinrom()) {
+ if ((processptr || processname) && notinrom()) {
uaecptr execbase = get_long (4);
uaecptr activetask = get_long (execbase + 276);
int process = get_byte(activetask + 8) == 13 ? 1 : 0;
strcpy(bankname, "Gayle (low)");
if (currprefs.cs_ide == 2)
strcpy(bankname, "A4000 IDE");
- if (currprefs.cs_mbdmac == 2)
+ if (currprefs.cs_mbdmac == 2) {
strcat(bankname," + NCR53C710 SCSI");
+ ncr_reset();
+ }
gayle_bank.name = bankname;
}
return cmd_writex (hfd, bank_data->xlateaddr (dataptr), offset, len);
}
+static int checkbounds(struct hardfiledata *hfd, uae_u64 offset, uae_u64 len)
+{
+ if (offset >= hfd->size)
+ return 0;
+ if (offset + len > hfd->size)
+ return 0;
+ return 1;
+}
+
int scsi_emulate(struct hardfiledata *hfd, struct hd_hardfiledata *hdhfd, uae_u8 *cmdbuf, int scsi_cmd_len,
uae_u8 *scsi_data, int *data_len, uae_u8 *r, int *reply_len, uae_u8 *s, int *sense_len)
{
len = cmdbuf[4];
if (!len) len = 256;
len *= hfd->blocksize;
- scsi_len = (uae_u32)cmd_readx (hfd, scsi_data, offset, len);
+ if (checkbounds(hfd, offset, len))
+ scsi_len = (uae_u32)cmd_readx (hfd, scsi_data, offset, len);
break;
case 0x0a: /* WRITE (6) */
offset = ((cmdbuf[1] & 31) << 16) | (cmdbuf[2] << 8) | cmdbuf[3];
len = cmdbuf[4];
if (!len) len = 256;
len *= hfd->blocksize;
- scsi_len = (uae_u32)cmd_writex (hfd, scsi_data, offset, len);
+ if (checkbounds(hfd, offset, len))
+ scsi_len = (uae_u32)cmd_writex (hfd, scsi_data, offset, len);
break;
case 0x12: /* INQUIRY */
+ if ((cmdbuf[1] & 1) || cmdbuf[2] != 0)
+ goto err;
len = cmdbuf[4];
+ if (cmdbuf[1] >> 5)
+ goto err;//r[0] = 0x7f; /* no lun supported */
r[2] = 2; /* supports SCSI-2 */
r[3] = 2; /* response data format */
r[4] = 32; /* additional length */
+ r[7] = 0x20; /* 16 bit bus */
scsi_len = lr = len < 36 ? (uae_u32)len : 36;
if (hdhfd) {
- r[2] = (hdhfd->iso_version << 6) | (hdhfd->ecma_version << 3) | hdhfd->ansi_version;
+ r[2] = hdhfd->ansi_version;
r[3] = hdhfd->ansi_version >= 2 ? 2 : 0;
+ r[7] = hdhfd->ansi_version >= 2 ? 0x20 : 0;
}
- r[7] = 0x20; /* 16 bit bus */
i = 0; /* vendor id */
while (i < 8 && hfd->vendor_id[i]) {
r[8 + i] = hfd->vendor_id[i];
int pc = cmdbuf[2] >> 6;
int pcode = cmdbuf[2] & 0x3f;
int dbd = cmdbuf[1] & 8;
- write_log("MODE SENSE PC=%d CODE=%d DBD=%d\n", pc, pcode, dbd);
+ //write_log("MODE SENSE PC=%d CODE=%d DBD=%d\n", pc, pcode, dbd);
p = r;
p[0] = 4 - 1;
p[1] = 0;
p[2] = 0;
p[3] = 0;
p += 4;
+ if (!dbd) {
+ uae_u32 blocks = (uae_u32)(hfd->size / hfd->blocksize);
+ p[-1] = 8;
+ wl(p + 0, blocks);
+ wl(p + 4, hfd->blocksize);
+ p += 8;
+ }
if (pcode == 0) {
p[0] = 0;
p[1] = 0;
} else if (pcode == 3) {
p[0] = 3;
p[1] = 24;
+ p[3] = 1;
p[10] = hdhfd->secspertrack >> 8;
p[11] = hdhfd->secspertrack;
p[12] = hfd->blocksize >> 8;
p[13] = hfd->blocksize;
+ p[15] = 1; // interleave
p[20] = 0x80;
r[0] += p[1];
} else if (pcode == 4) {
wl(p + 1, hdhfd->cyls);
p[1] = 24;
p[5] = hdhfd->heads;
+ wl(p + 13, hdhfd->cyls);
ww(p + 20, 5400);
r[0] += p[1];
} else {
goto err;
}
+ r[0] += r[3];
scsi_len = lr = r[0] + 1;
break;
}
break;
+ case 0x1d: /* SEND DIAGNOSTICS */
+ break;
case 0x25: /* READ_CAPACITY */
- wl (r, (uae_u32)(hfd->size / hfd->blocksize - 1));
- wl (r + 4, hfd->blocksize);
- scsi_len = lr = 8;
+ {
+ int pmi = cmdbuf[8] & 1;
+ uae_u32 lba = (cmdbuf[2] << 24) | (cmdbuf[3] << 16) | (cmdbuf[2] << 8) | cmdbuf[3];
+ uae_u32 blocks = (uae_u32)(hfd->size / hfd->blocksize - 1);
+ if (pmi) {
+ lba += hdhfd->secspertrack * hdhfd->heads;
+ lba /= hdhfd->secspertrack * hdhfd->heads;
+ lba *= hdhfd->secspertrack * hdhfd->heads;
+ if (lba > blocks)
+ lba = blocks;
+ blocks = lba;
+ }
+ wl (r, blocks);
+ wl (r + 4, hfd->blocksize);
+ scsi_len = lr = 8;
+ }
break;
case 0x28: /* READ (10) */
offset = rl (cmdbuf + 2);
offset *= hfd->blocksize;
len = rl (cmdbuf + 7 - 2) & 0xffff;
len *= hfd->blocksize;
- scsi_len = (uae_u32)cmd_readx (hfd, scsi_data, offset, len);
+ if (checkbounds(hfd, offset, len))
+ scsi_len = (uae_u32)cmd_readx (hfd, scsi_data, offset, len);
break;
case 0x2a: /* WRITE (10) */
offset = rl (cmdbuf + 2);
offset *= hfd->blocksize;
len = rl (cmdbuf + 7 - 2) & 0xffff;
len *= hfd->blocksize;
- scsi_len = (uae_u32)cmd_writex (hfd, scsi_data, offset, len);
+ if (checkbounds(hfd, offset, len))
+ scsi_len = (uae_u32)cmd_writex (hfd, scsi_data, offset, len);
break;
case 0x35: /* SYNCRONIZE CACHE (10) */
break;
offset *= hfd->blocksize;
len = rl (cmdbuf + 6);
len *= hfd->blocksize;
- scsi_len = (uae_u32)cmd_readx (hfd, scsi_data, offset, len);
+ if (checkbounds(hfd, offset, len))
+ scsi_len = (uae_u32)cmd_readx (hfd, scsi_data, offset, len);
break;
case 0xaa: /* WRITE (12) */
offset = rl (cmdbuf + 2);
offset *= hfd->blocksize;
len = rl (cmdbuf + 6);
len *= hfd->blocksize;
- scsi_len = (uae_u32)cmd_writex (hfd, scsi_data, offset, len);
+ if (checkbounds(hfd, offset, len))
+ scsi_len = (uae_u32)cmd_writex (hfd, scsi_data, offset, len);
break;
case 0x37: /* READ DEFECT DATA */
write_log ("UAEHF: READ DEFECT DATA\n");
extern struct scsi_data *scsis[8];
#define WD33C93 "WD33C93"
-#define SCSIID (scsis[wdregs[WD_DESTINATION_ID]])
+#define SCSIID (scsis[wdregs[WD_DESTINATION_ID] & 7])
extern int a2091_add_scsi_unit(int ch, char *path, int blocksize, int readonly,
char *devname, int sectors, int surfaces, int reserved,
extern int addscsi(int ch, char *path, int blocksize, int readonly,
char *devname, int sectors, int surfaces, int reserved,
- int bootpri, char *filesys);
+ int bootpri, char *filesys, int scsi_level);
#endif
#define MAX_TOTAL_DEVICES 8
-#define DEVICE_SCSI_BUFSIZE 4096
+#define DEVICE_SCSI_BUFSIZE 65536
//#define device_debug write_log
#define device_debug
extern void memwatch_dump2 (char *buf, int bufsize, int num);
+void debug_lgetpeek (uaecptr addr, uae_u32 v);
+void debug_wgetpeek (uaecptr addr, uae_u32 v);
+void debug_bgetpeek (uaecptr addr, uae_u32 v);
+void debug_bputpeek(uaecptr addr, uae_u32 v);
+void debug_wputpeek(uaecptr addr, uae_u32 v);
+void debug_lputpeek(uaecptr addr, uae_u32 v);
+
+
#else
STATIC_INLINE void activate_debugger (void) { };
int secspertrack_def;
int heads_def;
char *path;
- int iso_version, ecma_version, ansi_version;
+ int ansi_version;
};
#define HD_CONTROLLER_UAE 0
extern int movec_illg (int regno);
extern uae_u32 val_move2c (int regno);
+extern void val_move2c2 (int regno, uae_u32 val);
struct cpum2c {
int regno;
char *regname;
};
-struct romlist **getrombyident(int ver, int rev, int subver, int subrev, char *model, int all)
+struct romlist **getromlistbyident(int ver, int rev, int subver, int subrev, char *model, int all)
{
int i, j, ok, out, max;
struct romdata *rd;
return 0;
}
+STATIC_INLINE notcrc32(uae_u32 crc32)
+{
+ if (crc32 == 0xffffffff || crc32 == 0x00000000)
+ return 1;
+ return 0;
+}
+
struct romdata *getromdatabycrc (uae_u32 crc32)
{
int i = 0;
while (roms[i].name) {
- if (crc32 == roms[i].crc32)
+ if (crc32 == roms[i].crc32 && !notcrc32(crc32))
return &roms[i];
i++;
}
memcpy (rom, tmp, 4);
i = 0;
while (roms[i].name) {
- if (roms[i].crc32 && roms[i].size >= size) {
+ if (!notcrc32(roms[i].crc32) && roms[i].size >= size) {
if (crc32a == roms[i].crc32 || crc32b == roms[i].crc32)
return &roms[i];
if (crc32c == roms[i].crc32 && roms[i].type == ROMTYPE_AR)
void a3000_fakekick(int map)
{
static uae_u8 *blop;
+ static int f0;
+
if (map) {
uae_u8 *fkickmemory = a3000lmemory + allocated_a3000lmem - fkickmem_size;
- if (!blop)
- blop = xmalloc (fkickmem_size);
- memcpy (blop, kickmemory, fkickmem_size);
- memcpy (kickmemory, fkickmemory, fkickmem_size);
+ if (fkickmemory[2] == 0x4e && fkickmemory[3] == 0xf9 && fkickmemory[4] == 0x00) {
+ if (!blop)
+ blop = xmalloc (fkickmem_size);
+ memcpy (blop, kickmemory, fkickmem_size);
+ if (fkickmemory[5] == 0xfc) {
+ memcpy (kickmemory, fkickmemory, fkickmem_size / 2);
+ memcpy (kickmemory + fkickmem_size / 2, fkickmemory, fkickmem_size / 2);
+ if (!extendedkickmemory) {
+ if (!need_uae_boot_rom()) {
+ extendedkickmem_size = 65536;
+ extendedkickmem_mask = extendedkickmem_size - 1;
+ extendedkickmemory = (uae_u8 *) mapped_malloc (extendedkickmem_size, "rom_f0");
+ extendedkickmem_bank.baseaddr = (uae_u8 *) extendedkickmemory;
+ memcpy(extendedkickmemory, fkickmemory + fkickmem_size / 2, 65536);
+ map_banks(&extendedkickmem_bank, 0xf0, 1, 1);
+ f0 = 1;
+ } else {
+ write_log("A3000 Bonus hack: can't map bonus when uae boot rom is enabled\n");
+ }
+ }
+ } else {
+ memcpy (kickmemory, fkickmemory, fkickmem_size);
+ }
+ }
} else {
+ if (f0) {
+ map_banks(&dummy_bank, 0xf0, 1, 1);
+ mapped_free(extendedkickmemory);
+ extendedkickmemory = NULL;
+ f0 = 0;
+ }
if (blop)
memcpy (kickmemory, blop, fkickmem_size);
xfree(blop);
*/
#define NCR_LOG 1
+#define NCR_DEBUG 1
#include "sysconfig.h"
#include "sysdeps.h"
#define NCRNAME "NCR53C710"
#define NCR_REGS 0x40
-#define ROM_VECTOR 0x8080
-#define ROM_OFFSET 0x8000
+#define ROM_VECTOR 0x0200
+#define ROM_OFFSET 0x0000
#define ROM_SIZE 32768
#define ROM_MASK (ROM_SIZE - 1)
-#define BOARD_SIZE (65536 * 2)
+#define BOARD_SIZE 16777216
static uae_u8 *rom;
+static int board_mask;
static int configured;
static uae_u8 acmemory[100];
static uae_u8 read_rom(uaecptr addr)
{
- int off;
- uae_u8 v;
-
- addr -= 0x8080;
- off = (addr & (BOARD_SIZE - 1)) / 4;
- off += 0x80;
-
- if ((addr & 2))
- v = (rom[off] & 0x0f) << 4;
- else
- v = (rom[off] & 0xf0);
- write_log("%08.8X:%04.4X = %02.2X PC=%08X\n", addr, off, v, M68K_GETPC);
+ uae_u8 v = rom[addr];
+ //write_log("%08.8X = %02.2X PC=%08X\n", addr, v, M68K_GETPC);
return v;
}
void ncr_bput2(uaecptr addr, uae_u32 val)
{
- addr &= 0xffff;
+ addr &= board_mask;
if (addr >= NCR_REGS)
return;
switch (addr)
ncrregs[ISTAT_REG] = 0;
break;
case SCID_REG:
- ncrregs[ISTAT_REG] |= 2;
- //ncrregs[SSTAT1_REG] |= 1 << 4;
- //INT2();
break;
uae_u32 ncr_bget2(uaecptr addr)
{
- uae_u32 v;
+ uae_u32 v = 0;
- addr &= 0xffff;
- if (rom && addr >= ROM_OFFSET)
+ addr &= board_mask;
+ if (rom && addr >= ROM_VECTOR && addr >= ROM_OFFSET)
return read_rom(addr);
if (addr >= NCR_REGS)
- return 0;
+ return v;
v = ncrregs[addr];
switch (addr)
{
v |= 0x20;
break;
case ISTAT_REG:
- if (v)
- v |= 2;
- INT2();
break;
case CTEST8_REG:
v &= 0x0f; // revision 0
addr &= 65535;
v = (ncr_bget2 (addr) << 24) | (ncr_bget2 (addr + 1) << 16) |
(ncr_bget2 (addr + 2) << 8) | (ncr_bget2 (addr + 3));
-#ifdef NCR_DEBUG
- if (addr >= 0x40 && addr < ROM_OFFSET)
+#if NCR_DEBUG > 0
+ if (addr < ROM_VECTOR)
write_log ("ncr_lget %08.8X=%08.8X PC=%08.8X\n", addr, v, M68K_GETPC);
#endif
return v;
#ifdef JIT
special_mem |= S_READ;
#endif
- addr &= 65535;
+ addr &= board_mask;
v = (ncr_bget2 (addr) << 8) | ncr_bget2 (addr + 1);
#if NCR_DEBUG > 0
- if (addr >= 0x40 && addr < ROM_OFFSET)
+ if (addr < ROM_VECTOR)
write_log ("ncr_wget %08.8X=%04.4X PC=%08.8X\n", addr, v, M68K_GETPC);
#endif
return v;
#ifdef JIT
special_mem |= S_READ;
#endif
- addr &= 65535;
+ addr &= board_mask;
if (!configured) {
if (addr >= sizeof acmemory)
return 0;
#ifdef JIT
special_mem |= S_WRITE;
#endif
- addr &= 65535;
+ addr &= board_mask;
#if NCR_DEBUG > 0
- if (addr >= 0x40 && addr < ROM_OFFSET)
+ if (addr < ROM_VECTOR)
write_log ("ncr_lput %08.8X=%08.8X PC=%08.8X\n", addr, l, M68K_GETPC);
#endif
ncr_bput2 (addr, l >> 24);
#ifdef JIT
special_mem |= S_WRITE;
#endif
- addr &= 65535;
+ w &= 0xffff;
+ addr &= board_mask;
#if NCR_DEBUG > 0
- if (addr >= 0x40 && addr < ROM_OFFSET)
+ if (addr < ROM_VECTOR)
write_log ("ncr_wput %04.4X=%04.4X PC=%08.8X\n", addr, w & 65535, M68K_GETPC);
#endif
+ if (addr == 0x44 && !configured) {
+ uae_u32 value = (p96ram_start + ((currprefs.gfxmem_size + 0xffffff) & ~0xffffff)) >> 16;
+ chipmem_wput (regs.regs[11] + 0x20, value);
+ chipmem_wput (regs.regs[11] + 0x28, value);
+ map_banks (&ncr_bank, value, BOARD_SIZE >> 16, 0);
+ write_log ("A4091 Z3 autoconfigured at %04X0000\n", value);
+ configured = 1;
+ expamem_next();
+ return;
+ }
ncr_bput2 (addr, w >> 8);
ncr_bput2 (addr + 1, w);
}
special_mem |= S_WRITE;
#endif
b &= 0xff;
- addr &= 65535;
- if (addr == 0x48) {
- map_banks (&ncr_bank, b, BOARD_SIZE >> 16, BOARD_SIZE);
- write_log ("A4091 autoconfigured at %02.2X0000\n", b);
- configured = 1;
- expamem_next();
- return;
- }
- if (addr == 0x4c) {
+ addr &= board_mask;
+ if (addr == 0x4c && !configured) {
write_log ("A4091 AUTOCONFIG SHUT-UP!\n");
configured = 1;
expamem_next();
ncr_bput2 (addr, b);
}
-static uae_u32 REGPARAM2 ncr_wgeti (uaecptr addr)
-{
- uae_u32 v = 0xffff;
-#ifdef JIT
- special_mem |= S_READ;
-#endif
- addr &= 65535;
- if (addr >= ROM_OFFSET)
- v = (rom[addr & ROM_MASK] << 8) | rom[(addr + 1) & ROM_MASK];
- return v;
-}
-static uae_u32 REGPARAM2 ncr_lgeti (uaecptr addr)
-{
- uae_u32 v = 0xffff;
-#ifdef JIT
- special_mem |= S_READ;
-#endif
- addr &= 65535;
- v = (ncr_wgeti(addr) << 16) | ncr_wgeti(addr + 2);
- return v;
-}
-
static addrbank ncr_bank = {
ncr_lget, ncr_wget, ncr_bget,
ncr_lput, ncr_wput, ncr_bput,
default_xlate, default_check, NULL, "A4091",
- ncr_lgeti, ncr_wgeti, ABFLAG_IO
+ dummy_lgeti, dummy_wgeti, ABFLAG_IO
};
static void ew (int addr, uae_u32 value)
{
- addr &= 0xffff;
if (addr == 00 || addr == 02 || addr == 0x40 || addr == 0x42) {
acmemory[addr] = (value & 0xf0);
acmemory[addr + 2] = (value & 0x0f) << 4;
void ncr_reset (void)
{
+ board_mask = 131072 - 1;
configured = 0;
+ if (currprefs.cs_mbdmac == 2) {
+ board_mask = 65535 - 1;
+ configured = -1;
+ }
}
void ncr_init (void)
struct zfile *z;
int roms[3];
struct romlist *rl;
+ int i;
configured = 0;
memset (acmemory, 0xff, 100);
- ew (0x00, 0xc0 | 0x02 | 0x10);
+ ew (0x00, 0x80 | 0x10 | 0x00);
+ ew (0x08, 0x80 | 0x20 | 0x10);
+
/* A4091 hardware id */
ew (0x04, 0x54);
/* commodore's manufacturer id */
ew (0x28, ROM_VECTOR >> 8);
ew (0x2c, ROM_VECTOR);
- roms[0] = 57;
- roms[1] = 56;
+ ew (0x18, 0x00); /* ser.no. Byte 0 */
+ ew (0x1c, 0x00); /* ser.no. Byte 1 */
+ ew (0x20, 0x00); /* ser.no. Byte 2 */
+ ew (0x24, 0x00); /* ser.no. Byte 3 */
+
+ roms[0] = 58;
+ roms[1] = 57;
roms[2] = -1;
rl = getromlistbyids(roms);
z = zfile_fopen(rl->path, "rb");
if (z) {
write_log("loaded\n");
- rom = xmalloc (ROM_SIZE);
- zfile_fread (rom, ROM_SIZE, 1, z);
+ rom = xmalloc (ROM_SIZE * 4);
+ for (i = 0; i < ROM_SIZE; i++) {
+ uae_u8 b;
+ zfile_fread(&b, 1, 1, z);
+ rom[i * 4 + 0] = b;
+ rom[i * 4 + 2] = b << 4;
+ }
zfile_fclose(z);
} else {
write_log("failed to load\n");
} else {
romwarning(roms);
}
- map_banks (&ncr_bank, 0xe80000 >> 16, 0x10000 >> 16, 0x10000);
+ map_banks (&ncr_bank, 0xe80000 >> 16, 65536 >> 16, 0);
}
void mmu_op30(uaecptr pc, uae_u32 opcode, struct regstruct *regs, int isnext, uaecptr extra)
{
if (currprefs.cpu_model != 68030) {
-#if MMUOP_DEBUG > 0
- write_log("Unknown 68030 MMU OP %04X PC=%08X\n", opcode, m68k_getpc(regs));
-#endif
m68k_setpc (regs, pc);
op_illg (opcode, regs);
return;
void mmu_op(uae_u32 opcode, struct regstruct *regs, uae_u32 extra)
{
-#if MMUOP_DEBUG > 0
+#if MMUOP_DEBUG > 1
write_log("mmu_op %04X PC=%08X\n", opcode, m68k_getpc(regs));
#endif
if ((opcode & 0xFE0) == 0x0500) {
} else if ((opcode & 0x0FD8) == 0x548) {
if (currprefs.cpu_model < 68060) { /* PTEST not in 68060 */
/* PTEST */
-#if MMUOP > 0
+#if MMUOP_DEBUG > 0
write_log ("PTEST\n");
#endif
return;
}
}
#if MMUOP_DEBUG > 0
- write_log("Unknown MMU OP\n");
+ write_log("Unknown MMU OP %04X\n", opcode);
#endif
m68k_setpc (regs, m68k_getpc (regs) - 2);
op_illg (opcode, regs);
-1, NULL
};
+void val_move2c2 (int regno, uae_u32 val)
+{
+ switch (regno) {
+ case 0: regs.sfc = val; break;
+ case 1: regs.dfc = val; break;
+ case 2: regs.cacr = val; break;
+ case 3: regs.tcr = val; break;
+ case 4: regs.itt0 = val; break;
+ case 5: regs.itt1 = val; break;
+ case 6: regs.dtt0 = val; break;
+ case 7: regs.dtt1 = val; break;
+ case 8: regs.buscr = val; break;
+ case 0x800: regs.usp = val; break;
+ case 0x801: regs.vbr = val; break;
+ case 0x802: regs.caar = val; break;
+ case 0x803: regs.msp = val; break;
+ case 0x804: regs.isp = val; break;
+ case 0x805: regs.mmusr = val; break;
+ case 0x806: regs.urp = val; break;
+ case 0x807: regs.srp = val; break;
+ case 0x808: regs.pcr = val; break;
+ }
+}
+
uae_u32 val_move2c (int regno)
{
switch (regno) {
!define PRODUCT_NAME "WinUAE"
-!define PRODUCT_VERSION "1.4.2"
-!define PRODUCT_PUBLISHER "Toni Wilen"
+!define PRODUCT_VERSION "1.4.3"
+!define PRODUCT_PUBLISHER "Arabuusimiehet"
!define PRODUCT_WEB_SITE "http://www.winuae.net/"
!define PRODUCT_DIR_REGKEY "Software\Microsoft\Windows\CurrentVersion\App Paths\winuae.exe"
!define PRODUCT_UNINST_KEY "Software\Microsoft\Windows\CurrentVersion\Uninstall\${PRODUCT_NAME}"
if (did == di_mouse) {
if (rdpmouse(buf))
continue;
- if (rnum_mouse < 2 && !os_vista)
- continue;
if (num_mouse >= MAX_INPUT_DEVICES - 1) /* leave space for Windows mouse */
continue;
did += num_mouse;
#define GETBDM(x) (((x) - ((x / 10000) * 10000)) / 100)
#define GETBDD(x) ((x) % 100)
-#define WINUAEBETA 3
+#define WINUAEBETA 4
#define WINUAEPUBLICBETA 1
-#define WINUAEDATE MAKEBD(2007, 5, 27)
+#define WINUAEDATE MAKEBD(2007, 6, 2)
#define WINUAEEXTRA ""
#define WINUAEREV ""
+Beta 4:
+
+- return SCSI-1 style inquiry response when using A590/A2091 SCSI
+ emulation (Old HDToolbox compatibility fix)
+- do not crash with "out of bounds" error if SCSI emulation tried to
+ read/write non-existing HDF block(s)
+- SCSI READ CAPACITY PMI-bit emulated, HDToolbox "Read configuration
+ from drive" compatibility fix
+- A3000 1.3 SuperKickstart support implemented (includes "bonus"
+ code remapping to 0xf00000 area)
+- JIT on/off switching via uae-configuration re-enables direct mode
+- added MOVEC registers and PC to r <reg> <val> debugger command
+- A4091 ("A3090" says driver string in ROM...) Z3 card autoconfig and
+ ROM loading implemented (pointless, no NCR53C710 SCSI chip emulation
+ yet, same infinite loop as with A4000T KS3.1 built-in SCSI driver)
+- A590/A2091 Guru ROM adapter emulated, driver does not yet work,
+ uses not yet emulated WD33C93 features.
+- real SCSI device support (via hardware emulation) is not really
+ working. It isn't so easy to implement after all..
+- copper writes are now detected by memwatch break points (note: writes
+ only, freeze not possible. copper is a special case)
+
Beta 3:
ROM rescan required (or new hrtmon/superiv config support won't work)
- confirmed A3000 3.1 ROM added to rom scan list.
- floppy drive sound GUI didn't work correctly if fdrawcmd.sys was
not installed (=no PC floppy drives listed)
-- A3000 36.141 KS ROM SCSI driver compatiblity fix (long word writes
+- A3000 36.141 KS ROM SCSI driver compatibility fix (long word writes
to byte wide WD33C93 registers.. not the first time Commodore ignored
their own programming guidelines.. )
- A3000 SuperKickstart support hack, SuperKickstart loading works!
#include "blkdev.h"
static int outcmd[] = { 0x0a, 0x2a, 0xaa, -1 };
-static int incmd[] = { 0x08, 0x12, 0x1a, 0x25, 0x28, 0xa8, 0x37, -1 };
+static int incmd[] = { 0x03, 0x08, 0x12, 0x1a, 0x25, 0x28, 0x37, 0x42, 0x43, 0xa8, -1 };
+static int nonecmd[] = { 0x00, 0x35, -1 };
int scsi_data_dir(struct scsi_data *sd)
{
return -1;
}
}
- return 0;
+ for (i = 0; nonecmd[i] >= 0; i++) {
+ if (cmd == nonecmd[i]) {
+ return 0;
+ }
+ }
+ write_log("SCSI command %02X, no direction specified (IN?)!\n", sd->cmd[0]);
+ return -2;
}
void scsi_emulate_cmd(struct scsi_data *sd)
int len = sd->buffer[4];
memset (sd->buffer, 0, len);
memcpy (sd->buffer, sd->sense, sd->sense_len > len ? len : sd->sense_len);
+ sd->data_len = len;
} else if (sd->nativescsiunit < 0) {
sd->status = scsi_emulate(&sd->hfd->hfd, sd->hfd,
sd->cmd, sd->len, sd->buffer, &sd->data_len, sd->reply, &sd->reply_len, sd->sense, &sd->sense_len);
}
} else {
struct amigascsi as;
+
+ memset(sd->sense, 0, 256);
memset(&as, 0, sizeof as);
memcpy (&as.cmd, sd->cmd, sd->len);
- as.flags = 2;
- if (sd->direction < 0)
- as.flags |= 1;
+ as.flags = 2 | 1;
+ if (sd->direction > 0)
+ as.flags &= ~1;
as.sense_len = 32;
as.cmd_len = sd->len;
as.data = sd->buffer;
- as.len = sd->direction < 0 ? 256 * 512 : sd->data_len;
+ as.len = sd->direction < 0 ? DEVICE_SCSI_BUFSIZE : sd->data_len;
sys_command_scsi_direct_native(sd->nativescsiunit, &as);
sd->status = as.status;
- memcpy(sd->sense, as.sensedata, as.sense_len);
+ sd->data_len = as.len;
+ if (sd->status) {
+ sd->direction = 0;
+ sd->data_len = 0;
+ memcpy(sd->sense, as.sensedata, as.sense_len);
+ }
}
sd->offset = 0;
}
static void io_log (char *msg, uaecptr request)
{
if (log_scsi)
- write_log ("%s: %08X %d %08.8X %d %d io_actual=%d io_error=%d\n",
+ write_log ("%s: %08X %d %08X %d %d io_actual=%d io_error=%d\n",
msg, request, get_word(request + 28), get_long(request + 40),
get_long(request + 36), get_long(request + 44),
get_long (request + 32), get_byte (request + 31));
int i;
if (log_scsi)
- write_log ("async request %p (%d) added\n", request, type);
+ write_log ("async request %08x (%d) added\n", request, type);
i = 0;
while (i < MAX_ASYNC_REQUESTS) {
if (dev->d_request[i] == request) {
projects / francis / winuae.git / commitdiff