THROW(2);
}
+#if HARDWARE_BUS_ERROR_EMULATION
static void mmu030_hardware_bus_error(uaecptr addr, uae_u32 v, bool read, int size, uae_u32 fc)
{
int flags = size == sz_byte ? MMU030_SSW_SIZE_B : (size == sz_word ? MMU030_SSW_SIZE_W : MMU030_SSW_SIZE_L);
} else {
flags |= MMU030_SSW_RW;
}
+ hardware_bus_error = 0;
mmu030_page_fault(addr, read, flags, fc);
-
}
+#endif
static void mmu030_add_data_read_cache(uaecptr addr, uaecptr phys, uae_u32 fc)
{
}
cacheablecheck(addr);
x_phys_put_long(addr,val);
-#if BUS_ERROR_EMULATION
- if (cpu_bus_error)
+#if HARDWARE_BUS_ERROR_EMULATION
+ if (hardware_bus_error)
mmu030_hardware_bus_error(addr, val, false, sz_long, fc);
#endif
}
}
cacheablecheck(addr);
x_phys_put_word(addr,val);
-#if BUS_ERROR_EMULATION
- if (cpu_bus_error)
+#if HARDWARE_BUS_ERROR_EMULATION
+ if (hardware_bus_error)
mmu030_hardware_bus_error(addr, val, false, sz_word, fc);
#endif
}
}
cacheablecheck(addr);
x_phys_put_byte(addr,val);
-#if BUS_ERROR_EMULATION
- if (cpu_bus_error)
+#if HARDWARE_BUS_ERROR_EMULATION
+ if (hardware_bus_error)
mmu030_hardware_bus_error(addr, val, false, sz_byte, fc);
#endif
}
}
cacheablecheck(addr);
uae_u32 v = x_phys_get_long(addr);
-#if BUS_ERROR_EMULATION
- if (cpu_bus_error)
+#if HARDWARE_BUS_ERROR_EMULATION
+ if (hardware_bus_error)
mmu030_hardware_bus_error(addr, v, true, sz_long, fc);
#endif
return v;
}
cacheablecheck(addr);
uae_u16 v = x_phys_get_word(addr);
-#if BUS_ERROR_EMULATION
- if (cpu_bus_error)
+#if HARDWARE_BUS_ERROR_EMULATION
+ if (hardware_bus_error)
mmu030_hardware_bus_error(addr, v, true, sz_word, fc);
#endif
return v;
}
cacheablecheck(addr);
uae_u8 v = x_phys_get_byte(addr);
-#if BUS_ERROR_EMULATION
- if (cpu_bus_error)
+#if HARDWARE_BUS_ERROR_EMULATION
+ if (hardware_bus_error)
mmu030_hardware_bus_error(addr, v, true, sz_byte, fc);
#endif
return v;
#else
mmu030_cache_state = mmu030.mmu030_cache_state;
v = x_phys_get_ilong(mmu030.mmu030_last_physical_address + (addr & mmu030.translation.page.mask));
-#if BUS_ERROR_EMULATION
- if (cpu_bus_error)
+#if HARDWARE_BUS_ERROR_EMULATION
+ if (hardware_bus_error)
mmu030_hardware_bus_error(addr, v, true, sz_long, fc);
#endif
return v;
}
cacheablecheck(addr);
v = x_phys_get_ilong(addr);
-#if BUS_ERROR_EMULATION
- if (cpu_bus_error)
+#if HARDWARE_BUS_ERROR_EMULATION
+ if (hardware_bus_error)
mmu030_hardware_bus_error(addr, v, true, sz_long, fc);
#endif
return v;
#else
mmu030_cache_state = mmu030.mmu030_cache_state;
v = x_phys_get_iword(mmu030.mmu030_last_physical_address + (addr & mmu030.translation.page.mask));
-#if BUS_ERROR_EMULATION
- if (cpu_bus_error)
+#if HARDWARE_BUS_ERROR_EMULATION
+ if (hardware_bus_error)
mmu030_hardware_bus_error(addr, v, true, sz_word, fc);
#endif
return v;
}
cacheablecheck(addr);
v = x_phys_get_iword(addr);
-#if BUS_ERROR_EMULATION
- if (cpu_bus_error)
+#if HARDWARE_BUS_ERROR_EMULATION
+ if (hardware_bus_error)
mmu030_hardware_bus_error(addr, v, true, sz_word, fc);
#endif
return v;
else
x_phys_put_long(addr, val);
-#if BUS_ERROR_EMULATION
- if (cpu_bus_error)
+#if HARDWARE_BUS_ERROR_EMULATION
+ if (hardware_bus_error)
mmu030_hardware_bus_error(addr, val, false, size, fc);
#endif
}
else
x_phys_put_long(addr, val);
-#if BUS_ERROR_EMULATION
- if (cpu_bus_error)
+#if HARDWARE_BUS_ERROR_EMULATION
+ if (hardware_bus_error)
mmu030_hardware_bus_error(addr, val, false, size, fc);
#endif
}
else
v = x_phys_get_long(addr);
-#if BUS_ERROR_EMULATION
- if (cpu_bus_error)
+#if HARDWARE_BUS_ERROR_EMULATION
+ if (hardware_bus_error)
mmu030_hardware_bus_error(addr, v, true, size, fc);
#endif
else
v = x_phys_get_long(addr);
-#if BUS_ERROR_EMULATION
- if (cpu_bus_error)
+#if HARDWARE_BUS_ERROR_EMULATION
+ if (hardware_bus_error)
mmu030_hardware_bus_error(addr, v, true, size, fc);
#endif
int movem_index2[256];
int movem_next[256];
int bus_error_offset;
-int cpu_bus_error, cpu_bus_error_fake;
+int hardware_bus_error, hardware_bus_error_fake;
struct mmufixup mmufixup[2];
cpuop_func *cpufunctbl[65536];
if (safe_memory_start == 0xffffffff && safe_memory_end == 0xffffffff)
return;
if (addr >= safe_memory_start && addr < safe_memory_end) {
- cpu_bus_error_fake = -1;
+ hardware_bus_error_fake = -1;
if ((safe_memory_mode & 4) && !write && (fc & 2)) {
- cpu_bus_error |= 4;
- cpu_bus_error_fake |= 1;
+ hardware_bus_error |= 4;
+ hardware_bus_error_fake |= 1;
} else if ((safe_memory_mode & 1) && !write && !(fc & 2)) {
- cpu_bus_error |= 1;
- cpu_bus_error_fake |= 1;
+ hardware_bus_error |= 1;
+ hardware_bus_error_fake |= 1;
} else if ((safe_memory_mode & 2) && write) {
- cpu_bus_error |= 2;
- cpu_bus_error_fake |= 2;
+ hardware_bus_error |= 2;
+ hardware_bus_error_fake |= 2;
}
if (!write && (fc & 2) && feature_usp == 3) {
out_of_test_space = true;
return;
check_bus_error(addr, 1, regs.s ? 5 : 1);
uae_u8 *p = get_addr(addr, 1, 1);
- if (!out_of_test_space && !noaccesshistory && !cpu_bus_error_fake) {
+ if (!out_of_test_space && !noaccesshistory && !hardware_bus_error_fake) {
previoussame(addr, sz_byte);
if (ahcnt_current >= MAX_ACCESSHIST) {
wprintf(_T(" ahist overflow!"));
put_byte_test(addr + 1, v >> 0);
} else {
uae_u8 *p = get_addr(addr, 2, 1);
- if (!out_of_test_space && !noaccesshistory && !cpu_bus_error_fake) {
+ if (!out_of_test_space && !noaccesshistory && !hardware_bus_error_fake) {
previoussame(addr, sz_word);
if (ahcnt_current >= MAX_ACCESSHIST) {
wprintf(_T(" ahist overflow!"));
put_word_test(addr + 2, v >> 0);
} else {
uae_u8 *p = get_addr(addr, 4, 1);
- if (!out_of_test_space && !noaccesshistory && !cpu_bus_error_fake) {
+ if (!out_of_test_space && !noaccesshistory && !hardware_bus_error_fake) {
previoussame(addr, sz_long);
if (ahcnt_current >= MAX_ACCESSHIST) {
wprintf(_T(" ahist overflow!"));
test_memory_accessed = 0;
testing_active = 1;
testing_active_opcode = opc;
- cpu_bus_error = 0;
- cpu_bus_error_fake = 0;
+ hardware_bus_error = 0;
+ hardware_bus_error_fake = 0;
read_buffer_prev = regs.ir;
regs.read_buffer = regs.irc;
regs.write_buffer = 0xf00d;
out_of_test_space = 0;
noaccesshistory = 0;
- cpu_bus_error_fake = 0;
- cpu_bus_error = 0;
+ hardware_bus_error_fake = 0;
+ hardware_bus_error = 0;
ahcnt_current = 0;
ahcnt_written = 0;
multi_mode = 0;
// if only testing read bus errors, skip tests that generated only writes and vice-versa
// skip also all tests don't generate any bus errors
- if ((cpu_bus_error == 0 && safe_memory_mode) ||
- ((cpu_bus_error & 4) && !(safe_memory_mode & 4)) ||
- ((cpu_bus_error & 1) && !(safe_memory_mode & 1)) ||
- ((cpu_bus_error & 2) && !(safe_memory_mode & 2))) {
+ if ((hardware_bus_error == 0 && safe_memory_mode) ||
+ ((hardware_bus_error & 4) && !(safe_memory_mode & 4)) ||
+ ((hardware_bus_error & 1) && !(safe_memory_mode & 1)) ||
+ ((hardware_bus_error & 2) && !(safe_memory_mode & 2))) {
skipped = 1;
}
// skip if feature_target_opcode_offset mode and non-prefetch bus error
- if (target_opcode_address != 0xffffffff && (cpu_bus_error & 3)) {
+ if (target_opcode_address != 0xffffffff && (hardware_bus_error & 3)) {
skipped = 1;
}
if (m->bus_error) {
if (((m->bus_error & 1) && (rwi & 1)) || ((m->bus_error & 4) && (rwi & 4)) || ((m->bus_error & 2) && (rwi & 2))) {
-#if BUS_ERROR_EMULATION
- cpu_bus_error = 1;
+#if HARDWARE_BUS_ERROR_EMULATION
+ hardware_bus_error = 1;
#else
exception2(addr, (rwi & 2) == 0, size, ((rwi & 4) ? 2 : 1) | (regs.s ? 4 : 0));
#endif
return;
if (bus_error_text[0]) {
- printf("\tif(cpu_bus_error) {\n");
+ printf("\tif(hardware_bus_error) {\n");
if (bus_error_code[0])
printf("%s", bus_error_code);
printf("%s", bus_error_text);
if ((!using_prefetch && !using_ce) || cpu_level >= 2) {
fc &= 7;
- printf("\tif(cpu_bus_error) {\n");
+ printf("\tif(hardware_bus_error) {\n");
if (write) {
printf("\t\texception2_write(opcode, %sa + %d, %d, %s, %d);\n",
name, offset, size, writevar,
uae_u32 extra = fc & 0xffff0000;
fc &= 0xffff;
- printf("\tif(cpu_bus_error) {\n");
+ printf("\tif(hardware_bus_error) {\n");
int setapdiback = 0;
headerfile = fopen("cputbl.h", "wb");
- fprintf(headerfile, "#define BUS_ERROR_EMULATION %d\n", using_bus_error);
+ fprintf(headerfile, "#define HARDWARE_BUS_ERROR_EMULATION %d\n", using_bus_error);
stblfile = fopen("cpustbl.cpp", "wb");
generate_includes(stblfile, 0);
#endif
extern int bus_error_offset;
-extern int cpu_bus_error;
+extern int hardware_bus_error;
typedef uae_u32 REGPARAM3 cpuop_func (uae_u32) REGPARAM;
typedef void REGPARAM3 cpuop_func_ce (uae_u32) REGPARAM;
int mmu_enabled, mmu_triggered;
int cpu_cycles;
int bus_error_offset;
-int cpu_bus_error;
+int hardware_bus_error;
static int baseclock;
int m68k_pc_indirect;
bool m68k_interrupt_delay;
regs.intmask = nr - 24;
branch_stack_push(currpc, currpc);
regs.ir = x_get_word (m68k_getpc ()); // prefetch 1
-#if BUS_ERROR_EMULATION
- if (cpu_bus_error) {
+#if HARDWARE_BUS_ERROR_EMULATION
+ if (hardware_bus_error) {
if (nr == 2 || nr == 3) {
cpu_halt(CPU_HALT_DOUBLE_FAULT);
return;
regs.ipl_pin = intlev();
ipl_fetch();
regs.irc = x_get_word (m68k_getpc () + 2); // prefetch 2
-#if BUS_ERROR_EMULATION
- if (cpu_bus_error) {
+#if HARDWARE_BUS_ERROR_EMULATION
+ if (hardware_bus_error) {
if (nr == 2 || nr == 3) {
cpu_halt(CPU_HALT_DOUBLE_FAULT);
return;
last_notinstruction_for_exception_3 = exception_in_exception != 0;
last_size_for_exception_3 = size;
last_di_for_exception_3 = 1;
- cpu_bus_error = 0;
+ hardware_bus_error = 0;
if (currprefs.cpu_model == 68000 && currprefs.cpu_compatible) {
if (generates_group1_exception(regs.ir) && !(opcode & 0x20000)) {