cdp->state = 1;
cdp->wlen = cdp->len;
/* there are too many stupid sound routines that fail on "too" fast cpus.. */
- if (currprefs.cpu_level > 1)
+ if (currprefs.cpu_model >= 68020)
cdp->pt = cdp->lc;
#ifdef DEBUG_AUDIO
if (debugchannel (nr))
static void REGPARAM3 rtarea_wput (uaecptr, uae_u32) REGPARAM;
static void REGPARAM3 rtarea_bput (uaecptr, uae_u32) REGPARAM;
static uae_u8 *REGPARAM3 rtarea_xlate (uaecptr) REGPARAM;
+static int REGPARAM3 rtarea_check (uaecptr addr, uae_u32 size) REGPARAM;
addrbank rtarea_bank = {
rtarea_lget, rtarea_wget, rtarea_bget,
rtarea_lput, rtarea_wput, rtarea_bput,
- rtarea_xlate, default_check, NULL, "UAE Boot ROM",
+ rtarea_xlate, rtarea_check, NULL, "UAE Boot ROM",
rtarea_lget, rtarea_wget, ABFLAG_ROMIN
};
return rtarea + addr;
}
+static int REGPARAM2 rtarea_check (uaecptr addr, uae_u32 size)
+{
+ addr &= 0xFFFF;
+ return (addr + size) <= 0xFFFF;
+}
+
static uae_u32 REGPARAM2 rtarea_lget (uaecptr addr)
{
#ifdef JIT
static int blit_cyclecounter, blit_maxcyclecounter, blit_slowdown;
static int blit_linecyclecounter, blit_misscyclecounter;
-#ifdef CPUEMU_6
+#ifdef CPUEMU_12
extern uae_u8 cycle_line[];
#endif
bltstate = BLT_read;
}
-#ifdef CPUEMU_6
+#ifdef CPUEMU_12
static int blit_last_hpos;
blitter_done ();
}
-#ifdef CPUEMU_6
+#ifdef CPUEMU_12
static uae_u32 preva, prevb;
STATIC_INLINE uae_u16 blitter_doblit (void)
*
*/
-//#define CDTV_DEBUG
-//#define CDTV_DEBUG_CMD
+#define CDTV_DEBUG
+#define CDTV_DEBUG_CMD
//#define CDTV_DEBUG_6525
#include "sysconfig.h"
static volatile uae_u8 cdtv_command_buf[6];
static volatile uae_u8 dmac_istr, dmac_cntr;
static volatile uae_u16 dmac_dawr;
-static volatile uae_u32 dmac_acr, dmac_wtc;
+static volatile uae_u32 dmac_acr;
+static volatile int dmac_wtc;
static volatile int dmac_dma;
static volatile int activate_stch, cdrom_command_done, play_state, play_statewait;
static int readsector;
uae_u8 *p = NULL;
-#ifdef CDTV_DEBUG
- write_log("DMAC DMA: sector=%d, cnt=%d, addr=%08.8X, %d\n",
- cdrom_sector, cdrom_sectors, dmac_acr, dmac_wtc);
-#endif
+ write_log("DMAC DMA: sector=%d, addr=%08.8X, words=%d\n",
+ cdrom_offset / 2048, dmac_acr, dmac_wtc);
dma_wait += dmac_wtc * 312 * 50 / 75 + 1;
while (dmac_wtc > 0 && dmac_dma) {
if (!p || readsector != (cdrom_offset / 2048)) {
{"use_gui", "Enable the GUI? If no, then goes straight to emulator" },
{"use_debugger", "Enable the debugger?" },
{"cpu_speed", "can be max, real, or a number between 1 and 20" },
- {"cpu_type", "Can be 68000, 68010, 68020, 68020/68881" },
+ {"cpu_model", "Can be 68000, 68010, 68020, 68030, 68040, 68060" },
+ {"fpu_model", "Can be 68881, 68882, 68040, 68060" },
{"cpu_compatible", "yes enables compatibility-mode" },
{"cpu_24bit_addressing", "must be set to 'no' in order for Z3mem or P96mem to work" },
{"autoconfig", "yes = add filesystems and extra ram" },
static const char *linemode1[] = { "none", "double", "scanlines", 0 };
static const char *linemode2[] = { "n", "d", "s", 0 };
static const char *speedmode[] = { "max", "real", 0 };
-static const char *cpumode[] = {
- "68000", "68000", "68010", "68010", "68ec020", "68020", "68ec020/68881", "68020/68881",
- "68040", "68040", "xxxxx", "xxxxx", "68060", "68060", 0
-};
static const char *colormode1[] = { "8bit", "15bit", "16bit", "8bit_dither", "4bit_dither", "32bit", 0 };
static const char *colormode2[] = { "8", "15", "16", "8d", "4d", "32", 0 };
static const char *soundmode1[] = { "none", "interrupts", "normal", "exact", 0 };
"-", "Generic", "CDTV", "CD32", "A500", "A500+", "A600",
"A1000", "A1200", "A2000", "A3000", "A3000T", "A4000", "A4000T", 0
};
-static const char *fullmodes[] = { "false", "true", "fullwindow", 0 };
+/* 3-state boolean! */
+static const char *fullmodes[] = { "false", "true", /* "FILE_NOT_FOUND", */ "fullwindow", 0 };
static const char *obsolete[] = {
"accuracy", "gfx_opengl", "gfx_32bit_blits", "32bit_blits",
}
}
+static void write_compatibility_cpu(struct zfile *f, struct uae_prefs *p)
+{
+ char tmp[100];
+ int model;
+
+ model = p->cpu_model;
+ if (model == 68030)
+ model = 68020;
+ if (model == 68060)
+ model = 68040;
+ if (p->address_space_24 && model == 68020)
+ strcpy (tmp, "68ec020");
+ else
+ sprintf(tmp, "%d", model);
+ if (model == 68020 && (p->fpu_model == 68881 || p->fpu_model == 68882))
+ strcat(tmp,"/68881");
+ cfgfile_write (f, "cpu_type=%s\n", tmp);
+}
void cfgfile_save_options (struct zfile *f, struct uae_prefs *p, int type)
{
else
cfgfile_write (f, "cpu_speed=%s\n", p->m68k_speed == -1 ? "max" : "real");
- cfgfile_write (f, "cpu_type=%s\n", cpumode[p->cpu_level * 2 + !p->address_space_24]);
+ /* do not reorder start */
+ write_compatibility_cpu(f, p);
+ cfgfile_write (f, "cpu_model=%d\n", p->cpu_model);
+ if (p->fpu_model)
+ cfgfile_write (f, "fpu_model=%d\n", p->fpu_model);
cfgfile_write (f, "cpu_compatible=%s\n", p->cpu_compatible ? "true" : "false");
+ cfgfile_write (f, "cpu_24bit_addressing=%s\n", p->address_space_24 ? "true" : "false");
+ /* do not reorder end */
cfgfile_write (f, "cpu_cycle_exact=%s\n", p->cpu_cycle_exact ? "true" : "false");
cfgfile_write (f, "blitter_cycle_exact=%s\n", p->blitter_cycle_exact ? "true" : "false");
cfgfile_write (f, "rtg_nocustom=%s\n", p->picasso96_nocustom ? "true" : "false");
if (cfgfile_yesno (option, value, "cpu_cycle_exact", &p->cpu_cycle_exact)
|| cfgfile_yesno (option, value, "blitter_cycle_exact", &p->blitter_cycle_exact)) {
- if (p->cpu_level > 1 && p->cachesize > 0)
+ if (p->cpu_model >= 68020 && p->cachesize > 0)
p->cpu_cycle_exact = p->blitter_cycle_exact = 0;
/* we don't want cycle-exact in 68020/40+JIT modes */
return 1;
return 1;
}
- if (cfgfile_strval (option, value, "cpu_type", &p->cpu_level, cpumode, 0)) {
- p->address_space_24 = p->cpu_level < 8 && !(p->cpu_level & 1);
- p->cpu_level >>= 1;
+ if (cfgfile_string (option, value, "fpu_model", tmpbuf, sizeof tmpbuf)) {
+ p->fpu_model = atol(tmpbuf);
+ return 1;
+ }
+
+ if (cfgfile_string (option, value, "cpu_model", tmpbuf, sizeof tmpbuf)) {
+ p->cpu_model = atol(tmpbuf);
+ p->fpu_model = 0;
return 1;
}
+
+ /* old-style CPU configuration */
+ if (cfgfile_string (option, value, "cpu_type", tmpbuf, sizeof tmpbuf)) {
+ p->fpu_model = 0;
+ p->address_space_24 = 0;
+ p->cpu_model = 680000;
+ if (!strcmp(tmpbuf, "68000")) {
+ p->cpu_model = 68000;
+ } else if (!strcmp(tmpbuf, "68010")) {
+ p->cpu_model = 68010;
+ } else if (!strcmp(tmpbuf, "68ec020")) {
+ p->cpu_model = 68020;
+ p->address_space_24 = 1;
+ } else if (!strcmp(tmpbuf, "68020")) {
+ p->cpu_model = 68020;
+ } else if (!strcmp(tmpbuf, "68ec020/68881")) {
+ p->cpu_model = 68020;
+ p->fpu_model = 68881;
+ p->address_space_24 = 1;
+ } else if (!strcmp(tmpbuf, "68020/68881")) {
+ p->cpu_model = 68020;
+ p->fpu_model = 68881;
+ } else if (!strcmp(tmpbuf, "68040")) {
+ p->cpu_model = 68040;
+ p->fpu_model = 68040;
+ } else if (!strcmp(tmpbuf, "68060")) {
+ p->cpu_model = 68060;
+ p->fpu_model = 68060;
+ }
+ return 1;
+ }
+
if (p->config_version < (21 << 16)) {
if (cfgfile_strval (option, value, "cpu_speed", &p->m68k_speed, speedmode, 1)
/* Broken earlier versions used to write this out as a string. */
return;
}
- p->cpu_level = *spec++ - '0';
- p->address_space_24 = p->cpu_level < 2;
+ p->cpu_model = (*spec++) * 10 + 68000;
+ p->address_space_24 = p->cpu_model < 68020;
p->cpu_compatible = 0;
while (*spec != '\0') {
switch (*spec) {
case 'a':
- if (p->cpu_level < 2)
+ if (p->cpu_model < 68020)
write_log ("In 68000/68010 emulation, the address space is always 24 bit.\n");
- else if (p->cpu_level >= 4)
+ else if (p->cpu_model >= 68040)
write_log ("In 68040/060 emulation, the address space is always 32 bit.\n");
else
p->address_space_24 = 1;
break;
case 'c':
- if (p->cpu_level != 0)
+ if (p->cpu_model != 68000)
write_log ("The more compatible CPU emulation is only available for 68000\n"
"emulation, not for 68010 upwards.\n");
else
p->nr_floppies = 1;
p->dfxtype[0] = DRV_35_DD;
p->dfxtype[1] = DRV_NONE;
- p->cpu_level = 0;
+ p->cpu_model = 68000;
p->address_space_24 = 1;
p->chipmem_size = 0x00080000;
p->bogomem_size = 0x00080000;
p->prtname[0] = 0;
p->sername[0] = 0;
- p->cpu_level = 0;
+ p->fpu_model = 0;
+ p->cpu_model = 68000;
p->m68k_speed = 0;
p->cpu_compatible = 1;
p->address_space_24 = 1;
static void buildin_default_prefs_68020 (struct uae_prefs *p)
{
- p->cpu_level = 2;
+ p->cpu_model = 68020;
+ p->address_space_24 = 1;
p->cpu_compatible = 1;
p->chipset_mask = CSMASK_ECS_AGNUS | CSMASK_ECS_DENISE | CSMASK_AGA;
p->chipmem_size = 0x200000;
p->dfxtype[3] = DRV_NONE;
p->floppy_speed = 100;
- p->cpu_level = 0;
+ p->fpu_model = 0;
+ p->cpu_model = 68000;
p->m68k_speed = 0;
p->cpu_compatible = 1;
p->address_space_24 = 1;
p->chipmem_size = 0x400000;
p->z3fastmem_size = 8 * 1024 * 1024;
p->gfxmem_size = 8 * 1024 * 1024;
- p->cpu_level = 4;
+ p->cpu_model = 68060;
+ p->fpu_model = 68060;
p->chipset_mask = CSMASK_AGA | CSMASK_ECS_AGNUS | CSMASK_ECS_DENISE;
p->cpu_compatible = p->address_space_24 = 0;
p->m68k_speed = -1;
v = (addr & 1) ? ReadCIAA (r) : 0xff;
break;
case 3:
- if (currprefs.cpu_level == 0 && currprefs.cpu_compatible)
+ if (currprefs.cpu_model == 68000 && currprefs.cpu_compatible)
v = (addr & 1) ? regs.irc : regs.irc >> 8;
if (warned > 0) {
write_log ("cia_bget: unknown CIA address %x PC=%x\n", addr, M68K_GETPC);
v = (0xff << 8) | ReadCIAA (r);
break;
case 3:
- if (currprefs.cpu_level == 0 && currprefs.cpu_compatible)
+ if (currprefs.cpu_model == 68000 && currprefs.cpu_compatible)
v = regs.irc;
if (warned > 0) {
write_log ("cia_wget: unknown CIA address %x PC=%x\n", addr, M68K_GETPC);
static uae_u32 REGPARAM2 cia_wgeti (uaecptr addr)
{
- if (currprefs.cpu_level >= 2)
+ if (currprefs.cpu_model >= 68020)
return dummy_wgeti(addr);
return cia_wget(addr);
}
static uae_u32 REGPARAM2 cia_lgeti (uaecptr addr)
{
- if (currprefs.cpu_level >= 2)
+ if (currprefs.cpu_model >= 68020)
return dummy_lgeti(addr);
return cia_lget(addr);
}
addr &= 0x3f;
if ((addr & 3) == 2 || (addr & 3) == 0) {
int v = 0;
- if (currprefs.cpu_level == 0 && currprefs.cpu_compatible)
+ if (currprefs.cpu_model == 68000 && currprefs.cpu_compatible)
v = regs.irc >> 8;
return v;
}
*/
void comp_fsave_opp (uae_u32 opcode)
{
- uae_u32 ad;
- int incr = (opcode & 0x38) == 0x20 ? -1 : 1;
- int i;
-
FAIL(1);
return;
-
- if (!currprefs.compfpu) {
- FAIL(1);
- return;
- }
-
-#if DEBUG_FPP
- write_log ("JIT: fsave_opp at %08lx\n", M68K_GETPC);
-#endif
- if (!comp_fp_adr (opcode)) {
- m68k_setpc (®s, m68k_getpc (®s) - 2);
- op_illg (opcode, ®s);
- return;
- }
-
- if (currprefs.cpu_level >= 4) {
- /* 4 byte 68040 IDLE frame. */
- if (incr < 0) {
- ad -= 4;
- put_long (ad, 0x41000000);
- } else {
- put_long (ad, 0x41000000);
- ad += 4;
- }
- } else {
- if (incr < 0) {
- ad -= 4;
- put_long (ad, 0x70000000);
- for (i = 0; i < 5; i++) {
- ad -= 4;
- put_long (ad, 0x00000000);
- }
- ad -= 4;
- put_long (ad, 0x1f180000);
- } else {
- put_long (ad, 0x1f180000);
- ad += 4;
- for (i = 0; i < 5; i++) {
- put_long (ad, 0x00000000);
- ad += 4;
- }
- put_long (ad, 0x70000000);
- ad += 4;
- }
- }
- if ((opcode & 0x38) == 0x18)
- m68k_areg (®s, opcode & 7) = ad;
- if ((opcode & 0x38) == 0x20)
- m68k_areg (®s, opcode & 7) = ad;
}
void comp_frestore_opp (uae_u32 opcode)
{
- uae_u32 ad;
- uae_u32 d;
- int incr = (opcode & 0x38) == 0x20 ? -1 : 1;
-
FAIL(1);
return;
-
- if (!currprefs.compfpu) {
- FAIL(1);
- return;
- }
-
-#if DEBUG_FPP
- write_log ("frestore_opp at %08lx\n", M68K_GETPC);
-#endif
- if (!comp_fp_adr (opcode)) {
- m68k_setpc (®s, m68k_getpc (®s) - 2);
- op_illg (opcode, ®s);
- return;
- }
- if (currprefs.cpu_level >= 4) {
- /* 68040 */
- if (incr < 0) {
- /* @@@ This may be wrong. */
- ad -= 4;
- d = get_long (ad);
- if (d & 0xff000000) { /* Not a NULL frame? */
- if (!(d & 0x00ff0000)) { /* IDLE */
- } else if ((d & 0x00ff0000) == 0x00300000) { /* UNIMP */
- ad -= 44;
- } else if ((d & 0x00ff0000) == 0x00600000) { /* BUSY */
- ad -= 92;
- }
- }
- } else {
- d = get_long (ad);
- ad += 4;
- if (d & 0xff000000) { /* Not a NULL frame? */
- if (!(d & 0x00ff0000)) { /* IDLE */
- } else if ((d & 0x00ff0000) == 0x00300000) { /* UNIMP */
- ad += 44;
- } else if ((d & 0x00ff0000) == 0x00600000) { /* BUSY */
- ad += 92;
- }
- }
- }
- } else {
- if (incr < 0) {
- ad -= 4;
- d = get_long (ad);
- if (d & 0xff000000) {
- if ((d & 0x00ff0000) == 0x00180000)
- ad -= 6 * 4;
- else if ((d & 0x00ff0000) == 0x00380000)
- ad -= 14 * 4;
- else if ((d & 0x00ff0000) == 0x00b40000)
- ad -= 45 * 4;
- }
- } else {
- d = get_long (ad);
- ad += 4;
- if (d & 0xff000000) {
- if ((d & 0x00ff0000) == 0x00180000)
- ad += 6 * 4;
- else if ((d & 0x00ff0000) == 0x00380000)
- ad += 14 * 4;
- else if ((d & 0x00ff0000) == 0x00b40000)
- ad += 45 * 4;
- }
- }
- }
- if ((opcode & 0x38) == 0x18)
- m68k_areg (®s, opcode & 7) = ad;
- if ((opcode & 0x38) == 0x20)
- m68k_areg (®s, opcode & 7) = ad;
}
extern uae_u32 xhex_pi[], xhex_exp_1[], xhex_l2_e[], xhex_ln_2[], xhex_ln_10[];
const struct comptbl* nftbl=op_smalltbl_0_comp_nf;
int count;
#ifdef NOFLAGS_SUPPORT
- struct comptbl *nfctbl = (currprefs.cpu_level >= 4 ? op_smalltbl_0_nf
- : currprefs.cpu_level == 3 ? op_smalltbl_1_nf
- : currprefs.cpu_level == 2 ? op_smalltbl_2_nf
+ struct comptbl *nfctbl = (currprefs.cpu_level >= 5 ? op_smalltbl_0_nf
+ : currprefs.cpu_level == 4 ? op_smalltbl_1_nf
+ : (currprefs.cpu_level == 2 || currprefs.cpu_level == 3) ? op_smalltbl_2_nf
: currprefs.cpu_level == 1 ? op_smalltbl_3_nf
: ! currprefs.cpu_compatible ? op_smalltbl_4_nf
: op_smalltbl_5_nf);
static int last_sprite_point, nr_armed;
static int sprite_width, sprres, sprite_buffer_res;
-#ifdef CPUEMU_6
+#ifdef CPUEMU_12
uae_u8 cycle_line[256];
#endif
static int max_color_change = 400;
static int delta_color_change = 0;
#else
-struct sprite_entry sprite_entries[2][MAX_SPR_PIXELS / 16];
-struct color_change color_changes[2][MAX_REG_CHANGE];
+static struct sprite_entry sprite_entries[2][MAX_SPR_PIXELS / 16];
+static struct color_change color_changes[2][MAX_REG_CHANGE];
#endif
struct decision line_decisions[2 * (MAXVPOS + 1) + 1];
-struct draw_info line_drawinfo[2][2 * (MAXVPOS + 1) + 1];
-struct color_entry color_tables[2][(MAXVPOS + 1) * 2];
+static struct draw_info line_drawinfo[2][2 * (MAXVPOS + 1) + 1];
+static struct color_entry color_tables[2][(MAXVPOS + 1) * 2];
static int next_sprite_entry = 0;
static int prev_next_sprite_entry;
docols(¤t_colors);
/* docols(&colors_for_drawing);*/
- for (i = 0; i < (MAXVPOS + 1)*2; i++) {
- docols(color_tables[0]+i);
- docols(color_tables[1]+i);
+ for (i = 0; i < (MAXVPOS + 1) * 2; i++) {
+ docols(color_tables[0] + i);
+ docols(color_tables[1] + i);
}
}
#if 0
write_log ("vposr %x at %x\n", vp, m68k_getpc(®s));
#endif
- if (currprefs.cpu_level >= 2)
+ if (currprefs.cpu_model >= 68020)
hsyncdelay();
return vp;
}
uae_u16 hp = GETHPOS();
vp <<= 8;
vp |= hp;
- if (currprefs.cpu_level >= 2)
+ if (currprefs.cpu_model >= 68020)
hsyncdelay();
return vp;
}
if (copper_cant_read (old_hpos))
continue;
cop_state.i1 = chipmem_agnus_wget (cop_state.ip);
-#ifdef CPUEMU_6
+#ifdef CPUEMU_12
cycle_line[old_hpos] |= CYCLE_COPPER;
#endif
cop_state.ip += 2;
if (copper_cant_read (old_hpos))
continue;
cop_state.i2 = chipmem_agnus_wget (cop_state.ip);
-#ifdef CPUEMU_6
+#ifdef CPUEMU_12
cycle_line[old_hpos] |= CYCLE_COPPER;
#endif
cop_state.ip += 2;
uae_u16 data = last_custom_value;
if (dma) {
data = last_custom_value = chipmem_agnus_wget (s->pt);
-#ifdef CPUEMU_6
+#ifdef CPUEMU_12
cycle_line[hpos] |= CYCLE_SPRITE;
#endif
}
#ifdef CDTV
CDTV_hsync_handler ();
#endif
-#ifdef CPUEMU_6
+#ifdef CPUEMU_12
if (currprefs.cpu_cycle_exact || currprefs.blitter_cycle_exact) {
decide_blitter (hpos);
memset (cycle_line, 0, sizeof cycle_line);
static uae_u32 REGPARAM2 custom_wgeti (uaecptr addr)
{
- if (currprefs.cpu_level >= 2)
+ if (currprefs.cpu_model >= 68020)
return dummy_wgeti(addr);
return custom_wget(addr);
}
static uae_u32 REGPARAM2 custom_lgeti (uaecptr addr)
{
- if (currprefs.cpu_level >= 2)
+ if (currprefs.cpu_model >= 68020)
return dummy_lgeti(addr);
return custom_lget(addr);
}
#endif
}
-#ifdef CPUEMU_6
+#ifdef CPUEMU_12
STATIC_INLINE void sync_copper (int hpos)
{
return 0;
if (!ab->check (addr, size))
return 0;
- if (ab->flags == ABFLAG_RAM || ab->flags == ABFLAG_ROM)
+ if (ab->flags == ABFLAG_RAM || ab->flags == ABFLAG_ROM || ab->flags == ABFLAG_ROMIN)
return 1;
return 0;
}
}
if ((hitpc & 0xFFF80000) == 0xF80000)
return;
- if (currprefs.cpu_level == 0 && currprefs.cpu_compatible) {
+ if (currprefs.cpu_model == 68000 && currprefs.cpu_compatible) {
/* ignore single-word unconditional jump instructions
* (instruction prefetch from PC+2 can cause false positives) */
if (regs.irc == 0x4e75 || regs.irc == 4e74 || regs.irc == 0x4e72 || regs.irc == 4e77)
m68k_dumpstate (stdout, &nextpc);
nxdis = nextpc; nxmem = 0;
+ debugger_active = 1;
for (;;) {
char cmd, *inptr;
regs.t0 = regs.t1 = 0;
if (!regs.s) {
regs.usp = m68k_areg(®s, 7);
- if (currprefs.cpu_level >= 2)
+ if (currprefs.cpu_model >= 68020)
m68k_areg(®s, 7) = regs.m ? regs.msp : regs.isp;
else
m68k_areg(®s, 7) = regs.isp;
m68k_setpc (®s, mmu_callback);
fill_prefetch_slow (®s);
- if (currprefs.cpu_level > 0) {
+ if (currprefs.cpu_model > 68000) {
for (i = 0 ; i < 9; i++) {
m68k_areg(®s, 7) -= 4;
put_long (m68k_areg(®s, 7), 0);
#endif
if (disk_debug_logging > 1)
write_log (" ->motor off");
- if (currprefs.cpu_level <= 1 && currprefs.m68k_speed == 0) {
+ if (currprefs.cpu_model <= 68010 && currprefs.m68k_speed == 0) {
drv->motordelay = 1;
event2_newevent2(30, drv - floppy, motordelay_func);
}
dh = dh_line;
xlinebuffer = gfxvidinfo.linemem;
if (xlinebuffer == 0 && do_double
- && (border == 0 || (border != 1 && dip_for_drawing->nr_color_changes > 0)))
+ && (border == 0 || dip_for_drawing->nr_color_changes > 0))
xlinebuffer = gfxvidinfo.emergmem, dh = dh_emerg;
if (xlinebuffer == 0)
xlinebuffer = row_map[gfx_ypos], dh = dh_buf;
; 200?.??.?? Picasso96 vblank hack (TW)
; 2006.03.04 Mousehack code integrated (TW)
; 2006.18.07 FileSystem.resource find routine access fault fixed (TW)
+; 2007.03.30 mousehack do not start multiple times anymore (TW)
AllocMem = -198
FreeMem = -210
exter_data:
exter_server:
movem.l a2,-(sp)
- move.w #$FF50,d0
+ move.w #$FF50,d0 ; exter_int_helper
bsr.w getrtbase
moveq.l #0,d0
jsr (a0)
; This is the hard part - we have to send some messages.
move.l 4.w,a6
EXTS_loop:
- move.w #$FF50,d0 ;exter_int_helper
+ move.w #$FF50,d0 ; exter_int_helper
bsr.w getrtbase
moveq.l #2,d0
jsr (a0)
FSML_loop:
bsr.w mousehack_init
+
move.l a5,a0
jsr -384(a6) ; WaitPort
+
move.l a5,a0
jsr -372(a6) ; GetMsg
move.l d0,a4
move.l (a2),a0
FSML_check_old:
move.l a0,d0
- beq.b FSML_loop
+ beq.w FSML_loop
move.l (a0),a1
move.l d0,a0
; This field may be accessed concurrently by several UAE threads.
FSML_DoCommand:
bsr.b LockCheck ; Make sure there are enough locks for the C code to grab.
- move.w #$FF30,d0
+ move.w #$FF30,d0 ; filesys_handler
bsr.w getrtbase
jsr (a0)
tst.l d0
tst.b 157(a3)
bne.s .no
lea mousehack_e(pc),a0
- tst.w (a0)
- beq.s .no
+ cmp.b #1,(a0)
+ bne.s .no
lea mhname(pc),a0
lea mousehack_task(pc),a1
bsr createtask
st 157(a3)
+ ;tell native side that mousehack is active
+ move.w #$FF38,d0
+ bsr.w getrtbase
+ jsr (a0)
.no move.l (sp)+,a0
rts
return type;
}
+static uae_u32 REGPARAM2 mousehack_done (TrapContext *context)
+{
+ /* do not allow other fs threads to start another mousehack */
+ rtarea[get_long (RTAREA_BASE + 40) + 12 - 2] = 0xff;
+ return 1;
+}
+
void filesys_install (void)
{
uaecptr loop;
calltrap (deftrap2 (filesys_handler, 0, "filesys_handler"));
dw (RTS);
+ org (RTAREA_BASE + 0xFF38);
+ calltrap (deftrap2 (mousehack_done, 0, "mousehack_done"));
+ dw (RTS);
+
org (RTAREA_BASE + 0xFF40);
calltrap (deftrap2 (startup_handler, 0, "startup_handler"));
dw (RTS);
db(0x00); db(0x00); db(0x00); db(0x34); db(0x00); db(0x00); db(0x00); db(0xd4);
db(0x00); db(0x00); db(0x00); db(0x20); db(0x00); db(0x00); db(0x01); db(0x8e);
db(0x00); db(0x00); db(0x06); db(0xb8); db(0x00); db(0x00); db(0x07); db(0xdc);
- db(0x43); db(0xfa); db(0x09); db(0xa8); db(0x4e); db(0xae); db(0xff); db(0xa0);
+ db(0x43); db(0xfa); db(0x09); db(0xb4); db(0x4e); db(0xae); db(0xff); db(0xa0);
db(0x20); db(0x40); db(0x20); db(0x28); db(0x00); db(0x16); db(0x20); db(0x40);
db(0x4e); db(0x90); db(0x4e); db(0x75); db(0x48); db(0xe7); db(0xff); db(0xfe);
db(0x2c); db(0x78); db(0x00); db(0x04); db(0x30); db(0x3c); db(0xff); db(0xfc);
db(0x61); db(0x00); db(0x06); db(0x66); db(0x2a); db(0x50); db(0x43); db(0xfa);
- db(0x09); db(0xa0); db(0x70); db(0x24); db(0x7a); db(0x00); db(0x4e); db(0xae);
+ db(0x09); db(0xac); db(0x70); db(0x24); db(0x7a); db(0x00); db(0x4e); db(0xae);
db(0xfd); db(0xd8); db(0x4a); db(0x80); db(0x66); db(0x0c); db(0x43); db(0xfa);
- db(0x09); db(0x90); db(0x70); db(0x00); db(0x7a); db(0x01); db(0x4e); db(0xae);
+ db(0x09); db(0x9c); db(0x70); db(0x00); db(0x7a); db(0x01); db(0x4e); db(0xae);
db(0xfd); db(0xd8); db(0x28); db(0x40); db(0x20); db(0x3c); db(0x00); db(0x00);
db(0x02); db(0x2c); db(0x72); db(0x01); db(0x4e); db(0xae); db(0xff); db(0x3a);
db(0x26); db(0x40); db(0x27); db(0x4c); db(0x01); db(0x9c); db(0x7c); db(0x00);
db(0x4c); db(0xdf); db(0x04); db(0x00); db(0x4e); db(0x75); db(0x48); db(0xe7);
db(0xc0); db(0xc0); db(0x70); db(0x1a); db(0x22); db(0x3c); db(0x00); db(0x01);
db(0x00); db(0x01); db(0x4e); db(0xae); db(0xff); db(0x3a); db(0x22); db(0x40);
- db(0x41); db(0xfa); db(0x08); db(0x19); db(0x23); db(0x48); db(0x00); db(0x0a);
+ db(0x41); db(0xfa); db(0x08); db(0x25); db(0x23); db(0x48); db(0x00); db(0x0a);
db(0x41); db(0xfa); db(0xff); db(0x2a); db(0x23); db(0x48); db(0x00); db(0x0e);
db(0x41); db(0xfa); db(0xff); db(0x22); db(0x23); db(0x48); db(0x00); db(0x12);
db(0x33); db(0x7c); db(0x02); db(0x14); db(0x00); db(0x08); db(0x70); db(0x03);
db(0x00); db(0x00); db(0x00); db(0x0e); db(0x52); db(0x40); db(0x0c); db(0x40);
db(0x00); db(0x8c); db(0x66); db(0xf2); db(0x20); db(0x0a); db(0xe4); db(0x88);
db(0x21); db(0x40); db(0x00); db(0x36); db(0x22); db(0x48); db(0x41); db(0xfa);
- db(0x07); db(0xb3); db(0x23); db(0x48); db(0x00); db(0x0a); db(0x20); db(0x6b);
+ db(0x07); db(0xbf); db(0x23); db(0x48); db(0x00); db(0x0a); db(0x20); db(0x6b);
db(0x01); db(0x98); db(0x41); db(0xe8); db(0x00); db(0x12); db(0x4e); db(0xae);
db(0xff); db(0x10); db(0x4c); db(0xdf); db(0x4f); db(0x03); db(0x4e); db(0x75);
db(0x48); db(0xe7); db(0x7f); db(0x7e); db(0x2c); db(0x78); db(0x00); db(0x04);
db(0x60); db(0xd4); db(0x48); db(0xe7); db(0x40); db(0xe2); db(0x2c); db(0x78);
db(0x00); db(0x04); db(0x41); db(0xee); db(0x01); db(0x50); db(0x20); db(0x50);
db(0x4a); db(0x90); db(0x67); db(0x1a); db(0x22); db(0x68); db(0x00); db(0x0a);
- db(0x45); db(0xfa); db(0x06); db(0xa0); db(0x10); db(0x19); db(0x12); db(0x1a);
+ db(0x45); db(0xfa); db(0x06); db(0xac); db(0x10); db(0x19); db(0x12); db(0x1a);
db(0xb0); db(0x01); db(0x66); db(0x06); db(0x4a); db(0x00); db(0x67); db(0x42);
db(0x60); db(0xf2); db(0x20); db(0x50); db(0x60); db(0xe2); db(0x70); db(0x20);
db(0x22); db(0x3c); db(0x00); db(0x01); db(0x00); db(0x01); db(0x4e); db(0xae);
db(0xff); db(0x3a); db(0x24); db(0x40); db(0x15); db(0x7c); db(0x00); db(0x08);
- db(0x00); db(0x08); db(0x41); db(0xfa); db(0x06); db(0x76); db(0x25); db(0x48);
- db(0x00); db(0x0a); db(0x41); db(0xfa); db(0x06); db(0x2f); db(0x25); db(0x48);
+ db(0x00); db(0x08); db(0x41); db(0xfa); db(0x06); db(0x82); db(0x25); db(0x48);
+ db(0x00); db(0x0a); db(0x41); db(0xfa); db(0x06); db(0x3b); db(0x25); db(0x48);
db(0x00); db(0x0e); db(0x41); db(0xea); db(0x00); db(0x12); db(0x20); db(0x88);
db(0x58); db(0x90); db(0x21); db(0x48); db(0x00); db(0x08); db(0x41); db(0xee);
db(0x01); db(0x50); db(0x22); db(0x4a); db(0x4e); db(0xae); db(0xff); db(0x0a);
db(0x70); db(0xff); db(0x2c); db(0x4c); db(0x4e); db(0xee); db(0xff); db(0x6a);
db(0x2c); db(0x78); db(0x00); db(0x04); db(0x70); db(0x00); db(0x22); db(0x40);
db(0x4e); db(0xae); db(0xfe); db(0xda); db(0x20); db(0x40); db(0x4b); db(0xe8);
- db(0x00); db(0x5c); db(0x43); db(0xfa); db(0x04); db(0xbe); db(0x70); db(0x00);
+ db(0x00); db(0x5c); db(0x43); db(0xfa); db(0x04); db(0xca); db(0x70); db(0x00);
db(0x4e); db(0xae); db(0xfd); db(0xd8); db(0x24); db(0x40); db(0x20); db(0x3c);
db(0x00); db(0x00); db(0x00); db(0x9e); db(0x22); db(0x3c); db(0x00); db(0x01);
db(0x00); db(0x01); db(0x4e); db(0xae); db(0xff); db(0x3a); db(0x26); db(0x40);
db(0x00); db(0x36); db(0x22); db(0x4a); db(0x24); db(0x43); db(0x97); db(0xcb);
db(0x4e); db(0xae); db(0xfe); db(0xe6); db(0x4c); db(0xdf); db(0x4c); db(0x0c);
db(0x4e); db(0x75); db(0x00); db(0x00); db(0x00); db(0x00); db(0x00); db(0x00);
- db(0x2f); db(0x08); db(0x4a); db(0x2b); db(0x00); db(0x9d); db(0x66); db(0x18);
- db(0x41); db(0xfa); db(0xff); db(0xf0); db(0x4a); db(0x50); db(0x67); db(0x10);
- db(0x41); db(0xfa); db(0x01); db(0xba); db(0x43); db(0xfa); db(0x00); db(0x0e);
- db(0x61); db(0x00); db(0xff); db(0x8c); db(0x50); db(0xeb); db(0x00); db(0x9d);
- db(0x20); db(0x5f); db(0x4e); db(0x75); db(0x2c); db(0x79); db(0x00); db(0x00);
- db(0x00); db(0x04); db(0x70); db(0xff); db(0x4e); db(0xae); db(0xfe); db(0xb6);
- db(0x74); db(0x00); db(0x01); db(0xc2); db(0x93); db(0xc9); db(0x4e); db(0xae);
- db(0xfe); db(0xda); db(0x28); db(0x40); db(0x70); db(0x14); db(0x22); db(0x4c);
- db(0x4e); db(0xae); db(0xfe); db(0xd4); db(0x70); db(0x00); db(0x43); db(0xfa);
- db(0x01); db(0xae); db(0x4e); db(0xae); db(0xfd); db(0xd8); db(0x2e); db(0x00);
- db(0x70); db(0x00); db(0x30); db(0x3c); db(0x00); db(0x44); db(0x22); db(0x3c);
- db(0x00); db(0x01); db(0x00); db(0x01); db(0x4e); db(0xae); db(0xff); db(0x3a);
- db(0x2a); db(0x40); db(0x61); db(0x00); db(0xfe); db(0xbe); db(0x61); db(0x00);
- db(0xff); db(0x0a); db(0x2b); db(0x40); db(0x00); db(0x3c); db(0x67); db(0x00);
- db(0x00); db(0x7a); db(0x22); db(0x40); db(0x41); db(0xfa); db(0x01); db(0x3c);
- db(0x70); db(0x00); db(0x72); db(0x00); db(0x4e); db(0xae); db(0xfe); db(0x44);
- db(0x4a); db(0x80); db(0x66); db(0x00); db(0x00); db(0x66); db(0x61); db(0x00);
- db(0xfe); db(0x9a); db(0x61); db(0x00); db(0xfe); db(0xe6); db(0x2b); db(0x40);
- db(0x00); db(0x40); db(0x67); db(0x00); db(0x00); db(0x56); db(0x22); db(0x40);
- db(0x41); db(0xfa); db(0x01); db(0x25); db(0x70); db(0x00); db(0x72); db(0x00);
+ db(0x2f); db(0x08); db(0x4a); db(0x2b); db(0x00); db(0x9d); db(0x66); db(0x24);
+ db(0x41); db(0xfa); db(0xff); db(0xf0); db(0x0c); db(0x10); db(0x00); db(0x01);
+ db(0x66); db(0x1a); db(0x41); db(0xfa); db(0x01); db(0xc4); db(0x43); db(0xfa);
+ db(0x00); db(0x18); db(0x61); db(0x00); db(0xff); db(0x8a); db(0x50); db(0xeb);
+ db(0x00); db(0x9d); db(0x30); db(0x3c); db(0xff); db(0x38); db(0x61); db(0x00);
+ db(0xfe); db(0xa0); db(0x4e); db(0x90); db(0x20); db(0x5f); db(0x4e); db(0x75);
+ db(0x2c); db(0x79); db(0x00); db(0x00); db(0x00); db(0x04); db(0x70); db(0xff);
+ db(0x4e); db(0xae); db(0xfe); db(0xb6); db(0x74); db(0x00); db(0x01); db(0xc2);
+ db(0x93); db(0xc9); db(0x4e); db(0xae); db(0xfe); db(0xda); db(0x28); db(0x40);
+ db(0x70); db(0x14); db(0x22); db(0x4c); db(0x4e); db(0xae); db(0xfe); db(0xd4);
+ db(0x70); db(0x00); db(0x43); db(0xfa); db(0x01); db(0xae); db(0x4e); db(0xae);
+ db(0xfd); db(0xd8); db(0x2e); db(0x00); db(0x70); db(0x00); db(0x30); db(0x3c);
+ db(0x00); db(0x44); db(0x22); db(0x3c); db(0x00); db(0x01); db(0x00); db(0x01);
+ db(0x4e); db(0xae); db(0xff); db(0x3a); db(0x2a); db(0x40); db(0x61); db(0x00);
+ db(0xfe); db(0xb2); db(0x61); db(0x00); db(0xfe); db(0xfe); db(0x2b); db(0x40);
+ db(0x00); db(0x3c); db(0x67); db(0x00); db(0x00); db(0x7a); db(0x22); db(0x40);
+ db(0x41); db(0xfa); db(0x01); db(0x3c); db(0x70); db(0x00); db(0x72); db(0x00);
db(0x4e); db(0xae); db(0xfe); db(0x44); db(0x4a); db(0x80); db(0x66); db(0x00);
- db(0x00); db(0x42); db(0x47); db(0xed); db(0x00); db(0x16); db(0x27); db(0x4c);
- db(0x00); db(0x0c); db(0x27); db(0x42); db(0x00); db(0x08); db(0x70); db(0xff);
- db(0x26); db(0x80); db(0x27); db(0x40); db(0x00); db(0x04); db(0x43); db(0xed);
- db(0x00); db(0x00); db(0x13); db(0x7c); db(0x00); db(0x02); db(0x00); db(0x08);
- db(0x13); db(0x7c); db(0x00); db(0x05); db(0x00); db(0x09); db(0x41); db(0xfa);
- db(0x00); db(0xfc); db(0x23); db(0x48); db(0x00); db(0x0a); db(0x41); db(0xfa);
- db(0x00); db(0xa0); db(0x23); db(0x48); db(0x00); db(0x12); db(0x23); db(0x4b);
- db(0x00); db(0x0e); db(0x70); db(0x05); db(0x4e); db(0xae); db(0xff); db(0x58);
- db(0x60); db(0x02); db(0x4e); db(0x75); db(0x20); db(0x02); db(0x4e); db(0xae);
- db(0xfe); db(0xc2); db(0x22); db(0x6d); db(0x00); db(0x3c); db(0x45); db(0xed);
- db(0x00); db(0x26); db(0x33); db(0x7c); db(0x00); db(0x0b); db(0x00); db(0x1c);
- db(0x23); db(0x7c); db(0x00); db(0x00); db(0x00); db(0x16); db(0x00); db(0x24);
- db(0x23); db(0x4a); db(0x00); db(0x28); db(0x13); db(0x7c); db(0x00); db(0x01);
- db(0x00); db(0x1e); db(0x15); db(0x7c); db(0x00); db(0x04); db(0x00); db(0x04);
- db(0x42); db(0x2a); db(0x00); db(0x05); db(0x42); db(0x6a); db(0x00); db(0x06);
- db(0x42); db(0x6a); db(0x00); db(0x08); db(0x20); db(0x47); db(0x20); db(0x2d);
- db(0x00); db(0x16); db(0x32); db(0x28); db(0x00); db(0x30); db(0xd2); db(0x41);
- db(0x90); db(0x41); db(0x35); db(0x40); db(0x00); db(0x0a); db(0x20); db(0x2d);
- db(0x00); db(0x1a); db(0x32); db(0x28); db(0x00); db(0x2e); db(0xd2); db(0x41);
- db(0x90); db(0x41); db(0x48); db(0xc0); db(0x35); db(0x40); db(0x00); db(0x0c);
- db(0x22); db(0x6d); db(0x00); db(0x40); db(0x33); db(0x7c); db(0x00); db(0x0a);
- db(0x00); db(0x1c); db(0x13); db(0x7c); db(0x00); db(0x01); db(0x00); db(0x1e);
- db(0x4e); db(0xae); db(0xfe); db(0x38); db(0x22); db(0x6d); db(0x00); db(0x40);
- db(0x25); db(0x69); db(0x00); db(0x20); db(0x00); db(0x0e); db(0x25); db(0x69);
- db(0x00); db(0x24); db(0x00); db(0x12); db(0x22); db(0x6d); db(0x00); db(0x3c);
- db(0x4e); db(0xae); db(0xfe); db(0x38); db(0x60); db(0x00); db(0xff); db(0x76);
- db(0x30); db(0x3a); db(0xfe); db(0x82); db(0x48); db(0xc0); db(0x32); db(0x3a);
- db(0xfe); db(0x7e); db(0x48); db(0xc1); db(0xb0); db(0x91); db(0x66); db(0x00);
- db(0x00); db(0x0a); db(0xb2); db(0xa9); db(0x00); db(0x04); db(0x67); db(0x00);
- db(0x00); db(0x18); db(0x23); db(0x41); db(0x00); db(0x04); db(0x22); db(0x80);
- db(0x20); db(0x29); db(0x00); db(0x08); db(0x22); db(0x69); db(0x00); db(0x0c);
- db(0x2c); db(0x78); db(0x00); db(0x04); db(0x4e); db(0xae); db(0xfe); db(0xbc);
- db(0x41); db(0xf9); db(0x00); db(0xdf); db(0xf0); db(0x00); db(0x70); db(0x00);
- db(0x4e); db(0x75); db(0x69); db(0x6e); db(0x70); db(0x75); db(0x74); db(0x2e);
- db(0x64); db(0x65); db(0x76); db(0x69); db(0x63); db(0x65); db(0x00); db(0x74);
- db(0x69); db(0x6d); db(0x65); db(0x72); db(0x2e); db(0x64); db(0x65); db(0x76);
- db(0x69); db(0x63); db(0x65); db(0x00); db(0x55); db(0x41); db(0x45); db(0x20);
- db(0x6d); db(0x6f); db(0x75); db(0x73); db(0x65); db(0x20); db(0x68); db(0x61);
- db(0x63); db(0x6b); db(0x00); db(0x55); db(0x41); db(0x45); db(0x20); db(0x66);
- db(0x69); db(0x6c); db(0x65); db(0x73); db(0x79); db(0x73); db(0x74); db(0x65);
- db(0x6d); db(0x00); db(0x64); db(0x6f); db(0x73); db(0x2e); db(0x6c); db(0x69);
- db(0x62); db(0x72); db(0x61); db(0x72); db(0x79); db(0x00); db(0x69); db(0x6e);
- db(0x74); db(0x75); db(0x69); db(0x74); db(0x69); db(0x6f); db(0x6e); db(0x2e);
- db(0x6c); db(0x69); db(0x62); db(0x72); db(0x61); db(0x72); db(0x79); db(0x00);
- db(0x65); db(0x78); db(0x70); db(0x61); db(0x6e); db(0x73); db(0x69); db(0x6f);
- db(0x6e); db(0x2e); db(0x6c); db(0x69); db(0x62); db(0x72); db(0x61); db(0x72);
- db(0x79); db(0x00); db(0x46); db(0x69); db(0x6c); db(0x65); db(0x53); db(0x79);
- db(0x73); db(0x74); db(0x65); db(0x6d); db(0x2e); db(0x72); db(0x65); db(0x73);
- db(0x6f); db(0x75); db(0x72); db(0x63); db(0x65); db(0x00); db(0x00); db(0x00);
- db(0x00); db(0x00); db(0x03); db(0xf2);
+ db(0x00); db(0x66); db(0x61); db(0x00); db(0xfe); db(0x8e); db(0x61); db(0x00);
+ db(0xfe); db(0xda); db(0x2b); db(0x40); db(0x00); db(0x40); db(0x67); db(0x00);
+ db(0x00); db(0x56); db(0x22); db(0x40); db(0x41); db(0xfa); db(0x01); db(0x25);
+ db(0x70); db(0x00); db(0x72); db(0x00); db(0x4e); db(0xae); db(0xfe); db(0x44);
+ db(0x4a); db(0x80); db(0x66); db(0x00); db(0x00); db(0x42); db(0x47); db(0xed);
+ db(0x00); db(0x16); db(0x27); db(0x4c); db(0x00); db(0x0c); db(0x27); db(0x42);
+ db(0x00); db(0x08); db(0x70); db(0xff); db(0x26); db(0x80); db(0x27); db(0x40);
+ db(0x00); db(0x04); db(0x43); db(0xed); db(0x00); db(0x00); db(0x13); db(0x7c);
+ db(0x00); db(0x02); db(0x00); db(0x08); db(0x13); db(0x7c); db(0x00); db(0x05);
+ db(0x00); db(0x09); db(0x41); db(0xfa); db(0x00); db(0xfc); db(0x23); db(0x48);
+ db(0x00); db(0x0a); db(0x41); db(0xfa); db(0x00); db(0xa0); db(0x23); db(0x48);
+ db(0x00); db(0x12); db(0x23); db(0x4b); db(0x00); db(0x0e); db(0x70); db(0x05);
+ db(0x4e); db(0xae); db(0xff); db(0x58); db(0x60); db(0x02); db(0x4e); db(0x75);
+ db(0x20); db(0x02); db(0x4e); db(0xae); db(0xfe); db(0xc2); db(0x22); db(0x6d);
+ db(0x00); db(0x3c); db(0x45); db(0xed); db(0x00); db(0x26); db(0x33); db(0x7c);
+ db(0x00); db(0x0b); db(0x00); db(0x1c); db(0x23); db(0x7c); db(0x00); db(0x00);
+ db(0x00); db(0x16); db(0x00); db(0x24); db(0x23); db(0x4a); db(0x00); db(0x28);
+ db(0x13); db(0x7c); db(0x00); db(0x01); db(0x00); db(0x1e); db(0x15); db(0x7c);
+ db(0x00); db(0x04); db(0x00); db(0x04); db(0x42); db(0x2a); db(0x00); db(0x05);
+ db(0x42); db(0x6a); db(0x00); db(0x06); db(0x42); db(0x6a); db(0x00); db(0x08);
+ db(0x20); db(0x47); db(0x20); db(0x2d); db(0x00); db(0x16); db(0x32); db(0x28);
+ db(0x00); db(0x30); db(0xd2); db(0x41); db(0x90); db(0x41); db(0x35); db(0x40);
+ db(0x00); db(0x0a); db(0x20); db(0x2d); db(0x00); db(0x1a); db(0x32); db(0x28);
+ db(0x00); db(0x2e); db(0xd2); db(0x41); db(0x90); db(0x41); db(0x48); db(0xc0);
+ db(0x35); db(0x40); db(0x00); db(0x0c); db(0x22); db(0x6d); db(0x00); db(0x40);
+ db(0x33); db(0x7c); db(0x00); db(0x0a); db(0x00); db(0x1c); db(0x13); db(0x7c);
+ db(0x00); db(0x01); db(0x00); db(0x1e); db(0x4e); db(0xae); db(0xfe); db(0x38);
+ db(0x22); db(0x6d); db(0x00); db(0x40); db(0x25); db(0x69); db(0x00); db(0x20);
+ db(0x00); db(0x0e); db(0x25); db(0x69); db(0x00); db(0x24); db(0x00); db(0x12);
+ db(0x22); db(0x6d); db(0x00); db(0x3c); db(0x4e); db(0xae); db(0xfe); db(0x38);
+ db(0x60); db(0x00); db(0xff); db(0x76); db(0x30); db(0x3a); db(0xfe); db(0x76);
+ db(0x48); db(0xc0); db(0x32); db(0x3a); db(0xfe); db(0x72); db(0x48); db(0xc1);
+ db(0xb0); db(0x91); db(0x66); db(0x00); db(0x00); db(0x0a); db(0xb2); db(0xa9);
+ db(0x00); db(0x04); db(0x67); db(0x00); db(0x00); db(0x18); db(0x23); db(0x41);
+ db(0x00); db(0x04); db(0x22); db(0x80); db(0x20); db(0x29); db(0x00); db(0x08);
+ db(0x22); db(0x69); db(0x00); db(0x0c); db(0x2c); db(0x78); db(0x00); db(0x04);
+ db(0x4e); db(0xae); db(0xfe); db(0xbc); db(0x41); db(0xf9); db(0x00); db(0xdf);
+ db(0xf0); db(0x00); db(0x70); db(0x00); db(0x4e); db(0x75); db(0x69); db(0x6e);
+ db(0x70); db(0x75); db(0x74); db(0x2e); db(0x64); db(0x65); db(0x76); db(0x69);
+ db(0x63); db(0x65); db(0x00); db(0x74); db(0x69); db(0x6d); db(0x65); db(0x72);
+ db(0x2e); db(0x64); db(0x65); db(0x76); db(0x69); db(0x63); db(0x65); db(0x00);
+ db(0x55); db(0x41); db(0x45); db(0x20); db(0x6d); db(0x6f); db(0x75); db(0x73);
+ db(0x65); db(0x20); db(0x68); db(0x61); db(0x63); db(0x6b); db(0x00); db(0x55);
+ db(0x41); db(0x45); db(0x20); db(0x66); db(0x69); db(0x6c); db(0x65); db(0x73);
+ db(0x79); db(0x73); db(0x74); db(0x65); db(0x6d); db(0x00); db(0x64); db(0x6f);
+ db(0x73); db(0x2e); db(0x6c); db(0x69); db(0x62); db(0x72); db(0x61); db(0x72);
+ db(0x79); db(0x00); db(0x69); db(0x6e); db(0x74); db(0x75); db(0x69); db(0x74);
+ db(0x69); db(0x6f); db(0x6e); db(0x2e); db(0x6c); db(0x69); db(0x62); db(0x72);
+ db(0x61); db(0x72); db(0x79); db(0x00); db(0x65); db(0x78); db(0x70); db(0x61);
+ db(0x6e); db(0x73); db(0x69); db(0x6f); db(0x6e); db(0x2e); db(0x6c); db(0x69);
+ db(0x62); db(0x72); db(0x61); db(0x72); db(0x79); db(0x00); db(0x46); db(0x69);
+ db(0x6c); db(0x65); db(0x53); db(0x79); db(0x73); db(0x74); db(0x65); db(0x6d);
+ db(0x2e); db(0x72); db(0x65); db(0x73); db(0x6f); db(0x75); db(0x72); db(0x63);
+ db(0x65); db(0x00); db(0x00); db(0x00); db(0x00); db(0x00); db(0x03); db(0xf2);
#define DEBUG_FPP 0
+STATIC_INLINE int isfpu(struct regstruct *regs)
+{
+ if (regs->pcr & 2)
+ return FALSE;
+ if (currprefs.fpu_model <= 0)
+ return FALSE;
+ return TRUE;
+}
+
STATIC_INLINE int isinrom (void)
{
return (munge24 (m68k_getpc (®s)) & 0xFFF80000) == 0xF80000;
typedef uae_s32 tointtype;
#endif
+static int get_fpu_version(void)
+{
+ int v = 0;
+ switch (currprefs.fpu_model)
+ {
+ case 68881:
+ v = 0x1f;
+ break;
+ case 68882:
+ v = 0x20; /* ??? */
+ break;
+ case 68040:
+ v = 0x41;
+ break;
+ }
+ return v;
+}
+
STATIC_INLINE tointtype toint(fptype src, fptype minval, fptype maxval)
{
if (src < minval)
write_log ("fdbcc_opp at %08lx\n", m68k_getpc (regs));
#endif
cc = fpp_cond (opcode, extra & 0x3f);
- if (cc == -1) {
+ if (cc == -1 || !isfpu(regs)) {
m68k_setpc (regs, pc - 4);
op_illg (opcode, regs);
} else if (!cc) {
write_log ("fscc_opp at %08lx\n", m68k_getpc (regs));
#endif
cc = fpp_cond (opcode, extra & 0x3f);
- if (cc == -1) {
+ if (cc == -1 || !isfpu(regs)) {
m68k_setpc (regs, m68k_getpc (regs) - 4);
op_illg (opcode, regs);
} else if ((opcode & 0x38) == 0) {
write_log ("ftrapcc_opp at %08lx\n", m68k_getpc (regs));
#endif
cc = fpp_cond (opcode, opcode & 0x3f);
- if (cc == -1) {
+ if (cc == -1 || !isfpu(regs)) {
m68k_setpc (regs, oldpc);
op_illg (opcode, regs);
}
write_log ("fbcc_opp at %08lx\n", m68k_getpc (regs));
#endif
cc = fpp_cond (opcode, opcode & 0x3f);
- if (cc == -1) {
+ if (cc == -1 || !isfpu(regs)) {
m68k_setpc (regs, pc);
op_illg (opcode, regs);
} else if (cc) {
{
uae_u32 ad;
int incr = (opcode & 0x38) == 0x20 ? -1 : 1;
- int fpu_version = 0x18; /* 68881 */
-// int fpu_version = 0x38; /* 68882 */
+ int fpu_version = get_fpu_version();
int i;
-
#if DEBUG_FPP
if (!isinrom ())
write_log ("fsave_opp at %08lx\n", m68k_getpc (regs));
#endif
- if (get_fp_ad (opcode, &ad) == 0) {
+ if (get_fp_ad (opcode, &ad) == 0 || !isfpu(regs)) {
m68k_setpc (regs, m68k_getpc (regs) - 2);
op_illg (opcode, regs);
return;
}
-#if 0
- if (currprefs.cpu_level >= 6) {
- /* 6 byte 68060 IDLE frame. */
+ if (currprefs.fpu_model == 68060) {
+ /* 12 byte 68060 IDLE frame. */
if (incr < 0) {
- ad -= 6;
+ ad -= 4;
+ put_long (ad, 0x00000000);
+ ad -= 4;
+ put_long (ad, 0x00000000);
+ ad -= 4;
put_long (ad, 0x00006000);
} else {
put_long (ad, 0x00006000);
- ad += 6;
+ ad += 4;
+ put_long (ad, 0x00000000);
+ ad += 4;
+ put_long (ad, 0x00000000);
+ ad += 4;
}
- } else
-#endif
- if (currprefs.cpu_level >= 4) {
+ } else if (currprefs.fpu_model == 68040) {
/* 4 byte 68040 IDLE frame. */
if (incr < 0) {
ad -= 4;
- put_long (ad, 0x41000000);
+ put_long (ad, fpu_version << 24);
} else {
- put_long (ad, 0x41000000);
+ put_long (ad, fpu_version << 24);
ad += 4;
}
- } else {
+ } else { /* 68881/68882 */
+ int idle_size = currprefs.fpu_model == 68882 ? 0x38 : 0x18;
if (incr < 0) {
ad -= 4;
put_long (ad, 0x70000000);
- for (i = 0; i < 5; i++) {
+ for (i = 0; i < (idle_size - 1) / 4; i++) {
ad -= 4;
put_long (ad, 0x00000000);
}
ad -= 4;
- put_long (ad, 0x1f000000 | (fpu_version << 16));
+ put_long (ad, (fpu_version << 24) | (idle_size << 16));
} else {
- put_long (ad, 0x1f000000 | (fpu_version << 16));
+ put_long (ad, (fpu_version << 24) | (idle_size << 16));
ad += 4;
- for (i = 0; i < 5; i++) {
+ for (i = 0; i < (idle_size - 1) / 4; i++) {
put_long (ad, 0x00000000);
ad += 4;
}
if (!isinrom ())
write_log ("frestore_opp at %08lx\n", m68k_getpc (regs));
#endif
- if (get_fp_ad (opcode, &ad) == 0) {
+ if (get_fp_ad (opcode, &ad) == 0 || !isfpu(regs)) {
m68k_setpc (regs, m68k_getpc (regs) - 2);
op_illg (opcode, regs);
return;
}
-#if 0
- if (currprefs.cpu_level >= 6) {
- /* 68060 */
- d = get_long (ad);
+
+ if (currprefs.fpu_model == 68060) {
+ /* all 68060 FPU frames are 12 bytes */
if (incr < 0) {
- ad -= 6;
+ ad -= 4;
d = get_long (ad);
- } else
- ad += 6;
- } else
-#endif
- if (currprefs.cpu_level >= 4) {
+ ad -= 8;
+ } else {
+ d = get_long (ad);
+ ad += 4;
+ ad += 8;
+ }
+
+ } else if (currprefs.fpu_model == 68040) {
/* 68040 */
if (incr < 0) {
/* @@@ This may be wrong. */
}
}
}
- } else {
+ } else { /* 68881/68882 */
if (incr < 0) {
ad -= 4;
d = get_long (ad);
if (!isinrom ())
write_log ("FPP %04lx %04x at %08lx\n", opcode & 0xffff, extra, m68k_getpc (regs) - 4);
#endif
+ if (!isfpu(regs)) {
+ m68k_setpc (regs, m68k_getpc (regs) - 4);
+ op_illg (opcode, regs);
+ return;
+ }
+
switch ((extra >> 13) & 0x7) {
case 3:
uae_u8 *restore_fpu (uae_u8 *src)
{
- int model, i;
+ int i;
- model = restore_u32();
+ changed_prefs.fpu_model = currprefs.fpu_model = restore_u32();
restore_u32 ();
- if (currprefs.cpu_level == 2) {
- currprefs.cpu_level++;
+ if (currprefs.cpu_level == 2 || currprefs.cpu_level == 3) {
+ currprefs.cpu_level = 4;
init_m68k ();
}
changed_prefs.cpu_level = currprefs.cpu_level;
uae_u8 *save_fpu (int *len, uae_u8 *dstptr)
{
uae_u8 *dstbak,*dst;
- int model,i;
+ int i;
*len = 0;
- switch (currprefs.cpu_level)
- {
- case 3:
- model = 68881;
- break;
- case 4:
- model = 68040;
- break;
- case 6:
- model = 68060;
- break;
- default:
+ if (currprefs.fpu_model == 0)
return 0;
- }
if (dstptr)
dstbak = dst = dstptr;
else
dstbak = dst = malloc(4+4+8*10+4+4+4);
- save_u32 (model);
+ save_u32 (currprefs.fpu_model);
save_u32 (0);
for (i = 0; i < 8; i++) {
uae_u32 w1, w2, w3;
using_exception_3 = 0;
for (i = 0; i < 1; i++) /* We only do one level! */
{
- cpu_level = 4 - i;
+ cpu_level = 6 - i;
postfix = i;
if (noflags)
if (file) {
fscanf (file, "Total: %lu\n", &total);
while (fscanf (file, "%lx: %lu %s\n", &opcode, &count, name) == 3) {
- opcode_next_clev[nr] = 4;
+ opcode_next_clev[nr] = 6;
opcode_last_postfix[nr] = -1;
opcode_map[nr++] = opcode;
counts[opcode] = count;
if (table68k[opcode].handler == -1 && table68k[opcode].mnemo != i_ILLG
&& counts[opcode] == 0)
{
- opcode_next_clev[nr] = 4;
+ opcode_next_clev[nr] = 6;
opcode_last_postfix[nr] = -1;
opcode_map[nr++] = opcode;
counts[opcode] = count;
sync_m68k_pc ();
printf ("\tmmu_op(opcode, regs, extra);\n");
break;
+ case i_MMUOP30:
+ genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0, 0);
+ sync_m68k_pc ();
+ printf ("\tmmu_op30(opcode, regs, extra);\n");
+ break;
default:
abort ();
break;
using_ce = 0;
postfix2 = -1;
- for (i = 0; i < 7; i++) {
+ for (i = 0; i < 13; i++) {
postfix = i;
- if (i == 0 || i == 5 || i == 6) {
+ if (i >= 7 && i < 11)
+ continue;
+ if (i == 0 || i == 11 || i == 12) {
fprintf (stblfile, "#ifdef CPUEMU_%d\n", postfix);
postfix2 = postfix;
sprintf (fname, "cpuemu_%d.c", postfix);
freopen (fname, "wb", stdout);
generate_includes (stdout);
}
- cpu_level = 4 - i;
- if (i == 5 || i == 6) {
+ cpu_level = 6 - i;
+ if (i == 11 || i == 12) {
cpu_level = 0;
using_prefetch = 1;
using_exception_3 = 1;
- if (i == 6) using_ce = 1;
+ if (i == 12)
+ using_ce = 1;
for (rp = 0; rp < nr_cpuop_funcs; rp++)
opcode_next_clev[rp] = 0;
}
- if (i > 0 && i < 4)
+ if (i > 0 && i < 7)
fprintf (stblfile, "#ifndef CPUEMU_68000_ONLY\n");
fprintf (stblfile, "const struct cputbl CPUFUNC(op_smalltbl_%d)[] = {\n", postfix);
generate_func ();
- if (i > 0 && i < 4)
+ if (i > 0 && i < 7)
fprintf (stblfile, "#endif /* CPUEMU_68000_ONLY */\n");
if (postfix2 >= 0)
fprintf (stblfile, "#endif /* CPUEMU_%d */\n", postfix2);
return v;
}
-#ifdef CPUEMU_6
+#ifdef CPUEMU_12
STATIC_INLINE uae_u32 mem_access_delay_word_read (uaecptr addr)
{
if (addr < 0x200000 || (addr >= 0xc00000 && addr < 0xe00000)) {
flagtype stopped;
int intmask;
- uae_u32 vbr,sfc,dfc;
+ uae_u32 vbr, sfc, dfc;
#ifdef FPUEMU
fptype fp[8];
uae_u32 fpsr_highbyte;
#endif
+ uae_u32 pcr;
uae_u32 spcflags;
uae_u32 kick_mask;
uae_u32 address_space_mask;
#define CPU_OP_NAME(a) op ## a
-/* 68040 */
+/* 68060 */
extern const struct cputbl op_smalltbl_0_ff[];
-/* 68020 + 68881 */
+/* 68040 */
extern const struct cputbl op_smalltbl_1_ff[];
-/* 68020 */
+/* 68020/68030+FPU */
extern const struct cputbl op_smalltbl_2_ff[];
-/* 68010 */
+/* 68030 */
extern const struct cputbl op_smalltbl_3_ff[];
-/* 68000 */
+/* 68020 */
extern const struct cputbl op_smalltbl_4_ff[];
-/* 68000 slow but compatible. */
+/* 68010 */
extern const struct cputbl op_smalltbl_5_ff[];
-/* 68000 slow but compatible and cycle-exact. */
+/* 68000 */
extern const struct cputbl op_smalltbl_6_ff[];
+/* 68000 slow but compatible. */
+extern const struct cputbl op_smalltbl_11_ff[];
+/* 68000 slow but compatible and cycle-exact. */
+extern const struct cputbl op_smalltbl_12_ff[];
extern cpuop_func *cpufunctbl[65536] ASM_SYM_FOR_FUNC ("cpufunctbl");
int m68k_speed;
int cpu_level;
+ int cpu_model;
+ int fpu_model;
int cpu_compatible;
int address_space_24;
int picasso96_nocustom;
i_PACK, i_UNPK, i_TAS, i_BKPT, i_CALLM, i_RTM, i_TRAPcc, i_MOVES,
i_FPP, i_FDBcc, i_FScc, i_FTRAPcc, i_FBcc, i_FSAVE, i_FRESTORE,
i_CINVL, i_CINVP, i_CINVA, i_CPUSHL, i_CPUSHP, i_CPUSHA, i_MOVE16,
- i_MMUOP
+ i_MMUOP30, i_MMUOP
} ENUMNAME (instrmnem);
extern struct mnemolookup {
{
if (!uae_boot_rom)
return;
- if (rtarea[get_long (RTAREA_BASE + 40) + 12 - 1])
+ if (rtarea[get_long (RTAREA_BASE + 40) + 12 - 2] == 0xff)
return;
- rtarea[get_long (RTAREA_BASE + 40) + 12 - 1] = 1;
+ rtarea[get_long (RTAREA_BASE + 40) + 12 - 2] = 1;
}
static void mousehack_setpos(int mousexpos, int mouseypos)
fixup_prefs_dim2(&prefs->gfx_size_win);
}
+static void fixup_cpu(struct uae_prefs *p)
+{
+ p->cpu_level = 0;
+ switch(p->cpu_model)
+ {
+ case 68000:
+ p->cpu_level = 0;
+ p->address_space_24 = 1;
+ p->fpu_model = 0;
+ break;
+ case 68010:
+ p->cpu_level = 1;
+ p->address_space_24 = 1;
+ p->fpu_model = 0;
+ break;
+ case 68020:
+ p->cpu_level = 2;
+ break;
+ case 68030:
+ p->cpu_level = 3;
+ p->address_space_24 = 0;
+ break;
+ case 68040:
+ p->cpu_level = 5;
+ p->address_space_24 = 0;
+ if (p->fpu_model)
+ p->fpu_model = 68040;
+ break;
+ case 68060:
+ p->cpu_level = 6;
+ p->address_space_24 = 0;
+ if (p->fpu_model)
+ p->fpu_model = 68060;
+ break;
+ }
+ if ((p->cpu_level == 2 || p->cpu_level == 3) && p->fpu_model)
+ p->cpu_level = 4;
+}
+
+
void fixup_prefs (struct uae_prefs *p)
{
int err = 0;
build_in_chipset_prefs (p);
+ fixup_cpu(p);
+
if ((p->chipmem_size & (p->chipmem_size - 1)) != 0
|| p->chipmem_size < 0x40000
|| p->chipmem_size > 0x800000)
p->cachesize = 0;
err = 1;
}
- if (p->cpu_level < 2 && p->z3fastmem_size > 0) {
+ if (p->z3fastmem_size > 0 && (p->address_space_24 || p->cpu_model < 68020)) {
write_log ("Z3 fast memory can't be used with a 68000/68010 emulation. It\n"
"requires a 68020 emulation. Turning off Z3 fast memory.\n");
p->z3fastmem_size = 0;
err = 1;
}
- if (p->gfxmem_size > 0 && (p->cpu_level < 2 || p->address_space_24)) {
+ if (p->gfxmem_size > 0 && (p->cpu_model < 68020 || p->address_space_24)) {
write_log ("Picasso96 can't be used with a 68000/68010 or 68EC020 emulation. It\n"
"requires a 68020 emulation. Turning off Picasso96.\n");
p->gfxmem_size = 0;
if (p->cs_compatible) {
p->cs_fatgaryrev = p->cs_ramseyrev = p->cs_mbdmac = -1;
p->cs_ide = 0;
- if (p->cpu_level >= 2) {
+ if (p->cpu_model >= 68020) {
p->cs_fatgaryrev = 0;
p->cs_ide = -1;
p->cs_ramseyrev = 0x0f;
fixup_prefs_dimensions (p);
#ifdef CPU_68000_ONLY
+ p->cpu_model = 68000;
p->cpu_level = 0;
+ p->fpu_model = 0;
#endif
#ifndef CPUEMU_0
p->cpu_compatible = 1;
p->address_space_24 = 1;
#endif
-#if !defined(CPUEMU_5) && !defined (CPUEMU_6)
+#if !defined(CPUEMU_11) && !defined (CPUEMU_12)
p->cpu_compatible = 0;
p->address_space_24 = 0;
#endif
-#if !defined (CPUEMU_6)
+#if !defined (CPUEMU_12)
p->cpu_cycle_exact = p->blitter_cycle_exact = 0;
#endif
#ifndef AGA
#if !defined (UAESERIAL)
p->uaeserial = 0;
#endif
-#if defined(CPUEMU_6)
+#if defined(CPUEMU_12)
if (p->cpu_cycle_exact)
p->gfx_framerate = 1;
#endif
}
#ifdef JIT
- if (!(( currprefs.cpu_level >= 2 ) && ( currprefs.address_space_24 == 0 ) && ( currprefs.cachesize )))
+ if (!((currprefs.cpu_model >= 68020) && (currprefs.address_space_24 == 0) && (currprefs.cachesize)))
canbang = 0;
#endif
#endif
if (currprefs.illegal_mem)
dummylog(0, addr, 4, 0, 0);
- if (currprefs.cpu_level >= 2)
+ if (currprefs.cpu_model >= 68020)
return NONEXISTINGDATA;
return (regs.irc << 16) | regs.irc;
}
#endif
if (currprefs.illegal_mem)
dummylog(0, addr, 4, 0, 1);
- if (currprefs.cpu_level >= 2)
+ if (currprefs.cpu_model >= 68020)
return NONEXISTINGDATA;
return (regs.irc << 16) | regs.irc;
}
#endif
if (currprefs.illegal_mem)
dummylog(0, addr, 2, 0, 0);
- if (currprefs.cpu_level >= 2)
+ if (currprefs.cpu_model >= 68020)
return NONEXISTINGDATA;
return regs.irc;
}
#endif
if (currprefs.illegal_mem)
dummylog(0, addr, 2, 0, 1);
- if (currprefs.cpu_level >= 2)
+ if (currprefs.cpu_model >= 68020)
return NONEXISTINGDATA;
return regs.irc;
}
#endif
if (currprefs.illegal_mem)
dummylog(0, addr, 1, 0, 0);
- if (currprefs.cpu_level >= 2)
+ if (currprefs.cpu_model >= 68020)
return NONEXISTINGDATA;
return (addr & 1) ? regs.irc : regs.irc >> 8;
}
{
if (quit_program == 0) {
/* do this only in 68010+ mode, there are some tricky A500 programs.. */
- if (currprefs.cpu_level > 0 || !currprefs.cpu_compatible) {
+ if (currprefs.cpu_model > 68000 || !currprefs.cpu_compatible) {
#if defined(ENFORCER)
enforcer_disable ();
#endif
cb = &chipmem_bank;
#ifdef AGA
- if (currprefs.cpu_cycle_exact && currprefs.cpu_level >= 2)
+ if (currprefs.cpu_cycle_exact && currprefs.cpu_model >= 68020)
cb = &chipmem_bank_ce2;
#endif
if (chip)
} else {
struct romdata *rd = getromdatabydata (kickmemory, kickmem_size);
if (rd) {
- if ((rd->cpu & 3) == 1 && changed_prefs.cpu_level < 2) {
+ if ((rd->cpu & 3) == 1 && changed_prefs.cpu_model < 68020) {
notify_user (NUMSG_KS68EC020);
uae_restart (-1, NULL);
- } else if ((rd->cpu & 3) == 2 && (changed_prefs.cpu_level < 2 || changed_prefs.address_space_24)) {
+ } else if ((rd->cpu & 3) == 2 && (changed_prefs.cpu_model < 68020 || changed_prefs.address_space_24)) {
notify_user (NUMSG_KS68020);
uae_restart (-1, NULL);
}
int t = allocated_bogomem >> 16;
if (t > 0x1C)
t = 0x1C;
- if (t > 0x10 && ((currprefs.chipset_mask & CSMASK_AGA) || currprefs.cpu_level >= 2))
+ if (t > 0x10 && ((currprefs.chipset_mask & CSMASK_AGA) || currprefs.cpu_model >= 68020))
t = 0x10;
map_banks (&bogomem_bank, 0xC0, t, 0);
}
extern uae_u32 get_fpsr(void);
#define COUNT_INSTRS 0
+#define MC68060_PCR 0x04300100
#if COUNT_INSTRS
static unsigned long int instrcount[65536];
int i, opcnt;
unsigned long opcode;
const struct cputbl *tbl = 0;
+ int fpu_model = 0;
- switch (currprefs.cpu_level)
+ switch (currprefs.cpu_level)
{
#ifdef CPUEMU_0
#ifndef CPUEMU_68000_ONLY
- case 4:
- case 6:
+ case 6: /* 68060 */
tbl = op_smalltbl_0_ff;
break;
- case 3:
- tbl = op_smalltbl_1_ff;
+ case 5: /* 68040 */
+ tbl = op_smalltbl_0_ff;
break;
- case 2:
+ case 4: /* 68020/68030 + 68881+68882 */
tbl = op_smalltbl_2_ff;
break;
- case 1:
+ case 3: /* 68030 */
tbl = op_smalltbl_3_ff;
break;
+ case 2: /* 68020 */
+ tbl = op_smalltbl_4_ff;
+ break;
+ case 1: /* 68010 */
+ tbl = op_smalltbl_5_ff;
+ break;
#endif
#endif
- case 0:
- tbl = op_smalltbl_4_ff;
-#ifdef CPUEMU_5
+ case 0: /* 68000 */
+ tbl = op_smalltbl_6_ff;
+#ifdef CPUEMU_11
if (currprefs.cpu_compatible)
- tbl = op_smalltbl_5_ff; /* prefetch */
+ tbl = op_smalltbl_11_ff; /* prefetch */
#endif
-#ifdef CPUEMU_6
+#ifdef CPUEMU_12
if (currprefs.cpu_cycle_exact)
- tbl = op_smalltbl_6_ff; /* prefetch and cycle-exact */
+ tbl = op_smalltbl_12_ff; /* prefetch and cycle-exact */
#endif
break;
}
opcnt++;
}
}
- write_log ("Building CPU function table, %d opcodes (%d %d %d).\n",
+ write_log ("Building CPU function table, %d opcodes (%d %d %d). CPU=%d, FPU=%d.\n",
opcnt, currprefs.cpu_level,
currprefs.cpu_cycle_exact ? -1 : currprefs.cpu_compatible ? 1 : 0,
- currprefs.address_space_24);
+ currprefs.address_space_24, currprefs.cpu_model, currprefs.fpu_model);
#ifdef JIT
build_comp ();
#endif
void fill_prefetch_slow (struct regstruct *regs)
{
-#ifdef CPUEMU_6
+#ifdef CPUEMU_12
if (currprefs.cpu_cycle_exact) {
regs->ir = get_word_ce (m68k_getpc (regs));
regs->irc = get_word_ce (m68k_getpc (regs) + 2);
#endif
regs->ir = get_word (m68k_getpc (regs));
regs->irc = get_word (m68k_getpc (regs) + 2);
-#ifdef CPUEMU_6
+#ifdef CPUEMU_12
}
#endif
}
void check_prefs_changed_cpu (void)
{
if (currprefs.cpu_level != changed_prefs.cpu_level
+ || currprefs.cpu_model != changed_prefs.cpu_model
+ || currprefs.fpu_model != changed_prefs.fpu_model
|| currprefs.cpu_compatible != changed_prefs.cpu_compatible
|| currprefs.cpu_cycle_exact != changed_prefs.cpu_cycle_exact) {
fill_prefetch_slow (®s);
currprefs.cpu_level = changed_prefs.cpu_level;
+ currprefs.cpu_model = changed_prefs.cpu_model;
+ currprefs.fpu_model = changed_prefs.fpu_model;
currprefs.cpu_compatible = changed_prefs.cpu_compatible;
currprefs.cpu_cycle_exact = changed_prefs.cpu_cycle_exact;
currprefs.blitter_cycle_exact = changed_prefs.cpu_cycle_exact;
}
}
#endif
- write_log ("Building CPU table for configuration: 68");
+ write_log ("Building CPU table for configuration: %d", currprefs.cpu_model);
regs.address_space_mask = 0xffffffff;
if (currprefs.cpu_compatible > 0) {
- if (currprefs.address_space_24 && currprefs.cpu_level > 3)
+ if (currprefs.address_space_24 && currprefs.cpu_model >= 68030)
currprefs.address_space_24 = 0;
- if (currprefs.address_space_24 && currprefs.cpu_level > 1)
- write_log ("EC");
- }
- switch (currprefs.cpu_level) {
- case 1:
- write_log ("010");
- break;
- case 2:
- write_log ("020");
- break;
- case 3:
- write_log ("020/881");
- break;
- case 4:
- /* Who is going to miss the MMU anyway...? :-) */
- write_log ("040");
- break;
- case 6:
- /* Who is going to miss the MMU anyway...? :-) */
- write_log ("060");
- break;
- default:
- write_log ("000");
- break;
}
+ if (currprefs.fpu_model > 0)
+ write_log("/%d", currprefs.fpu_model);
if (currprefs.cpu_cycle_exact) {
- if (currprefs.cpu_level == 0)
+ if (currprefs.cpu_model == 68000)
write_log (" prefetch and cycle-exact");
else
write_log (" ~cycle-exact");
write_log (" prefetch");
if (currprefs.address_space_24) {
regs.address_space_mask = 0x00ffffff;
- write_log (" 24-bit addressing");
+ write_log (" 24-bit");
}
write_log ("\n");
regs->s = (regs->sr >> 13) & 1;
regs->m = (regs->sr >> 12) & 1;
regs->intmask = (regs->sr >> 8) & 7;
- if (currprefs.cpu_level >= 2) {
+ if (currprefs.cpu_model >= 68020) {
+ /* 68060 does not have MSP but does have M-bit.. */
+ if (currprefs.cpu_model >= 68060)
+ regs->msp = regs->isp;
if (olds != regs->s) {
if (olds) {
if (oldm)
m68k_areg (regs, 7) = regs->msp;
}
}
+ if (currprefs.cpu_model >= 68060)
+ regs->t0 = 0;
} else {
regs->t0 = regs->m = 0;
if (olds != regs->s) {
#endif
}
-#ifdef CPUEMU_6
+#ifdef CPUEMU_12
/* cycle-exact exception handler, 68000 only */
if (!regs->s) {
regs->usp = m68k_areg(regs, 7);
- if (currprefs.cpu_level >= 2)
+ if (currprefs.cpu_model >= 68020)
m68k_areg(regs, 7) = regs->m ? regs->msp : regs->isp;
else
m68k_areg(regs, 7) = regs->isp;
regs->s = 1;
}
- if (currprefs.cpu_level > 0) {
+ if (currprefs.cpu_model > 68000) {
if (nr == 2 || nr == 3) {
int i;
- if (currprefs.cpu_level >= 4) { /* 68040 */
+ if (currprefs.cpu_model >= 68040) {
if (nr == 2) {
for (i = 0 ; i < 18 ; i++) {
m68k_areg(regs, 7) -= 2;
write_log ("exception %d %08.8X %08.8X (%04.4X %04.4X)\n",
nr, oldpc, m68k_getpc(), intena, intreq);
#endif
-#ifdef CPUEMU_6
- if (currprefs.cpu_cycle_exact && currprefs.cpu_level == 0)
+#ifdef CPUEMU_12
+ if (currprefs.cpu_cycle_exact && currprefs.cpu_model == 68000)
Exception_ce (nr, regs, oldpc);
else
#endif
do_interrupt (nr, ®s);
}
-static uae_u32 caar, cacr, itt0, itt1, dtt0, dtt1, tc, mmusr, urp, srp, buscr, pcr;
+static uae_u32 caar, cacr, itt0, itt1, dtt0, dtt1, tc, mmusr, urp, srp, buscr;
#ifndef CPUEMU_68000_ONLY
static int movec_illg (int regno)
{
int regno2 = regno & 0x7ff;
- if (currprefs.cpu_level == 1) { /* 68010 */
+
+ if (currprefs.cpu_model == 68060) {
+ if (regno <= 8)
+ return 0;
+ if (regno == 0x800 || regno == 0x801 ||
+ regno == 0x806 || regno == 0x807 || regno == 0x808)
+ return 0;
+ return 1;
+ } else if (currprefs.cpu_model == 68010) {
if (regno2 < 2)
return 0;
return 1;
- }
- if (currprefs.cpu_level == 2 || currprefs.cpu_level == 3) { /* 68020 */
+ } else if (currprefs.cpu_model == 68020) {
if (regno == 3) return 1; /* 68040 only */
/* 4 is >=68040, but 0x804 is in 68020 */
if (regno2 < 4 || regno == 0x804)
return 0;
return 1;
- }
- if (currprefs.cpu_level >= 4) { /* 68040 */
+ } else if (currprefs.cpu_model == 68030) {
+ if (regno2 <= 2) return 0;
+ if (regno == 0x803 || regno == 0x804)
+ return 0;
+ return 1;
+ } else if (currprefs.cpu_model == 68040) {
if (regno == 0x802) return 1; /* 68020 only */
if (regno2 < 8) return 0;
- if (currprefs.cpu_level == 6 && regno2 == 8) /* 68060 only */
- return 0;
return 1;
}
return 1;
int m68k_move2c (int regno, uae_u32 *regp)
{
- //write_log("move2c %04.4X <- %08.8X\n", regno, *regp);
+#ifdef MOVEC_DEBUG
+ write_log("move2c %04.4X <- %08.8X PC=%x\n", regno, *regp, M68K_GETPC);
+#endif
if (movec_illg (regno)) {
op_illg (0x4E7B, ®s);
return 0;
switch (regno) {
case 0: regs.sfc = *regp & 7; break;
case 1: regs.dfc = *regp & 7; break;
- case 2:
- cacr = *regp & (currprefs.cpu_level < 4 ? 0x3 : (currprefs.cpu_level == 4 ? 0x80008000 : 0xf8800e00));
+ case 2:
+ {
+ uae_u32 cacr_mask = 0;
+ if (currprefs.cpu_model == 68020)
+ cacr_mask = 0x00000003;
+ else if (currprefs.cpu_model == 68030)
+ cacr_mask = 0x00003313;
+ else if (currprefs.cpu_model == 68040)
+ cacr_mask = 0x80008000;
+ else if (currprefs.cpu_model == 68060)
+ cacr_mask = 0xf880e000;
+ cacr = *regp & cacr_mask;
#ifdef JIT
- if (currprefs.cpu_level < 4) {
+ if (currprefs.cpu_model < 68040) {
set_cache_state(cacr & 1);
if (*regp & 0x08) {
flush_icache(1);
}
}
#endif
- break;
+ }
+ break;
case 3: tc = *regp & 0xc000; break;
/* Mask out fields that should be zero. */
case 4: itt0 = *regp & 0xffffe364; break;
case 0x805: mmusr = *regp; break;
case 0x806: urp = *regp; break;
case 0x807: srp = *regp; break;
- case 0x808: pcr = *regp & (0x40 | 2 | 1); break;
+ case 0x808:
+ {
+ uae_u32 opcr = regs.pcr;
+ regs.pcr = (*regp & (0x40 | 2 | 1)) | MC68060_PCR;
+ if (((opcr ^ regs.pcr) & 2) == 2) {
+ write_log("68060 FPU state: %s\n", regs.pcr & 2 ? "disabled" : "enabled");
+ flush_icache(2);
+ }
+ }
+ break;
default:
op_illg (0x4E7B, ®s);
return 0;
int m68k_movec2 (int regno, uae_u32 *regp)
{
- //write_log("movec2 %04.4X\n", regno);
+#ifdef MOVEC_DEBUG
+ write_log("movec2 %04.4X PC=%x\n", regno, M68K_GETPC);
+#endif
if (movec_illg (regno)) {
op_illg (0x4E7A, ®s);
return 0;
case 0x805: *regp = mmusr; break;
case 0x806: *regp = urp; break;
case 0x807: *regp = srp; break;
- case 0x808: *regp = 0x04300100 | pcr; break;
+ case 0x808: *regp = MC68060_PCR | regs.pcr; break;
default:
op_illg (0x4E7A, ®s);
return 0;
}
}
- //write_log("-> %08.8X\n", *regp);
+#ifdef MOVEC_DEBUG
+ write_log("-> %08.8X\n", *regp);
+#endif
return 1;
}
regs.fp_result=1;
regs.irc = 0xffff;
#endif
+ caar = cacr = 0;
+ itt0 = itt1 = dtt0 = dtt1 = 0;
+ tc = mmusr = urp = srp = buscr = 0;
+ /* 68060 FPU is not compatible with 68040,
+ * 68060 accelerators' boot ROM disables the FPU
+ */
+ if (currprefs.cpu_model == 68060)
+ regs.pcr |= 2;
+
fill_prefetch_slow (®s);
}
}
#ifdef CPUEMU_0
+void mmu_op30(uae_u32 opcode, struct regstruct *regs, uae_u16 extra)
+{
+ if (currprefs.cpu_model != 68030) {
+ m68k_setpc (regs, m68k_getpc (regs) - 2);
+ op_illg (opcode, regs);
+ return;
+ }
+ write_log("MMU030: %04.4x\n", opcode);
+ return;
+}
void mmu_op(uae_u32 opcode, struct regstruct *regs, uae_u16 extra)
{
+#ifdef MOVEC_DEBUG
+ write_log("mmu_op %04.4x\n", opcode);
+#endif
if ((opcode & 0xFE0) == 0x0500) {
/* PFLUSH */
mmusr = 0;
//write_log ("PFLUSH @$%lx\n", m68k_getpc());
+ return;
} else if ((opcode & 0x0FD8) == 0x548) {
- /* PTEST */
- //write_log ("PTEST @$%lx\n", m68k_getpc());
- } else
- op_illg (opcode, regs);
+ if (currprefs.cpu_model < 68060) { /* PTEST not in 68060 */
+ /* PTEST */
+ //write_log ("PTEST @$%lx\n", m68k_getpc());
+ return;
+ }
+ } else if ((opcode & 0x0FB8) == 0x588) {
+ /* PLPA */
+ if (currprefs.cpu_model == 68060) {
+ write_log("PLPA\n");
+ return;
+ }
+ } else if (opcode == 0xff00 && extra == 0x01c0) {
+ /* LPSTOP */
+ if (currprefs.cpu_model == 68060) {
+ write_log("LPSTOP\n");
+ return;
+ }
+ }
+ m68k_setpc (regs, m68k_getpc (regs) - 2);
+ op_illg (opcode, regs);
}
#endif
static void do_trace (void)
{
- if (regs.t0 && currprefs.cpu_level >= 2) {
+ if (regs.t0 && currprefs.cpu_model >= 68020) {
uae_u16 opcode;
/* should also include TRAP, CHK, SR modification FPcc */
/* probably never used so why bother */
#endif
-#ifndef CPUEMU_5
+#ifndef CPUEMU_11
static void m68k_run_1 (void)
{
if (do_specialties (cpu_cycles, r))
return;
}
- if (!currprefs.cpu_compatible || (currprefs.cpu_cycle_exact && currprefs.cpu_level == 0))
+ if (!currprefs.cpu_compatible || (currprefs.cpu_cycle_exact && currprefs.cpu_model == 68000))
return;
}
}
-#endif /* CPUEMU_5 */
+#endif /* CPUEMU_11 */
-#ifndef CPUEMU_6
+#ifndef CPUEMU_12
static void m68k_run_1_ce (void)
{
if (do_specialties (0, r))
return;
}
- if (!currprefs.cpu_cycle_exact || currprefs.cpu_level > 0)
+ if (!currprefs.cpu_cycle_exact || currprefs.cpu_model > 68000)
return;
}
}
}
#endif
#ifndef JIT
- run_func = currprefs.cpu_level == 0 && currprefs.cpu_cycle_exact ? m68k_run_1_ce :
- currprefs.cpu_level == 0 && currprefs.cpu_compatible ? m68k_run_1 :
+ run_func = currprefs.cpu_model == 68000 && currprefs.cpu_cycle_exact ? m68k_run_1_ce :
+ currprefs.cpu_model == 68000 && currprefs.cpu_compatible ? m68k_run_1 :
currprefs.cpu_compatible ? m68k_run_2p : m68k_run_2;
#else
if (mmu_enabled && !currprefs.cachesize) {
run_func = m68k_run_mmu;
} else {
- run_func = currprefs.cpu_cycle_exact && currprefs.cpu_level == 0 ? m68k_run_1_ce :
- currprefs.cpu_compatible > 0 && currprefs.cpu_level == 0 ? m68k_run_1 :
- currprefs.cpu_level >= 2 && currprefs.cachesize ? m68k_run_2a :
+ run_func = currprefs.cpu_cycle_exact && currprefs.cpu_model == 68000 ? m68k_run_1_ce :
+ currprefs.cpu_compatible > 0 && currprefs.cpu_model == 68000 ? m68k_run_1 :
+ currprefs.cpu_model >= 68020 && currprefs.cachesize ? m68k_run_2a :
currprefs.cpu_compatible ? m68k_run_2p : m68k_run_2;
}
#endif
*nextpc = m68k_getpc (®s) + m68kpc_offset;
}
+static int m2cregn[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 0x800, 0x801, 0x802, 0x803, 0x804, 0x805, 0x806, 0x807, 0x808, -1 };
+static char *m2cregs[] = { "SFC ", "DFC ", "CACR", "TC ", "ITT0", "ITT1", "DTT0", "DTT1", "BUSC",
+ "USP ", "VBR ", "CAAR", "MSP ", "ISP ", "MMUS", "URP ", "SRP ", "PCR ", 0 };
+
+static uae_u32 val_move2c (int regno)
+{
+ switch (regno) {
+ case 0: return regs.sfc;
+ case 1: return regs.dfc;
+ case 2: return cacr;
+ case 3: return tc;
+ case 4: return itt0;
+ case 5: return itt1;
+ case 6: return dtt0;
+ case 7: return dtt1;
+ case 8: return buscr;
+ case 0x800: return regs.usp;
+ case 0x801: return regs.vbr;
+ case 0x802: return caar;
+ case 0x803: return regs.msp;
+ case 0x804: return regs.isp;
+ case 0x805: return mmusr;
+ case 0x806: return urp;
+ case 0x807: return srp;
+ case 0x808: return regs.pcr | MC68060_PCR;
+ default: return 0;
+ }
+}
+
void m68k_dumpstate (void *f, uaecptr *nextpc)
{
- int i;
+ int i, j;
for (i = 0; i < 8; i++){
- f_out (f, "D%d: %08lx ", i, m68k_dreg(®s, i));
+ f_out (f, " D%d %08lX ", i, m68k_dreg(®s, i));
if ((i & 3) == 3) f_out (f, "\n");
}
for (i = 0; i < 8; i++){
- f_out (f, "A%d: %08lx ", i, m68k_areg(®s, i));
+ f_out (f, " A%d %08lX ", i, m68k_areg(®s, i));
if ((i & 3) == 3) f_out (f, "\n");
}
if (regs.s == 0) regs.usp = m68k_areg(®s, 7);
if (regs.s && regs.m) regs.msp = m68k_areg(®s, 7);
if (regs.s && regs.m == 0) regs.isp = m68k_areg(®s, 7);
- f_out (f, "USP=%08lx ISP=%08lx MSP=%08lx VBR=%08lx\n",
- regs.usp,regs.isp,regs.msp,regs.vbr);
+ j = 0;
+ for (i = 0; m2cregn[i] >= 0; i++) {
+ if (!movec_illg(m2cregn[i])) {
+ if (j > 0 && (j % 4) == 0)
+ f_out(f, "\n");
+ f_out (f, "%s %08.8X ", m2cregs[i], val_move2c(m2cregn[i]));
+ j++;
+ }
+ }
+ if (j > 0)
+ f_out (f, "\n");
f_out (f, "T=%d%d S=%d M=%d X=%d N=%d Z=%d V=%d C=%d IMASK=%d STP=%d\n",
regs.t1, regs.t0, regs.s, regs.m,
GET_XFLG(®s.ccrflags), GET_NFLG(®s.ccrflags), GET_ZFLG(®s.ccrflags),
GET_VFLG(®s.ccrflags), GET_CFLG(®s.ccrflags),
regs.intmask, regs.stopped);
#ifdef FPUEMU
- if (currprefs.cpu_level >= 2) {
+ if (currprefs.fpu_model) {
uae_u32 fpsr;
for (i = 0; i < 8; i++){
f_out (f, "FP%d: %g ", i, regs.fp[i]);
(fpsr & 0x1000000) != 0);
}
#endif
- if (currprefs.cpu_compatible) {
+ if (currprefs.cpu_compatible && currprefs.cpu_model == 68000) {
struct instr *dp;
struct mnemolookup *lookup1, *lookup2;
dp = table68k + regs.irc;
uae_u8 *restore_cpu (uae_u8 *src)
{
- int i,model,flags;
+ int i, flags, model;
uae_u32 l;
- model = restore_u32();
- switch (model) {
- case 68000:
- changed_prefs.cpu_level = 0;
- break;
- case 68010:
- changed_prefs.cpu_level = 1;
- break;
- case 68020:
- changed_prefs.cpu_level = 2;
- break;
- case 68040:
- changed_prefs.cpu_level = 4;
- break;
- case 68060:
- changed_prefs.cpu_level = 6;
- break;
- default:
- write_log ("Unknown cpu type %d\n", model);
- break;
- }
-
+ changed_prefs.cpu_model = model = restore_u32();
flags = restore_u32();
changed_prefs.address_space_24 = 0;
if (flags & CPUTYPE_EC)
changed_prefs.address_space_24 = 1;
if (model > 68000)
changed_prefs.cpu_compatible = 0;
- currprefs.cpu_level = changed_prefs.cpu_level;
currprefs.address_space_24 = changed_prefs.address_space_24;
currprefs.cpu_compatible = changed_prefs.cpu_compatible;
currprefs.cpu_cycle_exact = changed_prefs.cpu_cycle_exact;
dstbak = dst = dstptr;
else
dstbak = dst = malloc(4+4+15*4+4+4+4+4+2+4+4+4+4+4+4+4);
- model = cpumodel[currprefs.cpu_level];
+ model = currprefs.cpu_model;
save_u32 (model); /* MODEL */
save_u32 (currprefs.address_space_24 ? 1 : 0); /* FLAGS */
for(i = 0;i < 15; i++) save_u32 (regs.regs[i]); /* D0-D7 A0-A6 */
hwnd = GetDlgItem(hDlg, IDC_DBG_PREFETCH);
EnableWindow(hwnd, FALSE);
}
- if (currprefs.cpu_level < 2) {
+ if (currprefs.cpu_model < 68020) {
hwnd = GetDlgItem(hDlg, IDC_DBG_FPREG);
EnableWindow(hwnd, FALSE);
hwnd = GetDlgItem(hDlg, IDC_DBG_FPSR);
break;
}
- if( lockcnt )
+ if(lockcnt)
{
#ifdef _DEBUG
DebugBreak();
return 1;
}
- if( type == secondary_surface && DirectDrawState.flipping != single_buffer )
+ if(type == secondary_surface && DirectDrawState.flipping != single_buffer)
{
- IDirectDrawSurface7_Restore( DirectDrawState.primary.surface );
+ IDirectDrawSurface7_Restore(DirectDrawState.primary.surface);
}
while (FAILED(ddrval = IDirectDrawSurface7_Lock(surface, NULL, surfacedesc, DDLOCK_SURFACEMEMORYPTR | DDLOCK_WAIT, NULL)))
#define IDC_BLITIMM 1174
#define IDC_LORES 1176
#define IDC_VSYNC 1177
-#define IDC_AFULLSCREEN 1178
#define IDC_LORES_SMOOTHED 1179
#define IDC_FRAMERATE 1185
#define IDC_RATETEXT 1186
#define IDC_LM_SCANLINES 1191
#define IDC_INPUTSPEEDM 1191
#define IDC_P96RAM 1192
-#define IDC_PFULLSCREEN 1192
#define IDC_P96MEM 1193
#define IDC_DA_SLIDER 1193
#define IDC_FRAMERATE2 1194
#define IDC_CPU3 1203
#define IDC_CPU4 1204
#define IDC_CPU5 1205
-#define IDC_CPU6 1206
-#define IDC_SPEED 1207
+#define IDC_FPU1 1206
+#define IDC_FPU2 1207
+#define IDC_FPU3 1208
#define IDC_CS_HOST 1209
#define IDC_CS_68000 1210
#define IDC_CS_ADJUSTABLE 1211
#define IDC_GENLOCK 1220
#define IDC_COMPATIBLE_FPU 1221
#define IDC_FASTERRTG 1221
+#define IDC_COMPATIBLE24 1222
+#define IDC_SPEED 1223
#define IDC_SOUNDSETTINGS 1229
#define IDC_8BIT 1230
#define IDC_16BIT 1231
#ifndef APSTUDIO_READONLY_SYMBOLS
#define _APS_NO_MFC 1
#define _APS_3D_CONTROLS 1
-#define _APS_NEXT_RESOURCE_VALUE 258
+#define _APS_NEXT_RESOURCE_VALUE 253
#define _APS_NEXT_COMMAND_VALUE 40026
#define _APS_NEXT_CONTROL_VALUE 1761
#define _APS_NEXT_SYMED_VALUE 101
#define IDC_CPU3 1203
#define IDC_CPU4 1204
#define IDC_CPU5 1205
-#define IDC_CPU6 1206
-#define IDC_SPEED 1207
#define IDC_CS_HOST 1209
#define IDC_CS_68000 1210
#define IDC_CS_ADJUSTABLE 1211
#define IDC_GENLOCK 1220
#define IDC_COMPATIBLE_FPU 1221
#define IDC_FASTERRTG 1221
+#define IDC_COMPATIBLE24 1222
+#define IDC_SPEED 1223
+#define IDC_FPU0 1224
+#define IDC_FPU1 1225
+#define IDC_FPU2 1226
+#define IDC_FPU3 1227
#define IDC_SOUNDSETTINGS 1229
#define IDC_8BIT 1230
#define IDC_16BIT 1231
// Generated from the TEXTINCLUDE 2 resource.
//
#include "afxres.h"
-
/////////////////////////////////////////////////////////////////////////////
#undef APSTUDIO_READONLY_SYMBOLS
EDITTEXT IDC_MBRAM2,243,142,30,12,ES_CENTER | ES_READONLY
END
-IDD_CPU DIALOGEX 0, 0, 300, 192
+IDD_CPU DIALOGEX 0, 0, 300, 226
STYLE DS_LOCALEDIT | DS_SETFONT | DS_3DLOOK | DS_CONTROL | WS_CHILD
FONT 8, "MS Sans Serif", 0, 0, 0x0
BEGIN
- GROUPBOX "CPU",IDC_STATIC,5,3,81,148,BS_LEFT
- CONTROL "68000",IDC_CPU0,"Button",BS_AUTORADIOBUTTON | WS_GROUP | WS_TABSTOP,10,16,63,10
- CONTROL "68010",IDC_CPU1,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,10,31,65,10
- CONTROL "68EC020",IDC_CPU2,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,10,46,65,10
- CONTROL "68EC020 + FPU",IDC_CPU3,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,10,61,68,10
- CONTROL "68020",IDC_CPU4,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,10,76,63,10
- CONTROL "68020 + FPU",IDC_CPU5,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,10,91,64,10
- CONTROL "68040",IDC_CPU6,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,10,106,66,10
+ GROUPBOX "CPU",IDC_STATIC,5,3,81,139,BS_LEFT
+ CONTROL "68000",IDC_CPU0,"Button",BS_AUTORADIOBUTTON | WS_GROUP | WS_TABSTOP,13,16,63,10
+ CONTROL "68010",IDC_CPU1,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,13,30,65,10
+ CONTROL "68020",IDC_CPU2,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,13,44,63,10
+ CONTROL "68030",IDC_CPU3,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,13,58,64,10
+ CONTROL "68040",IDC_CPU4,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,13,72,66,10
+ CONTROL "68060",IDC_CPU5,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,13,85,66,10
CONTROL "More compatible [] Emulate 68000's prefetch registers. More compatible but slower.",IDC_COMPATIBLE,
- "Button",BS_AUTOCHECKBOX | BS_LEFT | WS_GROUP | WS_TABSTOP,10,124,73,8
+ "Button",BS_AUTOCHECKBOX | BS_LEFT | WS_GROUP | WS_TABSTOP,10,114,73,8
CONTROL "JIT [] Enable just-in-time CPU emulator. Significantly increases the speed of the CPU emulation. Requires 68020 or 68040 CPU.",IDC_JITENABLE,
- "Button",BS_AUTOCHECKBOX | WS_TABSTOP,10,137,73,10
+ "Button",BS_AUTOCHECKBOX | WS_TABSTOP,10,127,73,10
GROUPBOX "CPU Emulation Speed",IDC_STATIC,90,3,205,90
CONTROL "Fastest possible, but maintain chipset timing",IDC_CS_HOST,
"Button",BS_AUTORADIOBUTTON | BS_LEFT | WS_GROUP | WS_TABSTOP,95,18,195,10
CONTROL "Indirect",IDC_TRUST1,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,230,155,45,10
CONTROL "After RTG",IDC_TRUST2,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,230,168,59,10
CONTROL "More compatible [] More compatible but slower FPU emulation.",IDC_COMPATIBLE_FPU,
- "Button",BS_AUTOCHECKBOX | BS_LEFT | WS_GROUP | WS_TABSTOP,9,169,73,10
- GROUPBOX "FPU",IDC_STATIC,6,155,81,32,BS_LEFT
+ "Button",BS_AUTOCHECKBOX | BS_LEFT | WS_GROUP | WS_TABSTOP,9,206,73,10
+ GROUPBOX "FPU",IDC_STATIC,6,144,81,76,BS_LEFT
+ CONTROL "24-bit addressing",IDC_COMPATIBLE24,"Button",BS_AUTOCHECKBOX | BS_LEFT | WS_GROUP | WS_TABSTOP,10,100,73,8
+ CONTROL "None",IDC_FPU0,"Button",BS_AUTORADIOBUTTON | WS_GROUP | WS_TABSTOP,14,154,63,10
+ CONTROL "68881",IDC_FPU1,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,14,166,63,10
+ CONTROL "68882",IDC_FPU2,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,14,179,63,10
+ CONTROL "CPU internal",IDC_FPU3,"Button",BS_AUTORADIOBUTTON | WS_TABSTOP,14,192,63,10
END
IDD_FLOPPY DIALOGEX 0, 0, 300, 240
BEGIN
EDITTEXT IDC_DBG_OUTPUT1,1,79,370,205,ES_MULTILINE | ES_AUTOVSCROLL | ES_READONLY | ES_WANTRETURN | WS_VSCROLL | NOT WS_TABSTOP
EDITTEXT IDC_DBG_OUTPUT2,1,79,370,205,ES_MULTILINE | ES_AUTOVSCROLL | ES_READONLY | ES_WANTRETURN | WS_VSCROLL | NOT WS_TABSTOP
- LISTBOX IDC_DBG_MEM,1,92,370,205,LBS_OWNERDRAWFIXED | LBS_HASSTRINGS | LBS_NOINTEGRALHEIGHT
- LISTBOX IDC_DBG_DASM,1,92,370,205,LBS_OWNERDRAWFIXED | LBS_HASSTRINGS | LBS_NOINTEGRALHEIGHT
+ LISTBOX IDC_DBG_MEM,1,92,370,192,LBS_OWNERDRAWFIXED | LBS_HASSTRINGS | LBS_NOINTEGRALHEIGHT
+ LISTBOX IDC_DBG_DASM,1,92,370,192,LBS_OWNERDRAWFIXED | LBS_HASSTRINGS | LBS_NOINTEGRALHEIGHT
EDITTEXT IDC_DBG_MEMINPUT,1,79,36,12,ES_AUTOHSCROLL | ES_WANTRETURN
EDITTEXT IDC_DBG_INPUT,1,285,354,12,ES_AUTOHSCROLL | ES_WANTRETURN
PUSHBUTTON "?",IDC_DBG_HELP,356,285,15,12,NOT WS_TABSTOP
"resource.\0"
END
-
3 TEXTINCLUDE
BEGIN
"\r\0"
END
+2 TEXTINCLUDE
+BEGIN
+ "#include ""afxres.h""\r\0"
+END
+
#endif // APSTUDIO_INVOKED
#endif // Finnish resources
// Generated from the TEXTINCLUDE 3 resource.
//
-
/////////////////////////////////////////////////////////////////////////////
#endif // not APSTUDIO_INVOKED
#define UAESERIAL /* uaeserial.device emulation */
#define FPUEMU /* FPU emulation */
#define CPUEMU_0 /* generic 680x0 emulation */
-#define CPUEMU_5 /* 68000+prefetch emulation */
-#define CPUEMU_6 /* cycle-exact cpu&blitter */
+#define CPUEMU_11 /* 68000+prefetch emulation */
+#define CPUEMU_12 /* cycle-exact cpu&blitter */
#define ACTION_REPLAY /* Action Replay 1/2/3 support */
#define PICASSO96 /* Picasso96 display card emulation */
#define BSDSOCKET /* bsdsocket.library emulation */
#define OPENGL
#endif
#define CAPS
-#define CPUEMU_6
-#define CPUEMU_5
+#define CPUEMU_12
+#define CPUEMU_11
#endif
#define GETBDM(x) (((x) - ((x / 10000) * 10000)) / 100)
#define GETBDD(x) ((x) % 100)
-#define WINUAEBETA 1
+#define WINUAEBETA 2
#define WINUAEPUBLICBETA 1
-#define WINUAEDATE MAKEBD(2007, 3, 28)
+#define WINUAEDATE MAKEBD(2007, 3, 30)
#define IHF_WINDOWHIDDEN 6
#define NORMAL_WINDOW_STYLE (WS_VISIBLE | WS_BORDER | WS_CAPTION | WS_MINIMIZEBOX | WS_SYSMENU)
void S2X_init (int dw, int dh, int aw, int ah, int mult, int ad, int dd)
{
- int flags;
+ int flags = 0;
HRESULT ddrval;
- flags = usedfilter->x[mult];
- if (mult) {
+ if (!currprefs.gfx_filter || !usedfilter) {
+ usedfilter = &uaefilters[0];
+ mult = 1;
+ } else if (mult) {
if ((ad == 16 && !(flags & UAE_FILTER_MODE_16)) || (ad == 32 && !(flags & UAE_FILTER_MODE_32))) {
usedfilter = &uaefilters[0];
mult = 1;
sptr = gfxvidinfo.bufmem;
endsptr = gfxvidinfo.realbufmem + (amiga_height - 1) * 3 * gfxvidinfo.rowbytes;
- v = currprefs.gfx_filter_horiz_offset;
+ v = currprefs.gfx_filter ? currprefs.gfx_filter_horiz_offset : 0;
v += (dst_width / scale - amiga_width) / 8;
sptr += (int)(-v * 4.0 / 10.0) * (amiga_depth / 8);
aw -= (int)(-v * 4.0 / 10);
- v = currprefs.gfx_filter_vert_offset;
+ v = currprefs.gfx_filter ? currprefs.gfx_filter_vert_offset : 0;
v += (dst_height / scale - amiga_height) / 8;
sptr += (int)(-v * 4.0 / 10.0) * gfxvidinfo.rowbytes;
ah -= (int)(-v * 4.0 / 10);
if (aw < 16)
return;
- if (currprefs.gfx_filter_horiz_zoom || currprefs.gfx_filter_vert_zoom ||
+ if (currprefs.gfx_filter && (currprefs.gfx_filter_horiz_zoom || currprefs.gfx_filter_vert_zoom ||
currprefs.gfx_filter_horiz_zoom_mult != 1000 ||
- currprefs.gfx_filter_vert_zoom_mult != 1000) {
+ currprefs.gfx_filter_vert_zoom_mult != 1000)) {
int wz = dst_width * currprefs.gfx_filter_horiz_zoom_mult / 1000;
int hz = dst_height * currprefs.gfx_filter_vert_zoom_mult / 1000;
wz += currprefs.gfx_filter_horiz_zoom / 4;
}
- if (ok == 0) {
+ if (ok == 0 && currprefs.gfx_filter) {
usedfilter = &uaefilters[0];
changed_prefs.gfx_filter = usedfilter->type;
}
currentmode->flags |= DM_SWSCALE;
if (currentmode->current_depth < 15)
currentmode->current_depth = 16;
+ } else if (!usedfilter && currentmode->current_depth >= 15) {
+ ;//currentmode->flags |= DM_SWSCALE;
}
#endif
}
case IDC_DF1WPQ:
case IDC_EJECT1Q:
case IDC_DF1QQ:
- ret = FloppyDlgProc (hDlg, msg, wParam, lParam);
+ if (currentpage == QUICKSTART_ID)
+ ret = FloppyDlgProc (hDlg, msg, wParam, lParam);
break;
case IDC_QUICKSTART_SETCONFIG:
load_quickstart (hDlg, 1);
{
int enable = workprefs.cpu_cycle_exact ? FALSE : TRUE;
-#if !defined (CPUEMU_6)
+#if !defined (CPUEMU_12)
ew (hDlg, IDC_CYCLEEXACT, FALSE);
#endif
ew (hDlg, IDC_FASTCOPPER, enable);
if (workprefs.cpu_cycle_exact != n) {
workprefs.cpu_cycle_exact = workprefs.blitter_cycle_exact = n;
if (n) {
- if (workprefs.cpu_level == 0) {
+ if (workprefs.cpu_model == 68000) {
workprefs.cpu_compatible = 1;
workprefs.m68k_speed = 0;
}
return MiscDlgProc (hDlg, msg, wParam, lParam);
}
-static int cpu_ids[] = { IDC_CPU0, IDC_CPU0, IDC_CPU1, IDC_CPU1, IDC_CPU2, IDC_CPU4, IDC_CPU3, IDC_CPU5, IDC_CPU6, IDC_CPU6 };
+static int cpu_ids[] = { IDC_CPU0, IDC_CPU1, IDC_CPU2, IDC_CPU3, IDC_CPU4, IDC_CPU5 };
+static int fpu_ids[] = { IDC_FPU0, IDC_FPU1, IDC_FPU2, IDC_FPU3 };
static int trust_ids[] = { IDC_TRUST0, IDC_TRUST1, IDC_TRUST1, IDC_TRUST2 };
static void enable_for_cpudlg (HWND hDlg)
{
BOOL enable = FALSE, enable2 = FALSE;
BOOL cpu_based_enable = FALSE;
+ BOOL fpu;
/* These four items only get enabled when adjustable CPU style is enabled */
ew (hDlg, IDC_SPEED, workprefs.m68k_speed > 0);
- ew (hDlg, IDC_CS_CPU_TEXT, (!workprefs.cpu_cycle_exact || workprefs.cpu_level > 0) && workprefs.m68k_speed > 0);
- ew (hDlg, IDC_CS_CHIPSET_TEXT, (!workprefs.cpu_cycle_exact || workprefs.cpu_level > 0) && workprefs.m68k_speed > 0);
- ew (hDlg, IDC_CS_HOST, !workprefs.cpu_cycle_exact || workprefs.cpu_level > 0);
- ew (hDlg, IDC_CS_68000, !workprefs.cpu_cycle_exact || workprefs.cpu_level > 0);
- ew (hDlg, IDC_CS_ADJUSTABLE, !workprefs.cpu_cycle_exact || workprefs.cpu_level > 0);
+ ew (hDlg, IDC_COMPATIBLE24, workprefs.cpu_model == 68020);
+ ew (hDlg, IDC_CS_CPU_TEXT, (!workprefs.cpu_cycle_exact || workprefs.cpu_model > 68000) && workprefs.m68k_speed > 0);
+ ew (hDlg, IDC_CS_CHIPSET_TEXT, (!workprefs.cpu_cycle_exact || workprefs.cpu_model > 68000) && workprefs.m68k_speed > 0);
+ ew (hDlg, IDC_CS_HOST, !workprefs.cpu_cycle_exact || workprefs.cpu_model > 68000);
+ ew (hDlg, IDC_CS_68000, !workprefs.cpu_cycle_exact || workprefs.cpu_model > 68000);
+ ew (hDlg, IDC_CS_ADJUSTABLE, !workprefs.cpu_cycle_exact || workprefs.cpu_model > 68000);
ew (hDlg, IDC_CPUTEXT, workprefs.m68k_speed > 0 );
ew (hDlg, IDC_CPUIDLE, workprefs.m68k_speed != 0 ? TRUE : FALSE);
#if !defined(CPUEMU_0) || defined(CPUEMU_68000_ONLY)
ew (hDlg, IDC_CPU3, FALSE);
ew (hDlg, IDC_CPU4, FALSE);
ew (hDlg, IDC_CPU5, FALSE);
- ew (hDlg, IDC_CPU6, FALSE);
#endif
- cpu_based_enable = workprefs.cpu_level >= 2 &&
+ cpu_based_enable = workprefs.cpu_model >= 68020 &&
workprefs.address_space_24 == 0;
enable = cpu_based_enable && workprefs.cachesize;
ew (hDlg, IDC_FORCE, enable);
ew (hDlg, IDC_JITENABLE, cpu_based_enable);
ew (hDlg, IDC_COMPATIBLE, !workprefs.cpu_cycle_exact && !workprefs.cachesize);
- ew (hDlg, IDC_COMPATIBLE_FPU, workprefs.cpu_level >= 3);
+ ew (hDlg, IDC_COMPATIBLE_FPU, workprefs.fpu_model > 0);
+
+ fpu = TRUE;
+ if (workprefs.cpu_model < 68020 || workprefs.cpu_model > 68030)
+ fpu = FALSE;
+ ew (hDlg, IDC_FPU1, fpu);
+ ew (hDlg, IDC_FPU2, fpu);
+ ew (hDlg, IDC_FPU3, workprefs.cpu_model >= 68040);
#ifdef JIT
- if( enable )
- {
- if(!canbang)
- {
+ if(enable) {
+ if (!canbang) {
workprefs.compforcesettings = TRUE;
workprefs.comptrustbyte = 1;
workprefs.comptrustword = 1;
workprefs.comptrustlong = 1;
workprefs.comptrustnaddr= 1;
}
- }
- else
- {
+ } else {
workprefs.cachesize = 0; // Disable JIT
}
#endif
char cache[8] = "";
BOOL enable = FALSE;
BOOL cpu_based_enable = FALSE;
+ int cpu;
SendDlgItemMessage (hDlg, IDC_SPEED, TBM_SETPOS, TRUE, workprefs.m68k_speed <= 0 ? 1 : workprefs.m68k_speed / CYCLE_UNIT );
SetDlgItemInt( hDlg, IDC_CPUTEXT, workprefs.m68k_speed <= 0 ? 1 : workprefs.m68k_speed / CYCLE_UNIT, FALSE );
CheckDlgButton (hDlg, IDC_COMPATIBLE, workprefs.cpu_compatible);
+ CheckDlgButton (hDlg, IDC_COMPATIBLE24, workprefs.address_space_24);
CheckDlgButton (hDlg, IDC_COMPATIBLE_FPU, workprefs.fpu_strict);
SendDlgItemMessage (hDlg, IDC_CPUIDLE, TBM_SETPOS, TRUE, workprefs.cpu_idle == 0 ? 0 : 12 - workprefs.cpu_idle / 15);
- CheckRadioButton (hDlg, IDC_CPU0, IDC_CPU6, cpu_ids[workprefs.cpu_level * 2 + !workprefs.address_space_24]);
+ cpu = (workprefs.cpu_model - 68000) / 10;
+ if (cpu >= 5)
+ cpu--;
+ CheckRadioButton (hDlg, IDC_CPU0, IDC_CPU5, cpu_ids[cpu]);
+ CheckRadioButton (hDlg, IDC_FPU0, IDC_FPU3, fpu_ids[workprefs.fpu_model == 0 ? 0 : (workprefs.fpu_model == 68881 ? 1 : (workprefs.fpu_model == 68882 ? 2 : 3))]);
if (workprefs.m68k_speed == -1)
CheckRadioButton(hDlg, IDC_CS_HOST, IDC_CS_ADJUSTABLE, IDC_CS_HOST);
else
CheckRadioButton(hDlg, IDC_CS_HOST, IDC_CS_ADJUSTABLE, IDC_CS_ADJUSTABLE);
- cpu_based_enable = (workprefs.cpu_level >= 2) && (workprefs.address_space_24 == 0);
+ cpu_based_enable = (workprefs.cpu_model >= 68020) && (workprefs.address_space_24 == 0);
enable = cpu_based_enable && workprefs.cachesize;
#ifdef JIT
if(enable) {
- if(!canbang) {
+ if (!canbang) {
workprefs.compforcesettings = TRUE;
workprefs.comptrustbyte = 1;
workprefs.comptrustword = 1;
static void values_from_cpudlg (HWND hDlg)
{
- int newcpu, newtrust, oldcache, jitena;
+ int newcpu, newfpu, newtrust, oldcache, jitena;
static int cachesize_prev;
workprefs.cpu_compatible = workprefs.cpu_cycle_exact | (IsDlgButtonChecked (hDlg, IDC_COMPATIBLE) ? 1 : 0);
workprefs.fpu_strict = IsDlgButtonChecked (hDlg, IDC_COMPATIBLE_FPU) ? 1 : 0;
+ workprefs.address_space_24 = IsDlgButtonChecked (hDlg, IDC_COMPATIBLE24) ? 1 : 0;
workprefs.m68k_speed = IsDlgButtonChecked (hDlg, IDC_CS_HOST) ? -1
: IsDlgButtonChecked (hDlg, IDC_CS_68000) ? 0
: SendMessage (GetDlgItem (hDlg, IDC_SPEED), TBM_GETPOS, 0, 0) * CYCLE_UNIT;
- newcpu = (IsDlgButtonChecked (hDlg, IDC_CPU0) ? 0
- : IsDlgButtonChecked (hDlg, IDC_CPU1) ? 1
- : IsDlgButtonChecked (hDlg, IDC_CPU2) ? 2
- : IsDlgButtonChecked (hDlg, IDC_CPU3) ? 3
- : IsDlgButtonChecked (hDlg, IDC_CPU4) ? 4
- : IsDlgButtonChecked (hDlg, IDC_CPU5) ? 5 : 6);
+ newcpu = IsDlgButtonChecked (hDlg, IDC_CPU0) ? 68000
+ : IsDlgButtonChecked (hDlg, IDC_CPU1) ? 68010
+ : IsDlgButtonChecked (hDlg, IDC_CPU2) ? 68020
+ : IsDlgButtonChecked (hDlg, IDC_CPU3) ? 68030
+ : IsDlgButtonChecked (hDlg, IDC_CPU4) ? 68040
+ : IsDlgButtonChecked (hDlg, IDC_CPU5) ? 68060 : 0;
+ newfpu = IsDlgButtonChecked (hDlg, IDC_FPU0) ? 0
+ : IsDlgButtonChecked (hDlg, IDC_FPU1) ? 1
+ : IsDlgButtonChecked (hDlg, IDC_FPU2) ? 2
+ : IsDlgButtonChecked (hDlg, IDC_FPU3) ? 3 : 0;
+
/* When switching away from 68000, disable 24 bit addressing. */
- switch( newcpu )
+ workprefs.cpu_model = newcpu;
+ switch(newcpu)
{
- case 0: // 68000
- case 1: // 68010
- case 2: // 68EC020
- case 3: // 68EC020+FPU
+ case 68000:
+ case 68010:
+ workprefs.fpu_model = 0;
workprefs.address_space_24 = 1;
- workprefs.cpu_level = newcpu;
if (newcpu == 0 && workprefs.cpu_cycle_exact)
workprefs.m68k_speed = 0;
break;
-
- case 4: // 68020
- case 5: // 68020+FPU
- case 6: // 68040
+ case 68020:
+ workprefs.fpu_model = newfpu == 0 ? 0 : (newfpu == 2 ? 68882 : 68881);
+ break;
+ case 68030:
+ workprefs.address_space_24 = 0;
+ workprefs.fpu_model = newfpu == 0 ? 0 : (newfpu == 2 ? 68882 : 68881);
+ break;
+ case 68040:
+ workprefs.fpu_model = newfpu ? 68040 : 0;
+ workprefs.address_space_24 = 0;
+ if (workprefs.fpu_model)
+ workprefs.fpu_model = 68040;
+ break;
+ case 68060:
+ workprefs.fpu_model = newfpu ? 68060 : 0;
workprefs.address_space_24 = 0;
- workprefs.cpu_level = newcpu - 2;
break;
}
- newtrust = (IsDlgButtonChecked( hDlg, IDC_TRUST0 ) ? 0
- : IsDlgButtonChecked( hDlg, IDC_TRUST1 ) ? 1 : 3 );
+ newtrust = (IsDlgButtonChecked(hDlg, IDC_TRUST0) ? 0
+ : IsDlgButtonChecked(hDlg, IDC_TRUST1) ? 1 : 3);
workprefs.comptrustbyte = newtrust;
workprefs.comptrustword = newtrust;
workprefs.comptrustlong = newtrust;
workprefs.comptrustnaddr= newtrust;
- workprefs.compforcesettings = IsDlgButtonChecked( hDlg, IDC_FORCE );
- workprefs.compnf = IsDlgButtonChecked( hDlg, IDC_NOFLAGS );
- workprefs.compfpu = IsDlgButtonChecked( hDlg, IDC_JITFPU );
- workprefs.comp_hardflush = IsDlgButtonChecked( hDlg, IDC_HARDFLUSH );
- workprefs.comp_constjump = IsDlgButtonChecked( hDlg, IDC_CONSTJUMP );
+ workprefs.compforcesettings = IsDlgButtonChecked(hDlg, IDC_FORCE);
+ workprefs.compnf = IsDlgButtonChecked(hDlg, IDC_NOFLAGS);
+ workprefs.compfpu = IsDlgButtonChecked(hDlg, IDC_JITFPU);
+ workprefs.comp_hardflush = IsDlgButtonChecked(hDlg, IDC_HARDFLUSH);
+ workprefs.comp_constjump = IsDlgButtonChecked(hDlg, IDC_CONSTJUMP);
#ifdef JIT
oldcache = workprefs.cachesize;
if (workprefs.cachesize > 0)
workprefs.cpu_compatible = 0;
-
if (pages[KICKSTART_ID])
SendMessage(pages[KICKSTART_ID], WM_USER, 0, 0 );
if (pages[DISPLAY_ID])
static int getfloppybox (HWND hDlg, int f_text, char *out, int maxlen)
{
LRESULT val;
+ char *p1, *p2, *p;
+ char *tmp;
+ int i;
out[0] = 0;
val = SendDlgItemMessage (hDlg, f_text, CB_GETCURSEL, 0, 0L);
- if (val == CB_ERR) {
- char *p1, *p2;
- char *tmp;
- SendDlgItemMessage (hDlg, f_text, WM_GETTEXT, (WPARAM)maxlen, (LPARAM)out);
- tmp = xmalloc (maxlen + 1);
- strcpy (tmp, out);
- p1 = strstr(tmp, " { ");
- p2 = strstr(tmp, " }");
- if (p1 && p2 && p2 > p1) {
- *p1 = 0;
- memset (out, 0, maxlen);
- memcpy (out, p1 + 3, p2 - p1 - 3);
- strcat (out, tmp);
- }
- xfree (tmp);
- } else {
- char *p = DISK_history_get (val);
-#if 0
+ if (val != CB_ERR)
val = SendDlgItemMessage (hDlg, f_text, CB_GETLBTEXT, (WPARAM)val, (LPARAM)out);
- if (val != CB_ERR && val > 0) {
-#endif
- if (p) {
- strcpy (out, p);
- if (out[0]) {
- /* add to top of list */
- DISK_history_add (out, -1);
- }
- } else {
- out[0] = 0;
+ else
+ SendDlgItemMessage (hDlg, f_text, WM_GETTEXT, (WPARAM)maxlen, (LPARAM)out);
+
+ tmp = xmalloc (maxlen + 1);
+ strcpy (tmp, out);
+ p1 = strstr(tmp, " { ");
+ p2 = strstr(tmp, " }");
+ if (p1 && p2 && p2 > p1) {
+ *p1 = 0;
+ memset (out, 0, maxlen);
+ memcpy (out, p1 + 3, p2 - p1 - 3);
+ strcat (out, tmp);
+ }
+ xfree (tmp);
+ i = 0;
+ while ((p = DISK_history_get(i))) {
+ if (!strcmp(p, out)) {
+ DISK_history_add (out, -1);
+ break;
}
+ i++;
}
return out[0] ? 1 : 0;
}
case IDC_DF1TEXTQ:
getfloppyname (hDlg, 1);
addfloppytype (hDlg, 1);
- addfloppyhistory (hDlg);
+ //addfloppyhistory (hDlg);
break;
case IDC_DF2TEXT:
getfloppyname (hDlg, 2);
>
</File>
<File
- RelativePath="..\..\cpuemu_5.c"
+ RelativePath="..\..\cpuemu_11.c"
>
</File>
<File
- RelativePath="..\..\cpuemu_6.c"
+ RelativePath="..\..\cpuemu_12.c"
>
</File>
<File
+Beta 2:
+
+- 10x+ performance increase during "decrunching" color effects when
+ no filters enabled and bitplanes disabled (background color only)
+- console debugger breakpoints sometimes continued immediately
+- quickstart "random" selection inside archives should be fixed
+- mousehack interrupt do not start multiple times anymore
+- all CPU-specific special registers added to debugger
+- CPU/FPU configuration rewrite.
+ - new FPU options: none/68881/68882/CPU internal
+ - 68030 (EC-version, 030-only MMU instructions are simply ignored)
+ - proper 68060 with FPU support. See NOTEs below!
+ - 68040/68060 without FPU allowed but note that 68060.library does
+ not appear to like non-FPU 68060s..
+ - no FPU+68000/68010 (technically possible but not worth the trouble)
+
+ 68060 NOTES: No working Setpatch and 68060.library = NO FPU.
+ 68060 has FPU disable bit that all real 68060 accelerators' boot ROM
+ set because KS task switching routine do not understand 68060's
+ FRESTORE/FSAVE frames. Setpatch+68060.library is the fix.
+
+ Real 68060 is also extremely slow without 68060.library because all
+ caches and other speed-up features are not enabled but this is
+ completely irrelevant in emulation.
+
+ You can use "C:CPU" command to check CPU/FPU status:
+ - Incorrect: "System: 68060 (INST: blahblah"
+ - Correct: "System 68060 68882 (INST: blahblah"
+ New setpatch (44.38 confirmed) support 68060.library directly, older
+ versions need dummy 68040.library (less than 1K in size)
+
+ NOTE2: FPU emulation emulates all 6888x instructions, even those that
+ were removed from real 68040/060.
+ !!! NOTE3: _EMULATED_ 68040 and 68060 HAVE EQUAL SPEED !!!
+
+
Beta 1:
- Chip set extra config load/save missed some models (crash when
rc.top = y;
rc.right = x + w;
rc.bottom = y + h;
- if (MonitorFromRect (&rc, MONITOR_DEFAULTTONULL) != NULL)
- SetWindowPos(hwnd, HWND_TOP, x, y, w, h, SWP_NOACTIVATE | SWP_DEFERERASE);
+ if (MonitorFromRect (&rc, MONITOR_DEFAULTTONULL) != NULL) {
+ SetForegroundWindow(hwnd);
+ SetWindowPos(hwnd, HWND_TOP, x, y, w, h, SWP_NOACTIVATE);
+
+ }
}
}
}
*out = 0;
if (consoleopen > 0) {
return console_get_gui (out, maxlen);
- } else {
- DWORD len,totallen;
+ } else if (consoleopen < 0) {
+ DWORD len, totallen;
*out = 0;
- totallen=0;
- while(maxlen>0) {
- ReadConsole(stdinput,out,1,&len,0);
+ totallen = 0;
+ while(maxlen > 0) {
+ ReadConsole(stdinput, out, 1, &len, 0);
if(*out == 13)
break;
out++;
maxlen--;
totallen++;
}
- *out=0;
+ *out = 0;
return totallen;
}
return 0;
{ i_CPUSHA, "CPUSHA" },
{ i_MOVE16, "MOVE16" },
+ { i_MMUOP30, "MMUOP30" },
{ i_MMUOP, "MMUOP" },
{ i_ILLG, "" },
};
%
% Fields on a line:
% 16 chars bitpattern :
-% CPU level / privildge level :
+% CPU level / privilege level :
% CPU level 0: 68000
% 1: 68010
% 2: 68020
+% 3: 68030
+% 4: 68020/68030+FPU
+% 5: 68040
+% 6: 68060 (not used)
% privilege level 0: not privileged
% 1: unprivileged only on 68000 (check regs.s)
% 2: privileged (check regs.s)
1110 1111 11ss sSSS:20:?????:?????:13: BFINS #1,s[!Areg,Apdi,Aipi,Immd,PC8r,PC16]
% floating point co processor
-1111 0010 00ss sSSS:30:?????:?????:11: FPP #1,s
-1111 0010 01ss sSSS:30:?????:?????:11: FDBcc #1,s[Areg-Dreg]
-1111 0010 01ss sSSS:30:?????:?????:11: FScc #1,s[!Areg,Immd,PC8r,PC16]
-1111 0010 0111 1010:30:?????:?????:10: FTRAPcc #1
-1111 0010 0111 1011:30:?????:?????:10: FTRAPcc #2
-1111 0010 0111 1100:30:?????:?????:00: FTRAPcc
-1111 0010 10KK KKKK:30:?????:?????:11: FBcc #K,#1
-1111 0010 11KK KKKK:30:?????:?????:11: FBcc #K,#2
-1111 0011 00ss sSSS:32:?????:?????:20: FSAVE s[!Dreg,Areg,Aipi,Immd,PC8r,PC16]
-1111 0011 01ss sSSS:32:?????:?????:10: FRESTORE s[!Dreg,Areg,Apdi,Immd]
+1111 0010 00ss sSSS:40:?????:?????:11: FPP #1,s
+1111 0010 01ss sSSS:40:?????:?????:11: FDBcc #1,s[Areg-Dreg]
+1111 0010 01ss sSSS:40:?????:?????:11: FScc #1,s[!Areg,Immd,PC8r,PC16]
+1111 0010 0111 1010:40:?????:?????:10: FTRAPcc #1
+1111 0010 0111 1011:40:?????:?????:10: FTRAPcc #2
+1111 0010 0111 1100:40:?????:?????:00: FTRAPcc
+1111 0010 10KK KKKK:40:?????:?????:11: FBcc #K,#1
+1111 0010 11KK KKKK:40:?????:?????:11: FBcc #K,#2
+1111 0011 00ss sSSS:42:?????:?????:20: FSAVE s[!Dreg,Areg,Aipi,Immd,PC8r,PC16]
+1111 0011 01ss sSSS:42:?????:?????:10: FRESTORE s[!Dreg,Areg,Apdi,Immd]
-1111 0101 iiii iSSS:40:?????:?????:11: MMUOP #i,s
+% 68030 MMU
+1111 0000 00ss sSSS:30:?????:?????:11: MMUOP30 #i,s
+% Misc MMU
+1111 0101 iiii iSSS:50:?????:?????:11: MMUOP #i,s
% 68040 instructions
-1111 0100 pp00 1rrr:42:-----:-----:02: CINVL #p,Ar
-1111 0100 pp01 0rrr:42:-----:-----:02: CINVP #p,Ar
-1111 0100 pp01 1rrr:42:-----:-----:00: CINVA #p
-1111 0100 pp10 1rrr:42:-----:-----:02: CPUSHL #p,Ar
-1111 0100 pp11 0rrr:42:-----:-----:02: CPUSHP #p,Ar
-1111 0100 pp11 1rrr:42:-----:-----:00: CPUSHA #p
+1111 0100 pp00 1rrr:52:-----:-----:02: CINVL #p,Ar
+1111 0100 pp01 0rrr:52:-----:-----:02: CINVP #p,Ar
+1111 0100 pp01 1rrr:52:-----:-----:00: CINVA #p
+1111 0100 pp10 1rrr:52:-----:-----:02: CPUSHL #p,Ar
+1111 0100 pp11 0rrr:52:-----:-----:02: CPUSHP #p,Ar
+1111 0100 pp11 1rrr:52:-----:-----:00: CPUSHA #p
% destination register number is encoded in the following word
-1111 0110 0010 0rrr:40:-----:-----:12: MOVE16 ArP,AxP
-1111 0110 00ss sSSS:40:-----:-----:12: MOVE16 s[Dreg-Aipi],L
-1111 0110 00dd dDDD:40:-----:-----:12: MOVE16 L,d[Areg-Aipi]
-1111 0110 00ss sSSS:40:-----:-----:12: MOVE16 s[Aind],L
-1111 0110 00dd dDDD:40:-----:-----:12: MOVE16 L,d[Aipi-Aind]
+1111 0110 0010 0rrr:50:-----:-----:12: MOVE16 ArP,AxP
+1111 0110 00ss sSSS:50:-----:-----:12: MOVE16 s[Dreg-Aipi],L
+1111 0110 00dd dDDD:50:-----:-----:12: MOVE16 L,d[Areg-Aipi]
+1111 0110 00ss sSSS:50:-----:-----:12: MOVE16 s[Aind],L
+1111 0110 00dd dDDD:50:-----:-----:12: MOVE16 L,d[Aipi-Aind]
projects / francis / winuae.git / commitdiff