}
if (exc == 0 && cpuexc == 4) {
// successful complete generates exception 4 with matching PC
- if (lregs->pc + opcodeendsizeextra != tregs->pc && dooutput) {
+ if (lregs->pc + opcodeendsizeextra != tregs->pc && lregs->pc != tregs->pc && dooutput) {
sprintf(outbp, "PC: expected %08x but got %08x\n", lregs->pc, tregs->pc);
outbp += strlen(outbp);
if (tregs->pc == opcode_memory_addr) {
Change log:
+17.05.2020
+
+- Rewritten disassembler to use indirect and validated opword reads, now it is safe to use when testing bus errors.
+
09.05.2020
- dat format changed, now it is possible to continue running test if previous test reported error.