User/supervisor mode memory access handler helper function.

diff --git a/cpummu.cpp b/cpummu.cpp
index 2037e98e45b25e7b7ece32c0dfa0daf3462c98b8..50fbd5a06ade7186a3809059ee59b15527308639 100644 (file)
--- a/cpummu.cpp
+++ b/cpummu.cpp
@@ -383,6 +383,16 @@ void mmu_hardware_bus_error(uaecptr addr, uae_u32 v, bool read, bool ins, int si
        mmu_bus_error(addr, v, fc, !read, size, 0, true);
 }
 
+bool mmu_is_super_access(bool read)
+{
+       if (!ismoves) {
+               return regs.s;
+       } else {
+               uae_u32 fc = read ? regs.sfc : regs.dfc;
+               return (fc & 4) != 0;
+       }
+}
+
 void mmu_bus_error(uaecptr addr, uae_u32 val, int fc, bool write, int size,uae_u32 status060, bool nonmmu)
 {
        if (currprefs.mmu_model == 68040) {

diff --git a/cpummu30.cpp b/cpummu30.cpp
index 433c669aed0ecb6119298f8a833ed5acd80b8011..24eb66d87e6cfe0edd4c590ff5567ca2d1767649 100644 (file)
--- a/cpummu30.cpp
+++ b/cpummu30.cpp
@@ -1879,6 +1879,16 @@ void mmu030_hardware_bus_error(uaecptr addr, uae_u32 v, bool read, bool ins, int
        mmu030_page_fault(addr, read, flags, fc);
 }
 
+bool mmu030_is_super_access(bool read)
+{
+       if (!ismoves030) {
+               return regs.s;
+       } else {
+               uae_u32 fc = read ? regs.sfc : regs.dfc;
+               return (fc & 4) != 0;
+       }
+}
+
 static void mmu030_add_data_read_cache(uaecptr addr, uaecptr phys, uae_u32 fc)
 {
 #if MMU_DPAGECACHE030

diff --git a/include/cpummu.h b/include/cpummu.h
index 83b650e80df913aaf3398009ea2fe9b16eafb5c9..3376e5d1bdff89e6aa578203d2adbd4ba2220167 100644 (file)
--- a/include/cpummu.h
+++ b/include/cpummu.h
@@ -177,6 +177,7 @@ extern int mmu_match_ttr_write(uaecptr addr, bool super, bool data, uae_u32 val,
 extern int mmu_match_ttr_maybe_write(uaecptr addr, bool super, bool data, int size, bool write);
 extern uaecptr mmu_translate(uaecptr addr, uae_u32 val, bool super, bool data, bool write, int size);
 extern void mmu_hardware_bus_error(uaecptr addr, uae_u32 v, bool read, bool ins, int size);
+extern bool mmu_is_super_access(bool read);
 
 extern uae_u32 REGPARAM3 mmu060_get_rmw_bitfield (uae_u32 src, uae_u32 bdata[2], uae_s32 offset, int width) REGPARAM;
 extern void REGPARAM3 mmu060_put_rmw_bitfield (uae_u32 dst, uae_u32 bdata[2], uae_u32 val, uae_s32 offset, int width) REGPARAM;

diff --git a/include/cpummu030.h b/include/cpummu030.h
index 3ddddcf4202758b13bdf31b61cdf8aad82a76999..85a6d532bbb69d43e0ba880e088cfab46391f589 100644 (file)
--- a/include/cpummu030.h
+++ b/include/cpummu030.h
@@ -72,6 +72,8 @@ void mmu030_reset(int hardreset);
 void mmu030_set_funcs(void);
 uaecptr mmu030_translate(uaecptr addr, bool super, bool data, bool write);
 void mmu030_hardware_bus_error(uaecptr addr, uae_u32 v, bool read, bool ins, int size);
+bool mmu030_is_super_access(bool read);
+
 void mmu030_put_long(uaecptr addr, uae_u32 val, uae_u32 fc);
 void mmu030_put_word(uaecptr addr, uae_u16 val, uae_u32 fc);
 void mmu030_put_byte(uaecptr addr, uae_u8  val, uae_u32 fc);

diff --git a/include/newcpu.h b/include/newcpu.h
index ae219e94c9db877aac1e0bbd7ba84aa25089b4dc..8781966d7c1216bf82224337510516f9a602bfbb 100644 (file)
--- a/include/newcpu.h
+++ b/include/newcpu.h
@@ -574,6 +574,8 @@ STATIC_INLINE void m68k_setpc_normal(uaecptr pc)
 
 extern void cpu_invalidate_cache(uaecptr, int);
 
+extern bool(*is_super_access)(bool);
+
 extern uae_u32(*read_data_030_bget)(uaecptr);
 extern uae_u32(*read_data_030_wget)(uaecptr);
 extern uae_u32(*read_data_030_lget)(uaecptr);

diff --git a/newcpu.cpp b/newcpu.cpp
index e97df2646d087039565e581e03dcb7b45b7fd94e..ec3cf68bcb36ab998204ddbb855ca5d7caf7a6f6 100644 (file)
--- a/newcpu.cpp
+++ b/newcpu.cpp
@@ -257,6 +257,8 @@ void(*x_phys_put_byte)(uaecptr, uae_u32);
 void(*x_phys_put_word)(uaecptr, uae_u32);
 void(*x_phys_put_long)(uaecptr, uae_u32);
 
+bool(*is_super_access)(bool);
+
 static void set_x_cp_funcs(void)
 {
        x_cp_put_long = x_put_long;
@@ -843,7 +845,7 @@ void(*write_data_030_fc_wput)(uaecptr, uae_u32, uae_u32);
 void(*write_data_030_fc_lput)(uaecptr, uae_u32, uae_u32);
 
  
- static void set_x_ifetches(void)
+static void set_x_ifetches(void)
 {
        if (m68k_pc_indirect) {
                if (currprefs.cachesize) {
@@ -871,9 +873,35 @@ void(*write_data_030_fc_lput)(uaecptr, uae_u32, uae_u32);
        }
 }
 
+static bool is_super_access_68000(bool read)
+{
+       return regs.s;
+}
+static bool nommu_is_super_access(bool read)
+{
+       if (!ismoves_nommu) {
+               return regs.s;
+       } else {
+               uae_u32 fc = read ? regs.sfc : regs.dfc;
+               return (fc & 4) != 0;
+       }
+}
+
 // indirect memory access functions
 static void set_x_funcs (void)
 {
+       if (currprefs.cpu_model >= 68010) {
+               if (currprefs.mmu_model == 68030) {
+                       is_super_access = mmu030_is_super_access;
+               } else if (currprefs.mmu_model >= 68040) {
+                       is_super_access = mmu_is_super_access;
+               } else {
+                       is_super_access = nommu_is_super_access;
+               }
+       } else {
+               is_super_access = is_super_access_68000;
+       }
+
        if (currprefs.mmu_model) {
                if (currprefs.cpu_model == 68060) {