Bus error startup takes 4 more cycles than address error (at least with my bus error...

diff --git a/cputest/cputestgen.ini b/cputest/cputestgen.ini
index 518a326b3cbe9e5a9f61ac7772031b715a343c1b..19a67436d9cc07766115e1dd20e7466dfab3e199 100644 (file)
--- a/cputest/cputestgen.ini
+++ b/cputest/cputestgen.ini
@@ -167,10 +167,10 @@ enabled=1
 mode=all
 
 ; basic instruction test
-[test=ALL]
+[test=Basic]
 enabled=0
 mode=all
-feature_sr_mask=0xa000
+feature_sr_mask=0x8000
 
 ; interrupt exception
 [test=IRQ]

diff --git a/cputest/main.c b/cputest/main.c
index cbcbe236ad46aac19c6835574eddfc97c42ffa3a..15615d8c6d477f7fae0e9a8091c3fd660f0c446d 100644 (file)
--- a/cputest/main.c
+++ b/cputest/main.c
@@ -1714,6 +1714,7 @@ static int getexceptioncycles(int exc)
                switch (exc)
                {
                case 2:
+                       return 58;
                case 3:
                        return 54;
                case 4:
@@ -1742,6 +1743,7 @@ static int getexceptioncycles(int exc)
                switch (exc)
                {
                case 2:
+                       return 134;
                case 3:
                        return 130;
                case 4:

diff --git a/cputest/readme.txt b/cputest/readme.txt
index fdd58ff3e74e67fc408617db50dfff408823b91d..d42131ababec9e1accde0c6e72546aa8ff5cf75d 100644 (file)
--- a/cputest/readme.txt
+++ b/cputest/readme.txt
@@ -22,6 +22,7 @@ Tests executed for each tested instruction:
 - If instruction generated privilege violation exception, extra test round is run in supervisor mode.
 - Optionally can do any combination of T0, T1, S and M -bit SR register extra test rounds.
 - Every opcode value is tested. Total number of tests per opcode depends on available addressing modes etc. It can be hundreds of thousands or even millions..
+- Optinnally can be used to fully validate address and bus errors. Bus error testing requires extra hardware/logic.
 
 Test generation details:
 
@@ -39,10 +40,11 @@ Notes and limitations:
 - Single instruction test set will take long time to run on real 68000. Few minutes to much longer...
 - Undefined flags (for example DIV and CHK or 68000/010 bus address error) are also verified. It probably would be good idea to optionally filter them out.
 - FPU testing is not yet fully implemented.
+- TAS test will return wrong results if test RAM region is not fully TAS read-modify-write special memory access compatible.
 
 Tester compatibility (integer instructions only):
 
-68000: Complete. Including bus and address error stack frame/register/CCR modification undocumented behavior. Cycle count support.
+68000: Complete. Including bus and address error stack frame/register/CCR modification undocumented behavior. Full cycle count support.
 68010: Almost complete (same as 68000). Loop mode is also fully supported. NOTE: DIVS overflow undocumented N-flag is not fully correct.
 68020: Almost complete (DIV undocumented behavior is not yet known)
 68030: Same as 68020.
@@ -64,8 +66,6 @@ Cycle counting requires 100% accurate timing also for following instructions:
 0xDFF006 is used for cycle counting = accuracy will be +-2 CPU cycles. 0xDFF006 behavior must be accurate.
 Currently only supported hardware for cycle counting is 7MHz 68000/68010 PAL Amiga with real Fast RAM.
 
-Bus error cycle counting is not yet supported.
-
 --
 
 Not implemented or only partially implemented:
@@ -140,3 +140,13 @@ Change log:
 - Some instructions (for example TRAP) had wrong expected cycle count if instruction generated any non-trace exception and also trace exception.
 - added -skipexcccr parameter. Skip CCR check if instruction generates bus, address, divide by zero or CHK exception.
 - added -skipmem (ignore memory write mismatches) -skipreg (ignore register mismatched) -skipccr (ignored CCR mismatch) parameters.
+
+09.02.2020
+
+- All 68000 tests are 100% confirmed, including full cycle-count support.
+
+15.02.2020
+
+- 68000 Address error timing fix (CHK.W cycle count error)
+- 68000 MOVE to memory address error cycle order fixed.
+- 68000 re-verified (except bus errors)

diff --git a/newcpu.cpp b/newcpu.cpp
index f6fcd78f2cfc4bbf5b31b9145ff11609c51ed06a..086c2aadf331554da1864019e6d95e4668285d7e 100644 (file)
--- a/newcpu.cpp
+++ b/newcpu.cpp
@@ -2370,7 +2370,7 @@ static void exception_debug (int nr)
 Address/Bus Error:
 
 - [memory access causing bus/address error]
-- 8 idle cycles
+- 8 idle cycles (+4 if bus error)
 - write PC low word
 - write SR
 - write PC high word
@@ -2505,8 +2505,10 @@ static void Exception_ce000 (int nr)
                start = 4;
                if (nr == 7) // TRAPV
                        start = 0;
-               else if (nr == 2 || nr == 3)
+               else if (nr == 3)
                        start = 8;
+               else if (nr == 2)
+                       start = 12;
        }
 
        if (start)
@@ -2827,7 +2829,7 @@ static void add_approximate_exception_cycles(int nr)
                } else {
                        switch (nr)
                        {
-                       case 2: cycles = 54; break;             /* Bus error */
+                       case 2: cycles = 58; break;             /* Bus error */
                        case 3: cycles = 54; break;             /* Address error */
                        case 4: cycles = 34; break;             /* Illegal instruction */
                        case 5: cycles = 34; break;             /* Division by zero */
@@ -2852,7 +2854,7 @@ static void add_approximate_exception_cycles(int nr)
                } else {
                        switch (nr)
                        {
-                       case 2: cycles = 130; break;    /* Bus error */
+                       case 2: cycles = 134; break;    /* Bus error */
                        case 3: cycles = 130; break;    /* Address error */
                        case 4: cycles = 38; break;             /* Illegal instruction */
                        case 5: cycles = 38; break;             /* Division by zero */