Rancho RT1000 bridgeboard SCSI expansion. 53C400 updates.

diff --git a/expansion.cpp b/expansion.cpp
index 5d8ceb1df96efdd91279089f7e917e6b4dae4b82..47b03aea263e57937a72ce79c0451de78f911f7e 100644 (file)
--- a/expansion.cpp
+++ b/expansion.cpp
@@ -4225,7 +4225,7 @@ static const struct expansionboardsettings toccata_soundcard_settings[] = {
 
 static const struct expansionboardsettings x86_athdxt_settings[] = {
        {
-               _T("ROM Address\0") _T("0xCC000\0") _T("0xDC000\0") _T("0xEC000\0"),
+               _T("ROM address\0") _T("0xCC000\0") _T("0xDC000\0") _T("0xEC000\0"),
                _T("baseaddress\0") _T("0xcc000\0") _T("0xdc000\0") _T("0xec000\0"),
                true
        },
@@ -4234,6 +4234,16 @@ static const struct expansionboardsettings x86_athdxt_settings[] = {
        }
 };
 
+static const struct expansionboardsettings x86_rt1000_settings[] = {
+       {
+               _T("Base address\0") _T("0xC8000\0") _T("0xCC000\0") _T("0xD0000\0") _T("0xD4000\0") _T("0xD8000\0") _T("0xDC000 (*)\0") _T("0xE0000\0") _T("0xE4000\0"),
+               _T("baseaddress\0") _T("0xc8000\0") _T("0xcc000\0") _T("0xd0000\0") _T("0xd4000\0") _T("0xd8000\0") _T("0xdc000\0") _T("0xe0000\0") _T("0xe4000\0"),
+               true
+       },
+       {
+               NULL
+       }
+};
 
 static const struct expansionboardsettings harlequin_settings[] = {
        {
@@ -5277,6 +5287,15 @@ const struct expansionromtype expansionroms[] = {
                0, 0, 0, false, NULL,
                false, 0, x86_athdxt_settings
        },
+       {
+               _T("x86rt1000"), _T("Rancho RT1000"), _T("x86"),
+               NULL, x86_rt1000_init, NULL, x86_rt1000_add_unit, ROMTYPE_X86_RT1000, 0, 0, BOARD_NONAUTOCONFIG_AFTER_Z2, true,
+               NULL, 0,
+               false, EXPANSIONTYPE_SCSI,
+               0, 0, 0, false, NULL,
+               false, 0, x86_rt1000_settings
+
+       },
 
        /* PC Bridgeboards */
 

diff --git a/include/rommgr.h b/include/rommgr.h
index 2fca5d304651182939cb3f99339c2efcd29fa7f4..e731547f4865b15ee5cd69eee9f57c725cc0fcb1 100644 (file)
--- a/include/rommgr.h
+++ b/include/rommgr.h
@@ -107,7 +107,7 @@ extern int decode_cloanto_rom_do (uae_u8 *mem, int size, int real_size);
 #define ROMTYPE_A2286          0x0010002d
 #define ROMTYPE_A2386          0x0010002e
 #define ROMTYPE_OMTIADAPTER    0x0010002f
-#define ROMTYPE_X86_HD         0x00100030
+#define ROMTYPE_X86_RT1000     0x00100030
 #define ROMTYPE_X86_AT_HD1     0x00100031
 #define ROMTYPE_X86_AT_HD2     0x00100032
 #define ROMTYPE_X86_XT_IDE     0x00100033

diff --git a/include/scsi.h b/include/scsi.h
index 8e47c90e04b105027b8f5eb252251747df540d01..ee6e842e9032faa14c4a68745e84317adfdf593f 100644 (file)
--- a/include/scsi.h
+++ b/include/scsi.h
@@ -302,9 +302,9 @@ void fasttrak_add_scsi_unit(int ch, struct uaedev_config_info *ci, struct romcon
 uae_u8 idescsi_scsi_get(uaecptr addr);
 void idescsi_scsi_put(uaecptr addr, uae_u8 v);
 
-void x86_xt_hd_bput(int, uae_u8);
-uae_u8 x86_xt_hd_bget(int);
-bool x86_xt_hd_init(struct autoconfig_info *aci);
-void x86_add_xt_hd_unit(int ch, struct uaedev_config_info *ci, struct romconfig *rc);
+void x86_rt1000_bput(int, uae_u8);
+uae_u8 x86_rt1000_bget(int);
+bool x86_rt1000_init(struct autoconfig_info *aci);
+void x86_rt1000_add_unit(int ch, struct uaedev_config_info *ci, struct romconfig *rc);
 
 #endif /* UAE_SCSI_H */

diff --git a/scsi.cpp b/scsi.cpp
index 5574ad355a10268e6fff4d4641fa0e1829057508..4d32fded2c28dea7fe5789920adcb7614d89c733 100644 (file)
--- a/scsi.cpp
+++ b/scsi.cpp
@@ -31,6 +31,7 @@
 #define RAW_SCSI_DEBUG 0
 #define NCR5380_DEBUG 0
 #define NCR5380_DEBUG_IRQ 0
+#define NCR53400_DEBUG 0
 
 #define NCR5380_SUPRA 1
 #define NONCR_GOLEM 2
@@ -55,7 +56,7 @@
 #define OMTI_PROMIGOS 21
 #define OMTI_SYSTEM2000 22
 #define OMTI_ADAPTER 23
-#define OMTI_X86 24
+#define NCR5380_X86_RT1000 24
 #define NCR5380_PHOENIXBOARD 25
 #define NCR5380_TRUMPCARDPRO 26
 #define NCR5380_IVSVECTOR 27 // nearly identical to trumpcard pro
@@ -809,8 +810,10 @@ struct raw_scsi
 struct soft_scsi
 {
        uae_u8 regs[32];
-       uae_u8 regs_400[2];
+       uae_u16 regs_400[2];
+       uae_u8 scratch_400[64];
        int c400_count;
+       bool c400;
        uae_u8 aic_reg;
        struct raw_scsi rscsi;
        bool irq;
@@ -1059,6 +1062,7 @@ static void raw_scsi_reset_bus(struct soft_scsi *scsi)
 #if RAW_SCSI_DEBUG
        write_log(_T("SCSI BUS reset\n"));
 #endif
+       raw_scsi_reset(r);
        for (int i = 0; i < 8; i++) {
                scsi_emulate_reset_device(r->device[i]);
        }
@@ -1278,6 +1282,11 @@ static void raw_scsi_write_data(struct raw_scsi *rs, uae_u8 data)
                        } else if (sd->direction <= 0) {
                                scsi_emulate_cmd(sd);
                                scsi_start_transfer(sd);
+#if RAW_SCSI_DEBUG
+                               if (sd->status) {
+                                       write_log(_T("raw_scsi: status = %d len = %d\n"), sd->status, sd->data_len);
+                               }
+#endif
                                if (!sd->status && sd->data_len > 0) {
 #if RAW_SCSI_DEBUG
                                        write_log(_T("raw_scsi: data in %d bytes waiting\n"), sd->data_len);
@@ -1769,7 +1778,8 @@ void x86_doirq(uint8_t irqnum);
 void ncr80_rethink(void)
 {
        for (int i = 0; soft_scsi_devices[i]; i++) {
-               if (soft_scsi_devices[i]->irq && soft_scsi_devices[i]->intena) {
+               struct soft_scsi *s = soft_scsi_devices[i];
+               if (s->irq && s->intena && ((s->c400 && (s->regs_400[0] & 0x10) && !s->c400_count) || !s->c400)) {
                        if (soft_scsi_devices[i] == x86_hd_data) {
                                x86_doirq(5);
                        } else {
@@ -1822,14 +1832,16 @@ static void ncr5380_check_phase(struct soft_scsi *scsi)
        }
 }
 
-static void ncr5380_reset(struct soft_scsi *scsi)
+static void ncr5380_reset(struct soft_scsi *scsi, bool busreset)
 {
        struct raw_scsi *r = &scsi->rscsi;
 
        memset(scsi->regs, 0, sizeof scsi->regs);
-       raw_scsi_reset_bus(scsi);
-       scsi->regs[1] = 0x80;
-       ncr5380_set_irq(scsi);
+       if (busreset) {
+               raw_scsi_reset_bus(scsi);
+               scsi->regs[1] = 0x80;
+               ncr5380_set_irq(scsi);
+       }
 }
 
 uae_u8 ncr5380_bget(struct soft_scsi *scsi, int reg)
@@ -1955,7 +1967,7 @@ void ncr5380_bput(struct soft_scsi *scsi, int reg, uae_u8 v)
                                        raw_scsi_set_ack(r, (v & (1 << 4)) != 0);
                        }
                        if (v & 0x80) { // RST
-                               ncr5380_reset(scsi);
+                               ncr5380_reset(scsi, true);
                        }
                }
                break;
@@ -2031,10 +2043,11 @@ static void ncr53400_dmacount(struct soft_scsi *scsi)
        if (scsi->c400_count == 128) {
                scsi->c400_count = 0;
                scsi->regs_400[1]--;
-               if (scsi->regs_400[1] == 0) {
-                       scsi->regs[5] &= ~0x40; // dma request
-                       ncr5380_check_phase(scsi);
-               }
+               scsi->regs_400[1] &= 0xff;
+               ncr5380_check_phase(scsi);
+               scsi->regs[5] |= 0x80; // end of dma
+               scsi->regs[3] |= 0x80; // last byte sent
+               ncr5380_set_irq(scsi);
        }
 }
 
@@ -2042,16 +2055,26 @@ static uae_u8 ncr53400_bget(struct soft_scsi *scsi, int reg)
 {
        struct raw_scsi *rs = &scsi->rscsi;
        uae_u8 v = 0;
-       uae_u8 csr = scsi->regs_400[0];
+       uae_u8 csr = (uae_u8)scsi->regs_400[0];
 
        if (ncr53400_5380(scsi) && reg < 8) {
                v = ncr5380_bget(scsi, reg);
-               //write_log(_T("53C80 REG GET %02x -> %02x\n"), reg, v);
+#if NCR53400_DEBUG
+               static uae_u8 lastreg, lastval;
+               if (lastreg != reg || lastval != v) {
+                       write_log(_T("53C80 REG GET %02x -> %02x\n"), reg, v);
+                       lastreg = reg;
+                       lastval = v;
+               }
+#endif
                return v;
        }
        if (reg & 0x80) {
                v = raw_scsi_get_data(rs, true);
                ncr53400_dmacount(scsi);
+#if NCR53400_DEBUG
+               write_log(_T("53C400 DATA GET %02x %d\n"), v, scsi->c400_count);
+#endif
        } else if (reg & 0x100) {
                switch (reg) {
                        case 0x100:
@@ -2066,10 +2089,14 @@ static uae_u8 ncr53400_bget(struct soft_scsi *scsi, int reg)
                                        v |= 0x01;
                                break;
                        case 0x101:
-                               v = scsi->regs_400[1];
+                               v = (uae_u8)scsi->regs_400[1];
                                break;
                }
-               //write_log(_T("53C400 REG GET %02x -> %02x\n"), reg, v);
+#if NCR53400_DEBUG
+               write_log(_T("53C400 REG GET %02x -> %02x\n"), reg, v);
+#endif
+       } else if (reg & 0x200) {
+               v = scsi->scratch_400[reg & 0x3f];
        }
        ncr5380_check_phase(scsi);
        return v;
@@ -2078,32 +2105,43 @@ static uae_u8 ncr53400_bget(struct soft_scsi *scsi, int reg)
 static void ncr53400_bput(struct soft_scsi *scsi, int reg, uae_u8 v)
 {
        struct raw_scsi *rs = &scsi->rscsi;
-       uae_u8 csr = scsi->regs_400[0];
+       uae_u8 csr = (uae_u8)scsi->regs_400[0];
 
        if (ncr53400_5380(scsi) && reg < 8) {
                ncr5380_bput(scsi, reg, v);
-               //write_log(_T("53C80 REG PUT %02x -> %02x\n"), reg, v);
+#if NCR53400_DEBUG
+               write_log(_T("53C80 REG PUT %02x -> %02x\n"), reg, v);
+#endif
                return;
        }
        if (reg & 0x80) {
                raw_scsi_put_data(rs, v, true);
                ncr53400_dmacount(scsi);
+#if NCR53400_DEBUG
+               write_log(_T("53C400 DATA PUT %02x %d\n"), v, scsi->c400_count);
+#endif
        } else if (reg & 0x100) {
                switch (reg) {
                        case 0x100:
                                scsi->regs_400[0] = v;
                                if (v & 0x80) {
-                                       ncr5380_reset(scsi);
+                                       // 53C400 reset does not reset 53C80
                                        scsi->regs_400[0] = 0x80;
                                        scsi->regs_400[1] = 0;
                                }
                                break;
                        case 0x101:
                                scsi->regs_400[1] = v;
+                               if (v == 0)
+                                       scsi->regs_400[1] = 256;
                                scsi->c400_count = 0;
                                break;
                }
-               //write_log(_T("53C400 REG PUT %02x -> %02x\n"), reg, v);
+#if NCR53400_DEBUG
+               write_log(_T("53C400 REG PUT %02x -> %02x\n"), reg, v);
+#endif
+       } else if (reg & 0x200) {
+               scsi->scratch_400[reg & 0x3f] = v;
        }
        ncr5380_check_phase(scsi);
 }
@@ -3793,32 +3831,6 @@ static void ncr80_bput2(struct soft_scsi *ncr, uaecptr addr, uae_u32 val, int si
 #endif
 }
 
-// x86 bridge hd
-void x86_xt_hd_bput(int portnum, uae_u8 v)
-{
-       struct soft_scsi *scsi = x86_hd_data;
-       write_log(_T("X86 HD PUT %04x = %02x\n"), portnum, v);
-       if (!scsi)
-               return;
-       if (portnum < 0) {
-               struct raw_scsi *rs = &scsi->rscsi;
-               raw_scsi_busfree(rs);
-               scsi->chip_state = 0;
-               return;
-       }
-       omti_bput(scsi, v & 3, v);
-}
-uae_u8 x86_xt_hd_bget(int portnum)
-{
-       uae_u8 v = 0xff;
-       struct soft_scsi *scsi = x86_hd_data;
-       write_log(_T("X86 HD GET %04x\n"), portnum);
-       if (!scsi)
-               return v;
-       v = omti_bget(scsi, v & 3);
-       return v;
-}
-
 // mainhattan paradox scsi
 uae_u8 parallel_port_scsi_read(int reg, uae_u8 data, uae_u8 dir)
 {
@@ -4352,6 +4364,7 @@ bool rochard_scsi_init(struct romconfig *rc, uaecptr baseaddress)
 {
        struct soft_scsi *scsi = getscsi(rc);
        scsi->configured = true;
+       scsi->c400 = true;
        scsi->dma_controller = true;
        scsi->baseaddress = baseaddress;
        return scsi != NULL;
@@ -4792,29 +4805,6 @@ void omtiadapter_scsi_unit(int ch, struct uaedev_config_info *ci, struct romconf
        generic_soft_scsi_add(ch, ci, rc, OMTI_ADAPTER, 65536, 0, ROMTYPE_OMTIADAPTER);
 }
 
-extern void x86_xt_ide_bios(struct zfile*, struct romconfig *rc);
-bool x86_xt_hd_init(struct autoconfig_info *aci)
-{
-       if (!aci->doinit)
-               return true;
-
-       struct soft_scsi *scsi = getscsi(aci->rc);
-
-       if (!scsi)
-               return false;
-       struct zfile *f = read_device_from_romconfig(aci->rc, 0);
-       x86_xt_ide_bios(f, aci->rc);
-       zfile_fclose(f);
-       scsi->configured = 1;
-       x86_hd_data = scsi;
-       return true;
-}
-
-void x86_add_xt_hd_unit(int ch, struct uaedev_config_info *ci, struct romconfig *rc)
-{
-       generic_soft_scsi_add(ch, ci, rc, OMTI_X86, 0, 0, ROMTYPE_X86_HD);
-}
-
 bool phoenixboard_init(struct autoconfig_info *aci)
 {
        if (!aci->doinit) {
@@ -5181,7 +5171,6 @@ void profex_add_scsi_unit(int ch, struct uaedev_config_info *ci, struct romconfi
        }
 }
 
-
 bool fasttrak_init(struct autoconfig_info *aci)
 {
        if (!aci->doinit) {
@@ -5203,3 +5192,56 @@ void fasttrak_add_scsi_unit(int ch, struct uaedev_config_info *ci, struct romcon
 {
        generic_soft_scsi_add(ch, ci, rc, NCR5380_FASTTRAK, 65536, 65536, ROMTYPE_FASTTRAK);
 }
+
+// x86 bridge scsi rancho rt1000
+void x86_rt1000_bput(int portnum, uae_u8 v)
+{
+       struct soft_scsi *scsi = x86_hd_data;
+       if (!scsi)
+               return;
+       if (portnum < 0) {
+               struct raw_scsi *rs = &scsi->rscsi;
+               raw_scsi_busfree(rs);
+               scsi->chip_state = 0;
+               return;
+       }
+       ncr53400_bput(scsi, portnum, v);
+}
+uae_u8 x86_rt1000_bget(int portnum)
+{
+       uae_u8 v = 0xff;
+       struct soft_scsi *scsi = x86_hd_data;
+       if (!scsi)
+               return v;
+       v = ncr53400_bget(scsi, portnum);
+       return v;
+}
+
+extern void x86_rt1000_bios(struct zfile*, struct romconfig *rc);
+bool x86_rt1000_init(struct autoconfig_info *aci)
+{
+       static const int parent[] = { ROMTYPE_A1060, ROMTYPE_A2088, ROMTYPE_A2088T, ROMTYPE_A2286, ROMTYPE_A2386, 0 };
+       aci->parent_romtype = parent;
+       if (!aci->doinit)
+               return true;
+
+       struct soft_scsi *scsi = getscsi(aci->rc);
+
+       if (!scsi)
+               return false;
+       struct zfile *f = read_device_from_romconfig(aci->rc, 0);
+       if (f) {
+               x86_rt1000_bios(f, aci->rc);
+               zfile_fclose(f);
+       }
+       scsi->configured = 1;
+       scsi->dma_controller = true;
+       scsi->c400 = true;
+       x86_hd_data = scsi;
+       return true;
+}
+
+void x86_rt1000_add_unit(int ch, struct uaedev_config_info *ci, struct romconfig *rc)
+{
+       generic_soft_scsi_add(ch, ci, rc, NCR5380_X86_RT1000, 0, 0, ROMTYPE_X86_RT1000);
+}

diff --git a/x86.cpp b/x86.cpp
index 17140ddff50f9fe57ce57cab6eeabb9d5e208a2f..91f593b9fe57d963404394fa15c29b0b8b53af2d 100644 (file)
--- a/x86.cpp
+++ b/x86.cpp
@@ -100,6 +100,7 @@ static int x86_vga_board;
 int x86_cmos_bank;
 
 static uae_u8 *xtiderom;
+static uae_u8 *rt1000rom;
 
 int GAMEBLASTER = 1;
 int sound_pos_global;
@@ -241,7 +242,7 @@ static void reset_x86_cpu(struct x86_bridge *xb)
        reset_cpu();
        // reset x86 hd controllers
        x86_ide_hd_put(-1, 0, 0);
-       x86_xt_hd_bput(-1, 0);
+       x86_rt1000_bput(-1, 0);
 }
 
 uint8_t x86_get_jumpers(void)
@@ -2192,14 +2193,6 @@ void portout(uint16_t portnum, uint8_t v)
                x86_ide_hd_put(portnum, v, 0);
                break;
 
-               // xt hd
-               case 0x320:
-               case 0x321:
-               case 0x322:
-               case 0x323:
-               x86_xt_hd_bput(portnum, v);
-               break;
-
                // universal xt bios
                case 0x300:
                case 0x301:
@@ -2585,14 +2578,6 @@ uint8_t portin(uint16_t portnum)
                v = x86_ide_hd_get(portnum, 0);
                break;
 
-               // xt hd
-               case 0x320:
-               case 0x321:
-               case 0x322:
-               case 0x323:
-               v = x86_xt_hd_bget(portnum);
-               break;
-
                // universal xt bios
                case 0x300:
                case 0x301:
@@ -3055,6 +3040,98 @@ static void vgalfb_writel(uint32_t addr, uint32_t val, void *priv)
        vgalfb_ram_put(x86_vga_board, addr + 3, val >> 24);
 }
 
+static int to53c400reg(uint32_t addr, bool rw)
+{
+       //write_log(_T("%c %08x\n"), rw ? 'W' : 'R', addr);
+       // Scratchpad RAM
+       if (addr >= 0x3800 && addr <= 0x387f)
+               return (addr & 0x3f) | 0x200;
+       // 53C80 registers
+       if (addr >= 0x3880 && addr <= 0x38ff)
+               return addr & 7;
+       // Data port
+       if (addr >= 0x3900 && addr <= 0x397f)
+               return 0x80;
+       // 53C400 registers
+       if (addr >= 0x3980 && addr <= 0x39ff) {
+               int reg = addr & 3;
+               if (reg >= 2)
+                       return -1;
+               return reg | 0x100;
+       }
+       return -1;
+}
+
+static uint8_t mem_read_romext3(uint32_t addr, void *priv)
+{
+       uae_u8 v = 0xff;
+       addr &= 0x3fff;
+       if (addr < 0x2000) {
+               v = rt1000rom[addr];
+       } else if (addr >= 0x3a00) {
+               write_log(_T("mem_read_romext3 %08x\n"), addr);
+       } else if (addr >= 0x3800) {
+               int reg = to53c400reg(addr, false);
+               if (reg >= 0)
+                       v = x86_rt1000_bget(reg);
+       }
+       return v;
+}
+static uint16_t mem_read_romextw3(uint32_t addr, void *priv)
+{
+       uae_u16 v = 0xffff;
+       addr &= 0x3fff;
+       if (addr < 0x2000) {
+               v =  *(uint16_t *)&rt1000rom[addr & 0x1fff];
+       } else if (addr >= 0x3a00) {
+               write_log(_T("mem_read_romext3 %08x\n"), addr);
+       } else if (addr >= 0x3800) {
+               int reg = to53c400reg(addr + 0, false);
+               v = 0;
+               if (reg >= 0)
+                       v = x86_rt1000_bget(reg);
+               reg = to53c400reg(addr + 1, false);
+               if (reg >= 0)
+                       v |= x86_rt1000_bget(reg) << 8;
+       }
+       return v;
+}
+static uint32_t mem_read_romextl3(uint32_t addr, void *priv)
+{
+       return *(uint32_t *)&rt1000rom[addr & 0x3fff];
+}
+static void mem_write_romext3(uint32_t addr, uint8_t val, void *priv)
+{
+       addr &= 0x3fff;
+       if (addr >= 0x3a00) {
+               write_log(_T("mem_write_romext3 %08x %02x\n"), addr, val);
+       } else if (addr >= 0x3800) {
+               int reg = to53c400reg(addr, true);
+               if (reg >= 0)
+                       x86_rt1000_bput(reg, val);
+       }
+}
+static void mem_write_romextw3(uint32_t addr, uint16_t val, void *priv)
+{
+       addr &= 0x3fff;
+       if (addr >= 0x3a00) {
+               write_log(_T("mem_write_romextw3 %08x %04x\n"), addr, val);
+       } else if (addr >= 0x3800) {
+               int reg = to53c400reg(addr + 0, true);
+               if (reg >= 0)
+                       x86_rt1000_bput(reg, val);
+               reg = to53c400reg(addr + 1, true);
+               if (reg >= 0)
+                       x86_rt1000_bput(reg, val >> 8);
+       } else {
+               write_log(_T("mem_write_romextw3 %08x %04x\n"), addr, val);
+       }
+}
+static void mem_write_romextl3(uint32_t addr, uint32_t val, void *priv)
+{
+
+}
+
 static uint8_t mem_read_romext2(uint32_t addr, void *priv)
 {
        return xtiderom[addr & 0x3fff];
@@ -3116,6 +3193,8 @@ void x86_bridge_reset(void)
                rom = NULL;
                xfree(xtiderom);
                xtiderom = NULL;
+               xfree(rt1000rom);
+               rt1000rom = NULL;
                xfree(xb->mouse_base);
                xfree(xb->cms_base);
                xfree(xb->sb_base);
@@ -3345,6 +3424,18 @@ static void ne2000_isa_irq_callback(struct pci_board_state *pcibs, bool irq)
                x86_clearirq(xb->ne2000_irq);
 }
 
+void x86_rt1000_bios(struct zfile *z, struct romconfig *rc)
+{
+       struct x86_bridge *xb = bridges[0];
+       uae_u32 addr = 0;
+       if (!xb || !z)
+               return;
+       addr = (rc->device_settings & 7) * 0x4000 + 0xc8000;
+       rt1000rom = xcalloc(uae_u8, 0x2000 + 1);
+       zfile_fread(rt1000rom, 1, 0x2000, z);
+       mem_mapping_add(&bios_mapping[6], addr, 0x4000, mem_read_romext3, mem_read_romextw3, mem_read_romextl3, mem_write_romext3, mem_write_romextw3, mem_write_romextl3, rt1000rom, MEM_MAPPING_EXTERNAL | MEM_MAPPING_ROM, 0);
+}
+
 void x86_xt_ide_bios(struct zfile *z, struct romconfig *rc)
 {
        struct x86_bridge *xb = bridges[0];