*
* A590/A2091/A3000/CDTV SCSI expansion (DMAC/SuperDMAC + WD33C93) emulation
* Includes A590 + XT drive emulation.
-* GVP Series II
+* GVP Series I and II
+* A2090
*
-* Copyright 2007-2014 Toni Wilen
+* Copyright 2007-2015 Toni Wilen
*
*/
#include "savestate.h"
#include "cpuboard.h"
+#define DMAC_8727_ROM_VECTOR 0x8000
#define CDMAC_ROM_VECTOR 0x2000
#define CDMAC_ROM_OFFSET 0x2000
#define GVP_ROM_OFFSET 0x8000
-#define GVP_SERIES_I_RAM_OFFSET 0x4000
-#define GVP_SERIES_I_RAM_MASK 16383
+#define GVP_SERIES_I_RAM_OFFSET_1 0x04000
+#define GVP_SERIES_I_RAM_OFFSET_2 0x04000
+#define GVP_SERIES_I_RAM_OFFSET_3 0x10000
+#define GVP_SERIES_I_RAM_MASK_1 (4096 - 1)
+#define GVP_SERIES_I_RAM_MASK_2 (16384 - 1)
+#define GVP_SERIES_I_RAM_MASK_3 (16384 - 1)
/* SuperDMAC CNTR bits. */
#define SCNTR_TCEN (1<<5)
static struct wd_state *wda2091[] = {
&wd_a2091,
- &wd_a2091_2,
+ &wd_a2091_2
};
static struct wd_state *wdscsi[] = {
static struct wd_state *gvpscsi[] = {
&wd_gvp,
- &wd_gvp_2,
+ &wd_gvp_2
};
static void reset_dmac(struct wd_state *wd)
break;
case COMMODORE_SDMAC:
case COMMODORE_DMAC:
+ case COMMODORE_8727:
wd->cdmac.dmac_dma = 0;
wd->cdmac.dmac_istr = 0;
wd->cdmac.dmac_cntr = 0;
switch (wd->dmac_type)
{
case GVP_DMAC_S1:
- return wd->gdmac.cntr && (wd->wc.auxstatus & ASR_INT) != 0;
+ if ((wd->gdmac.cntr & 0x80) && (wd->wc.auxstatus & ASR_INT))
+ return true;
+ break;
case GVP_DMAC_S2:
if (wd->wc.auxstatus & ASR_INT)
wd->gdmac.cntr |= 2;
- if ((wd->gdmac.cntr & (2 | 8)) == 10)
+ if ((wd->gdmac.cntr & (2 | 8)) == (2 | 8))
return true;
break;
case COMMODORE_SDMAC:
if ((wd->cdmac.dmac_cntr & CNTR_INTEN) && (wd->cdmac.dmac_istr & (ISTR_INTS | ISTR_E_INT)))
return true;
break;
+ case COMMODORE_8727:
+ if (wd->wc.auxstatus & ASR_INT)
+ wd->cdmac.dmac_istr |= ISTR_INTS;
+ if ((wd->cdmac.dmac_cntr & CNTR_INTEN) && (wd->cdmac.dmac_istr & ISTR_INTS))
+ return true;
+ break;
}
return false;
}
break;
case COMMODORE_SDMAC:
case COMMODORE_DMAC:
+ case COMMODORE_8727:
wds->cdmac.dmac_dma = -1;
break;
}
return wds->gdmac.dma_on > 0;
case COMMODORE_SDMAC:
case COMMODORE_DMAC:
+ case COMMODORE_8727:
return wds->cdmac.dmac_dma > 0;
}
return false;
void rethink_a2091 (void)
{
if (isirq (&wd_a2091) ||isirq (&wd_a2091_2) || isirq (&wd_a3000) || isirq(&wd_gvp) || isirq(&wd_gvp_2)) {
- uae_int_requested |= 2;
+ INTREQ_0(0x8000 | 0x0008);
#if A2091_DEBUG > 2 || A3000_DEBUG > 2
write_log (_T("Interrupt_RETHINK\n"));
#endif
- } else {
- uae_int_requested &= ~2;
}
}
return;
if (!(wd->wc.auxstatus & ASR_INT))
return;
- if (isirq(wd))
- uae_int_requested |= 2;
+ rethink_a2091();
}
static void dmac_a2091_xt_int(struct wd_state *wd)
if (!wd->enabled)
return;
wd->cdmac.xt_irq = true;
- if (isirq(wd))
- uae_int_requested |= 2;
+ rethink_a2091();
}
void scsi_dmac_a2091_start_dma (struct wd_state *wd)
static void set_status (struct wd_chip_state *wd, uae_u8 status, int delay)
{
- wd->queue_index++;
if (wd->queue_index >= WD_STATUS_QUEUE)
- wd->queue_index = 0;
+ return;
wd->scsidelay_status[wd->queue_index] = status;
wd->scsidelay_irq[wd->queue_index] = delay == 0 ? 1 : (delay <= 2 ? 2 : delay);
+ wd->queue_index++;
}
static void set_status (struct wd_chip_state *wd, uae_u8 status)
uae_u8 mode = wd->wdregs[WD_CONTROL] >> 5;
switch(wds->dmac_type)
{
+ case COMMODORE_8727:
+ if (mode != 0 && mode != 4) {
+ write_log (_T("%s weird DMA mode %d!!\n"), WD33C93, mode);
+ }
+ return mode == 4;
case COMMODORE_DMAC:
case COMMODORE_SDMAC:
case GVP_DMAC_S2:
}
}
+static bool dmacheck_a2090 (struct wd_state *wd)
+{
+ int dir = wd->cdmac.dmac_acr & 0x00800000;
+ wd->cdmac.dmac_acr &= 0x7fffff;
+ wd->cdmac.dmac_acr++;
+ wd->cdmac.dmac_acr &= 0x7fffff;
+ wd->cdmac.dmac_acr |= dir;
+ wd->cdmac.dmac_wtc--;
+ return wd->cdmac.dmac_wtc == 0;
+}
+
+
+static bool do_dma_commodore_8727(struct wd_state *wd, struct scsi_data *scsi)
+{
+ int dir = wd->cdmac.dmac_acr & 0x00800000;
+
+ if (scsi->direction < 0) {
+ if (dir) {
+ write_log(_T("8727 mismatched direction!\n"));
+ return false;
+ }
+#if WD33C93_DEBUG > 0
+ uaecptr odmac_acr = wd->cdmac.dmac_acr;
+#endif
+ for (;;) {
+ uae_u8 v1 = 0, v2 = 0;
+ int status;
+ status = scsi_receive_data (scsi, &v1);
+ if (!status)
+ status = scsi_receive_data (scsi, &v2);
+ put_word((wd->cdmac.dmac_acr << 1) & 0xffffff, (v1 << 8) | v2);
+ if (wd->wc.wd_dataoffset < sizeof wd->wc.wd_data) {
+ wd->wc.wd_data[wd->wc.wd_dataoffset++] = v1;
+ wd->wc.wd_data[wd->wc.wd_dataoffset++] = v2;
+ }
+ if (decreasetc (&wd->wc))
+ break;
+ if (decreasetc (&wd->wc))
+ break;
+ if (status)
+ break;
+ if (dmacheck_a2090 (wd))
+ break;
+ }
+#if WD33C93_DEBUG > 0
+ write_log (_T("%s Done DMA from WD, %d/%d %08X\n"), WD33C93, scsi->offset, scsi->data_len, (odmac_acr << 1) & 0xffffff);
+#endif
+ return true;
+ } else if (scsi->direction > 0) {
+ if (!dir) {
+ write_log(_T("8727 mismatched direction!\n"));
+ return false;
+ }
+#if WD33C93_DEBUG > 0
+ uaecptr odmac_acr = wd->cdmac.dmac_acr;
+#endif
+ for (;;) {
+ int status;
+ uae_u16 v = get_word((wd->cdmac.dmac_acr << 1) & 0xffffff);
+ if (wd->wc.wd_dataoffset < sizeof wd->wc.wd_data) {
+ wd->wc.wd_data[wd->wc.wd_dataoffset++] = v >> 8;
+ wd->wc.wd_data[wd->wc.wd_dataoffset++] = v;
+ }
+ status = scsi_send_data (scsi, v >> 8);
+ if (!status)
+ status = scsi_send_data (scsi, v);
+ if (decreasetc (&wd->wc))
+ break;
+ if (decreasetc (&wd->wc))
+ break;
+ if (status)
+ break;
+ if (dmacheck_a2090 (wd))
+ break;
+ }
+#if WD33C93_DEBUG > 0
+ write_log (_T("%s Done DMA to WD, %d/%d %08x\n"), WD33C93, scsi->offset, scsi->data_len, (odmac_acr << 1) & 0xffffff);
+#endif
+ return true;
+ }
+ return false;
+}
+
static bool do_dma_commodore(struct wd_state *wd, struct scsi_data *scsi)
{
if (wd->cdtv)
uae_u8 v;
int status = scsi_receive_data (scsi, &v);
wd->gdmac.buffer[wd->wc.wd_dataoffset++] = v;
- wd->wc.wd_dataoffset &= GVP_SERIES_I_RAM_MASK;
+ wd->wc.wd_dataoffset &= wd->gdmac.s1_rammask;
if (decreasetc (&wd->wc))
break;
if (status)
for (;;) {
int status;
uae_u8 v = wd->gdmac.buffer[wd->wc.wd_dataoffset++];
- wd->wc.wd_dataoffset &= GVP_SERIES_I_RAM_MASK;
+ wd->wc.wd_dataoffset &= wd->gdmac.s1_rammask;
status = scsi_send_data (scsi, v);
wd->gdmac.addr++;
if (decreasetc (&wd->wc))
case COMMODORE_DMAC:
case COMMODORE_SDMAC:
return do_dma_commodore(wd, scsi);
+ case COMMODORE_8727:
+ return do_dma_commodore_8727(wd, scsi);
case GVP_DMAC_S2:
return do_dma_gvp_s2(wd, scsi);
case GVP_DMAC_S1:
}
// 0x30 = command phase has started
scsi->data_len = tmp_tc;
- scsi_emulate_analyze (scsi);
- wd->wdregs[WD_COMMAND_PHASE] = 0x30 + gettc (wd);
- settc (wd, 0);
#if WD33C93_DEBUG > 0
write_log (_T("%s: Got Command %s, datalen=%d\n"), WD33C93, scsitostring (wd, scsi), scsi->data_len);
#endif
+ if (!scsi_emulate_analyze (scsi)) {
+ wd->wdregs[WD_COMMAND_PHASE] = 0x46;
+ goto end;
+ }
+ wd->wdregs[WD_COMMAND_PHASE] = 0x30 + gettc (wd);
+ settc (wd, 0);
}
if (wd->wdregs[WD_COMMAND_PHASE] <= 0x41) {
}
if (wd->scsi->direction) {
+ // wanted data but nothing available?
+ if (scsi->direction < 0 && scsi->data_len == 0 && gettc(wd)) {
+ setphase(wd, 0x46);
+ wd->wd_phase = CSR_UNEXP | PHS_STATUS;
+ set_status (wd, wd->wd_phase, 1);
+ return;
+ }
if (canwddma (wds)) {
if (scsi->direction <= 0) {
do_dma(wds);
}
if (gettc (wd) > 0) {
// requested more data than was available.
+ setphase(wd, 0x46);
wd->wd_phase = CSR_UNEXP | PHS_STATUS;
set_status (wd, wd->wd_phase, 1);
return;
set_status (wd, wd->wd_phase, 1);
return;
}
- wd->wdregs[WD_COMMAND_PHASE] = 0x46;
+ setphase(wd, 0x46);
}
}
wd->wd_selected = 0;
}
-static void wd_cmd_trans_info (struct wd_state *wds, struct scsi_data *scsi)
+static void wd_cmd_trans_info (struct wd_state *wds, struct scsi_data *scsi, bool pad)
{
struct wd_chip_state *wd = &wds->wc;
if (wd->wdregs[WD_COMMAND_PHASE] == 0x20) {
scsi->data_len = gettc (wd);
}
- if (canwddma (wds)) {
- wd->wd_data_avail = -1;
+ if (pad) {
+ int v;
+ settc(wd, 0);
+ if (wd->scsi->direction < 0) {
+ v = wd_do_transfer_in (wd, wd->scsi, false);
+ } else if (wd->scsi->direction > 0) {
+ v = wd_do_transfer_out (wd, wd->scsi);
+ }
+ wd->scsi->direction = 0;
+ wd->wd_data_avail = 0;
} else {
- wd->wd_data_avail = 1;
+ if (canwddma (wds)) {
+ wd->wd_data_avail = -1;
+ } else {
+ wd->wd_data_avail = 1;
+ }
}
#if WD33C93_DEBUG > 0
wd->scsi = NULL;
wd->scsidelay_irq[0] = 0;
wd->scsidelay_irq[1] = 0;
+ wd->queue_index = 0;
wd->auxstatus = 0;
wd->wd_data_avail = 0;
if (irq) {
}
}
+static void wd_master_reset(struct wd_chip_state *wd, bool irq)
+{
+ memset(wd->wdregs, 0, sizeof wd->wdregs);
+ wd_cmd_reset(wd, irq);
+}
+
static void wd_cmd_abort (struct wd_chip_state *wd)
{
#if WD33C93_DEBUG > 0
static void xt_command_done(struct wd_state *wd);
-static void wd_check_interrupt(struct wd_state *wds)
+static void wd_check_interrupt(struct wd_state *wds, bool checkonly)
{
struct wd_chip_state *wd = &wds->wc;
if (wd->auxstatus & ASR_INT)
return;
- for (int i = 0; i < WD_STATUS_QUEUE; i++) {
- if (wd->scsidelay_irq[i] == 1) {
- wd->scsidelay_irq[i] = 0;
- doscsistatus(wds, wd->scsidelay_status[i]);
- wd->wd_busy = 0;
- } else if (wd->scsidelay_irq[i] > 1) {
- wd->scsidelay_irq[i]--;
+ if (wd->queue_index == 0)
+ return;
+ if (wd->scsidelay_irq[0] == 1) {
+ wd->scsidelay_irq[0] = 0;
+ doscsistatus(wds, wd->scsidelay_status[0]);
+ wd->wd_busy = 0;
+ if (wd->queue_index == 2) {
+ wd->scsidelay_irq[0] = 1;
+ wd->scsidelay_status[0] = wd->scsidelay_status[1];
+ wd->queue_index = 1;
+ } else {
+ wd->queue_index = 0;
}
+ } else if (!checkonly && wd->scsidelay_irq[0] > 1) {
+ wd->scsidelay_irq[0]--;
}
}
xt_command_done(wds);
}
}
- wd_check_interrupt(wds);
+ wd_check_interrupt(wds, false);
}
if (!wds->enabled)
return;
scsi_hsync_check_dma(wds);
- wd_check_interrupt(wds);
+ wd_check_interrupt(wds, false);
}
void scsi_hsync (void)
write_comm_pipe_u32 (&wds->requests, makecmd (wd->scsi, 3, 0), 1);
}
} else if (wd->sasr == WD_SCSI_STATUS) {
- uae_int_requested &= ~2;
wd->auxstatus &= ~0x80;
if (wds->cdtv)
cdtv_scsi_clear_int ();
wds->cdmac.dmac_istr &= ~ISTR_INTS;
+ wd_check_interrupt(wds, true);
#if 0
if (wd->wdregs[WD_COMMAND_PHASE] == 0x10) {
wd->wdregs[WD_COMMAND_PHASE] = 0x11;
/* DMAC */
-static uae_u32 dmac_a2091_read_word (struct wd_state *wd, uaecptr addr)
-{
- uae_u32 v = 0;
-
- if (addr < 0x40)
- return (wd->dmacmemory[addr] << 8) | wd->dmacmemory[addr + 1];
- if (addr >= CDMAC_ROM_OFFSET) {
- if (wd->rom) {
- int off = addr & wd->rom_mask;
- if (wd->rombankswitcher && (addr & 0xffe0) == CDMAC_ROM_OFFSET)
- wd->rombank = (addr & 0x02) >> 1;
- off += wd->rombank * wd->rom_size;
- return (wd->rom[off] << 8) | wd->rom[off + 1];
- }
- return 0;
- }
- addr &= ~1;
- switch (addr)
- {
- case 0x40:
- v = wd->cdmac.dmac_istr;
- if (v && (wd->cdmac.dmac_cntr & CNTR_INTEN))
- v |= ISTR_INT_P;
- wd->cdmac.dmac_istr &= ~0xf;
- break;
- case 0x42:
- v = wd->cdmac.dmac_cntr;
- break;
- case 0x80:
- if (wd->cdmac.old_dmac)
- v = (wd->cdmac.dmac_wtc >> 16) & 0xffff;
- break;
- case 0x82:
- if (wd->cdmac.old_dmac)
- v = wd->cdmac.dmac_wtc & 0xffff;
- break;
- case 0x90:
- v = wdscsi_getauxstatus(&wd->wc);
- break;
- case 0x92:
- v = wdscsi_get(&wd->wc, wd);
- break;
- case 0xc0:
- v = 0xf8 | (1 << 0) | (1 << 1) | (1 << 2); // bits 0-2 = dip-switches
- break;
- case 0xc2:
- case 0xc4:
- case 0xc6:
- v = 0xffff;
- break;
- case 0xe0:
- if (wd->cdmac.dmac_dma <= 0)
- scsi_dmac_a2091_start_dma (wd);
- break;
- case 0xe2:
- scsi_dmac_a2091_stop_dma (wd);
- break;
- case 0xe4:
- dmac_a2091_cint (wd);
- break;
- case 0xe8:
- /* FLUSH (new only) */
- if (!wd->cdmac.old_dmac && wd->cdmac.dmac_dma > 0)
- wd->cdmac.dmac_istr |= ISTR_FE_FLG;
- break;
- }
+static uae_u8 dmac8727_read_pcss(struct wd_state *wd)
+{
+ uae_u8 v;
+ v = wd->cdmac.c8727_pcss;
#if A2091_DEBUG_IO > 0
- write_log (_T("dmac_wget %04X=%04X PC=%08X\n"), addr, v, M68K_GETPC);
+ write_log(_T("dmac8727_read_pcss %02x\n"), v);
#endif
return v;
}
-static uae_u32 dmac_a2091_read_byte (struct wd_state *wd, uaecptr addr)
+static uae_u8 dmac8727_read_pcsd(struct wd_state *wd)
{
- uae_u32 v = 0;
-
- if (addr < 0x40)
- return wd->dmacmemory[addr];
- if (addr >= CDMAC_ROM_OFFSET) {
- if (wd->rom) {
- int off = addr & wd->rom_mask;
- if (wd->rombankswitcher && (addr & 0xffe0) == CDMAC_ROM_OFFSET)
- wd->rombank = (addr & 0x02) >> 1;
- off += wd->rombank * wd->rom_size;
- return wd->rom[off];
- }
- return 0;
- }
-
- switch (addr)
+ struct commodore_dmac *c = &wd->cdmac;
+ uae_u8 v = 0;
+ switch(c->c8727_pcss)
{
- case 0x91:
- v = wdscsi_getauxstatus (&wd->wc);
+ case 0xf7:
+ wd->cdmac.dmac_dma = 1;
break;
- case 0x93:
- v = wdscsi_get (&wd->wc, wd);
- break;
- case 0xa1:
- case 0xa3:
- case 0xa5:
- case 0xa7:
- v = read_xt_reg(wd, (addr - 0xa0) / 2);
+ case 0xef:
+ v = (1 << 7) | (1 << 5); // dma complete, no overflow
break;
- default:
- v = dmac_a2091_read_word (wd, addr);
- if (!(addr & 1))
- v >>= 8;
+ default:
+ write_log(_T("dmac8727 read pscd %02x\n"), c->c8727_pcss);
break;
}
-#if A2091_DEBUG_IO > 0
- write_log (_T("dmac_bget %04X=%02X PC=%08X\n"), addr, v, M68K_GETPC);
-#endif
return v;
}
-static void dmac_a2091_write_word (struct wd_state *wd, uaecptr addr, uae_u32 b)
+static void dmac8727_write_pcss(struct wd_state *wd, uae_u8 v)
{
- if (addr < 0x40)
- return;
- if (addr >= CDMAC_ROM_OFFSET)
- return;
-
+ wd->cdmac.c8727_pcss = v;
#if A2091_DEBUG_IO > 0
- write_log (_T("dmac_wput %04X=%04X PC=%08X\n"), addr, b & 65535, M68K_GETPC);
+ write_log(_T("dmac8727_write_pcss %02x\n"), v);
#endif
+}
- addr &= ~1;
- switch (addr)
+static void dmac8727_write_pcsd(struct wd_state *wd, uae_u8 v)
+{
+ struct commodore_dmac *c = &wd->cdmac;
+ switch (c->c8727_pcss)
{
- case 0x42:
- wd->cdmac.dmac_cntr = b;
- if (wd->cdmac.dmac_cntr & CNTR_PREST)
- dmac_reset (wd);
+ case 0xfb:
+ c->dmac_acr &= 0xff00ffff;
+ c->dmac_acr |= v << 16;
break;
- case 0x80:
- wd->cdmac.dmac_wtc &= 0x0000ffff;
- wd->cdmac.dmac_wtc |= b << 16;
- break;
- case 0x82:
- wd->cdmac.dmac_wtc &= 0xffff0000;
- wd->cdmac.dmac_wtc |= b & 0xffff;
- break;
- case 0x84:
- wd->cdmac.dmac_acr &= 0x0000ffff;
- wd->cdmac.dmac_acr |= b << 16;
- break;
- case 0x86:
- wd->cdmac.dmac_acr &= 0xffff0000;
- wd->cdmac.dmac_acr |= b & 0xfffe;
- if (wd->cdmac.old_dmac)
- wd->cdmac.dmac_acr &= ~3;
- break;
- case 0x8e:
- wd->cdmac.dmac_dawr = b;
+ case 0xfd:
+ c->dmac_acr &= 0xffff00ff;
+ c->dmac_acr |= v << 8;
break;
- case 0x90:
- wdscsi_sasr (&wd->wc, b);
+ case 0xfe:
+ case 0xf6:
+ c->dmac_acr &= 0xffffff00;
+ c->dmac_acr |= v << 0;
+ c->dmac_wtc = 65535;
break;
- case 0x92:
- wdscsi_put (&wd->wc, wd, b);
- break;
- case 0xc2:
- case 0xc4:
- case 0xc6:
- break;
- case 0xe0:
- if (wd->cdmac.dmac_dma <= 0)
- scsi_dmac_a2091_start_dma (wd);
- break;
- case 0xe2:
- scsi_dmac_a2091_stop_dma (wd);
- break;
- case 0xe4:
- dmac_a2091_cint (wd);
+ case 0xff:
+ c->dmac_dma = 0;
break;
- case 0xe8:
- /* FLUSH */
- wd->cdmac.dmac_istr |= ISTR_FE_FLG;
+ default:
+ write_log(_T("dmac8727 pscd %02x = %02x\n"), c->c8727_pcss, v);
break;
}
}
-static void dmac_a2091_write_byte (struct wd_state *wd, uaecptr addr, uae_u32 b)
+static uae_u32 dmac_a2091_read_word (struct wd_state *wd, uaecptr addr)
{
+ uae_u32 v = 0;
+
if (addr < 0x40)
- return;
- if (addr >= CDMAC_ROM_OFFSET)
- return;
+ return (wd->dmacmemory[addr] << 8) | wd->dmacmemory[addr + 1];
-#if A2091_DEBUG_IO > 0
- write_log (_T("dmac_bput %04X=%02X PC=%08X\n"), addr, b & 255, M68K_GETPC);
-#endif
+ if (wd->dmac_type == COMMODORE_8727) {
- switch (addr)
- {
- case 0x91:
- wdscsi_sasr (&wd->wc, b);
- break;
- case 0x93:
- wdscsi_put (&wd->wc, wd, b);
- break;
- case 0xa1:
- case 0xa3:
- case 0xa5:
- case 0xa7:
- write_xt_reg(wd, (addr - 0xa0) / 2, b);
- break;
- default:
- if (addr & 1)
- dmac_a2091_write_word (wd, addr, b);
- else
- dmac_a2091_write_word (wd, addr, b << 8);
- }
-}
+ if (addr >= CDMAC_ROM_OFFSET) {
+ if (wd->rom) {
+ int off = addr & wd->rom_mask;
+ return (wd->rom[off] << 8) | wd->rom[off + 1];
+ }
+ return 0;
+ }
+ switch (addr)
+ {
+ case 0x40:
+ v = 0;
+ if (wd->cdmac.dmac_istr & ISTR_INTS)
+ v |= (1 << 7) | (1 << 4);
+ break;
+ case 0x42:
+ v = 0;
+ if (wd->cdmac.dmac_cntr & CNTR_INTEN)
+ v |= 1 << 4;
+ break;
+ case 0x60:
+ v = wdscsi_getauxstatus (&wd->wc);
+ break;
+ case 0x62:
+ v = wdscsi_get (&wd->wc, wd);
+ break;
+ case 0x64:
+ v = dmac8727_read_pcss(wd);
+ break;
+ case 0x68:
+ v = dmac8727_read_pcsd(wd);
+ break;
+ }
+ v <<= 8;
+ return v;
-static uae_u32 REGPARAM2 dmac_a2091_lget (struct wd_state *wd, uaecptr addr)
-{
- uae_u32 v;
-#ifdef JIT
- special_mem |= S_READ;
-#endif
- addr &= 65535;
- v = dmac_a2091_read_word(wd, addr) << 16;
- v |= dmac_a2091_read_word(wd, addr + 2) & 0xffff;
- return v;
-}
+ } else if (wd->dmac_type == COMMODORE_DMAC) {
+ if (addr >= CDMAC_ROM_OFFSET) {
+ if (wd->rom) {
+ int off = addr & wd->rom_mask;
+ if (wd->rombankswitcher && (addr & 0xffe0) == CDMAC_ROM_OFFSET)
+ wd->rombank = (addr & 0x02) >> 1;
+ off += wd->rombank * wd->rom_size;
+ return (wd->rom[off] << 8) | wd->rom[off + 1];
+ }
+ return 0;
+ }
-static uae_u32 REGPARAM2 dmac_a2091_wget(struct wd_state *wd, uaecptr addr)
-{
- uae_u32 v;
-#ifdef JIT
- special_mem |= S_READ;
+ addr &= ~1;
+ switch (addr)
+ {
+ case 0x40:
+ v = wd->cdmac.dmac_istr;
+ if (v && (wd->cdmac.dmac_cntr & CNTR_INTEN))
+ v |= ISTR_INT_P;
+ wd->cdmac.dmac_istr &= ~0xf;
+ break;
+ case 0x42:
+ v = wd->cdmac.dmac_cntr;
+ break;
+ case 0x80:
+ if (wd->cdmac.old_dmac)
+ v = (wd->cdmac.dmac_wtc >> 16) & 0xffff;
+ break;
+ case 0x82:
+ if (wd->cdmac.old_dmac)
+ v = wd->cdmac.dmac_wtc & 0xffff;
+ break;
+ case 0x90:
+ v = wdscsi_getauxstatus(&wd->wc);
+ break;
+ case 0x92:
+ v = wdscsi_get(&wd->wc, wd);
+ break;
+ case 0xc0:
+ v = 0xf8 | (1 << 0) | (1 << 1) | (1 << 2); // bits 0-2 = dip-switches
+ break;
+ case 0xc2:
+ case 0xc4:
+ case 0xc6:
+ v = 0xffff;
+ break;
+ case 0xe0:
+ if (wd->cdmac.dmac_dma <= 0)
+ scsi_dmac_a2091_start_dma (wd);
+ break;
+ case 0xe2:
+ scsi_dmac_a2091_stop_dma (wd);
+ break;
+ case 0xe4:
+ dmac_a2091_cint (wd);
+ break;
+ case 0xe8:
+ /* FLUSH (new only) */
+ if (!wd->cdmac.old_dmac && wd->cdmac.dmac_dma > 0)
+ wd->cdmac.dmac_istr |= ISTR_FE_FLG;
+ break;
+ }
+ }
+#if A2091_DEBUG_IO > 0
+ write_log (_T("dmac_wget %04X=%04X PC=%08X\n"), addr, v, M68K_GETPC);
#endif
- addr &= 65535;
- v = dmac_a2091_read_word(wd, addr);
return v;
}
-static uae_u32 REGPARAM2 dmac_a2091_bget(struct wd_state *wd, uaecptr addr)
+static uae_u32 dmac_a2091_read_byte (struct wd_state *wd, uaecptr addr)
{
- uae_u32 v;
+ uae_u32 v = 0;
+
+ if (addr < 0x40)
+ return wd->dmacmemory[addr];
+
+ if (wd->dmac_type == COMMODORE_8727) {
+
+ if (addr >= DMAC_8727_ROM_VECTOR) {
+ if (wd->rom) {
+ int off = addr & wd->rom_mask;
+ return wd->rom[off];
+ }
+ return 0;
+ }
+ switch (addr)
+ {
+ case 0x40:
+ v = 0;
+ if (wd->cdmac.dmac_istr & ISTR_INTS)
+ v |= (1 << 7) | (1 << 4);
+ break;
+ case 0x42:
+ v = 0;
+ if (wd->cdmac.dmac_cntr & CNTR_INTEN)
+ v |= 1 << 4;
+ v |= wd->cdmac.c8727_ctl & 0x80;
+ break;
+ case 0x60:
+ v = wdscsi_getauxstatus (&wd->wc);
+ break;
+ case 0x62:
+ v = wdscsi_get (&wd->wc, wd);
+ break;
+ case 0x64:
+ v = dmac8727_read_pcss(wd);
+ break;
+ case 0x68:
+ v = dmac8727_read_pcsd(wd);
+ break;
+ }
+
+ } else if (wd->dmac_type == COMMODORE_DMAC) {
+ if (addr >= CDMAC_ROM_OFFSET) {
+ if (wd->rom) {
+ int off = addr & wd->rom_mask;
+ if (wd->rombankswitcher && (addr & 0xffe0) == CDMAC_ROM_OFFSET)
+ wd->rombank = (addr & 0x02) >> 1;
+ off += wd->rombank * wd->rom_size;
+ return wd->rom[off];
+ }
+ return 0;
+ }
+
+ switch (addr)
+ {
+ case 0x91:
+ v = wdscsi_getauxstatus (&wd->wc);
+ break;
+ case 0x93:
+ v = wdscsi_get (&wd->wc, wd);
+ break;
+ case 0xa1:
+ case 0xa3:
+ case 0xa5:
+ case 0xa7:
+ v = read_xt_reg(wd, (addr - 0xa0) / 2);
+ break;
+ default:
+ v = dmac_a2091_read_word (wd, addr);
+ if (!(addr & 1))
+ v >>= 8;
+ break;
+ }
+ }
+#if A2091_DEBUG_IO > 0
+ write_log (_T("dmac_bget %04X=%02X PC=%08X\n"), addr, v, M68K_GETPC);
+#endif
+ return v;
+}
+
+static void dmac_a2091_write_word (struct wd_state *wd, uaecptr addr, uae_u32 b)
+{
+#if A2091_DEBUG_IO > 0
+ write_log (_T("dmac_wput %04X=%04X PC=%08X\n"), addr, b & 65535, M68K_GETPC);
+#endif
+
+ if (addr < 0x40)
+ return;
+
+ if (wd->dmac_type == COMMODORE_8727) {
+
+ if (addr >= DMAC_8727_ROM_VECTOR)
+ return;
+
+ b >>= 8;
+ switch(addr)
+ {
+ case 0x40:
+ break;
+ case 0x42:
+ wd->cdmac.dmac_cntr &= ~CNTR_INTEN;
+ if (b & (1 << 4))
+ wd->cdmac.dmac_cntr |= CNTR_INTEN;
+ break;
+ case 0x50:
+ // clear interrupt
+ wd->cdmac.dmac_istr &= ~(ISTR_INT_F | ISTR_INTS);
+ break;
+ case 0x60:
+ wdscsi_sasr (&wd->wc, b);
+ break;
+ case 0x62:
+ wdscsi_put (&wd->wc, wd, b);
+ break;
+ case 0x64:
+ dmac8727_write_pcss(wd, b);
+ break;
+ case 0x68:
+ dmac8727_write_pcsd(wd, b);
+ break;
+ }
+
+
+ } else if (wd->dmac_type == COMMODORE_DMAC) {
+
+ if (addr >= CDMAC_ROM_OFFSET)
+ return;
+
+ addr &= ~1;
+ switch (addr)
+ {
+ case 0x42:
+ wd->cdmac.dmac_cntr = b;
+ if (wd->cdmac.dmac_cntr & CNTR_PREST)
+ dmac_reset (wd);
+ break;
+ case 0x80:
+ wd->cdmac.dmac_wtc &= 0x0000ffff;
+ wd->cdmac.dmac_wtc |= b << 16;
+ break;
+ case 0x82:
+ wd->cdmac.dmac_wtc &= 0xffff0000;
+ wd->cdmac.dmac_wtc |= b & 0xffff;
+ break;
+ case 0x84:
+ wd->cdmac.dmac_acr &= 0x0000ffff;
+ wd->cdmac.dmac_acr |= b << 16;
+ break;
+ case 0x86:
+ wd->cdmac.dmac_acr &= 0xffff0000;
+ wd->cdmac.dmac_acr |= b & 0xfffe;
+ if (wd->cdmac.old_dmac)
+ wd->cdmac.dmac_acr &= ~3;
+ break;
+ case 0x8e:
+ wd->cdmac.dmac_dawr = b;
+ break;
+ case 0x90:
+ wdscsi_sasr (&wd->wc, b);
+ break;
+ case 0x92:
+ wdscsi_put (&wd->wc, wd, b);
+ break;
+ case 0xc2:
+ case 0xc4:
+ case 0xc6:
+ break;
+ case 0xe0:
+ if (wd->cdmac.dmac_dma <= 0)
+ scsi_dmac_a2091_start_dma (wd);
+ break;
+ case 0xe2:
+ scsi_dmac_a2091_stop_dma (wd);
+ break;
+ case 0xe4:
+ dmac_a2091_cint (wd);
+ break;
+ case 0xe8:
+ /* FLUSH */
+ wd->cdmac.dmac_istr |= ISTR_FE_FLG;
+ break;
+ }
+ }
+}
+
+static void dmac_a2091_write_byte (struct wd_state *wd, uaecptr addr, uae_u32 b)
+{
+#if A2091_DEBUG_IO > 0
+ write_log (_T("dmac_bput %04X=%02X PC=%08X\n"), addr, b & 255, M68K_GETPC);
+#endif
+
+ if (addr < 0x40)
+ return;
+
+ if (wd->dmac_type == COMMODORE_8727) {
+
+ if (addr >= DMAC_8727_ROM_VECTOR)
+ return;
+
+ switch(addr)
+ {
+ case 0x40:
+ break;
+ case 0x42:
+ wd->cdmac.dmac_cntr &= ~CNTR_INTEN;
+ if (b & (1 << 4))
+ wd->cdmac.dmac_cntr |= CNTR_INTEN;
+ wd->cdmac.c8727_ctl = b;
+ break;
+ case 0x50:
+ // clear interrupt
+ wd->cdmac.dmac_istr &= ~(ISTR_INT_F | ISTR_INTS);
+ break;
+ case 0x60:
+ wdscsi_sasr (&wd->wc, b);
+ break;
+ case 0x62:
+ wdscsi_put (&wd->wc, wd, b);
+ break;
+ case 0x64:
+ dmac8727_write_pcss(wd, b);
+ break;
+ case 0x68:
+ dmac8727_write_pcsd(wd, b);
+ break;
+ }
+
+ } else if (wd->dmac_type == COMMODORE_DMAC) {
+
+ if (addr >= CDMAC_ROM_OFFSET)
+ return;
+
+ switch (addr)
+ {
+ case 0x91:
+ wdscsi_sasr (&wd->wc, b);
+ break;
+ case 0x93:
+ wdscsi_put (&wd->wc, wd, b);
+ break;
+ case 0xa1:
+ case 0xa3:
+ case 0xa5:
+ case 0xa7:
+ write_xt_reg(wd, (addr - 0xa0) / 2, b);
+ break;
+ default:
+ if (addr & 1)
+ dmac_a2091_write_word (wd, addr, b);
+ else
+ dmac_a2091_write_word (wd, addr, b << 8);
+ }
+ }
+}
+
+static uae_u32 REGPARAM2 dmac_a2091_lget (struct wd_state *wd, uaecptr addr)
+{
+ uae_u32 v;
+#ifdef JIT
+ special_mem |= S_READ;
+#endif
+ addr &= 65535;
+ v = dmac_a2091_read_word(wd, addr) << 16;
+ v |= dmac_a2091_read_word(wd, addr + 2) & 0xffff;
+ return v;
+}
+
+static uae_u32 REGPARAM2 dmac_a2091_wget(struct wd_state *wd, uaecptr addr)
+{
+ uae_u32 v;
+#ifdef JIT
+ special_mem |= S_READ;
+#endif
+ addr &= 65535;
+ v = dmac_a2091_read_word(wd, addr);
+ return v;
+}
+
+static uae_u32 REGPARAM2 dmac_a2091_bget(struct wd_state *wd, uaecptr addr)
+{
+ uae_u32 v;
#ifdef JIT
special_mem |= S_READ;
#endif
{
uae_u32 v = 0;
- addr &= 0xffff;
+ addr &= wd->board_mask;
if (addr < 0x3e) {
v = wd->dmacmemory[addr];
- } else if (addr >= GVP_ROM_OFFSET) {
+ } else if (addr >= GVP_ROM_OFFSET && addr < 65536) {
if (wd->gdmac.series2) {
if (addr & 1) {
v = wd->gdmac.version;
}
}
} else {
- if (wd->rom) {
+ if ((addr & 1) && wd->gdmac.use_version) {
+ v = wd->gdmac.version;
+ } else if (wd->rom) {
v = wd->rom[addr - GVP_ROM_OFFSET];
}
}
- } else if (addr >= GVP_SERIES_I_RAM_OFFSET && !wd->gdmac.series2) {
+ } else if (addr >= wd->gdmac.s1_ramoffset && !wd->gdmac.series2) {
+#if GVP_S1_DEBUG_IO > 1
+ int off = wd->gdmac.bufoffset;
+#endif
v = wd->gdmac.buffer[wd->gdmac.bufoffset++];
- wd->gdmac.bufoffset &= GVP_SERIES_I_RAM_MASK;
+ wd->gdmac.bufoffset &= wd->gdmac.s1_rammask;
+#if GVP_S1_DEBUG_IO > 1
+ write_log(_T("gvp_s1_bget sram %d %04x\n"), off, v);
+#endif
} else if (wd->configured) {
if (wd->gdmac.series2) {
switch (addr)
switch (addr)
{
case 0x3e:
- v = wd->wc.auxstatus & ASR_INT;
+ v = (wd->wc.auxstatus & ASR_INT) ? 0x80 : 0x00;
break;
case 0x60: // SASR
v = wdscsi_getauxstatus(&wd->wc);
case 0x62: // SCMD
v = wdscsi_get(&wd->wc, wd);
break;
+ case 0x68:
+ v = 0;
+ break;
default:
write_log(_T("gvp_s1_bget_unk %04X PC=%08X\n"), addr, M68K_GETPC);
break;
return v;
}
+
static uae_u32 dmac_gvp_read_word(struct wd_state *wd, uaecptr addr)
{
uae_u32 v = 0;
- addr &= 0xffff;
+ addr &= wd->board_mask;
if (addr < 0x3e) {
v = (wd->dmacmemory[addr] << 8) | wd->dmacmemory[addr + 1];
- } else if (addr >= GVP_ROM_OFFSET) {
+ } else if (addr >= GVP_ROM_OFFSET && addr < 65536) {
if (wd->gdmac.series2) {
if (wd->rom) {
if (wd->rombankswitcher && (addr & 0xffe0) == GVP_ROM_OFFSET)
if (wd->rom) {
v = (wd->rom[addr - GVP_ROM_OFFSET] << 8) | (wd->rom[addr - GVP_ROM_OFFSET + 1]);
}
+ if (wd->gdmac.use_version) {
+ v &= 0xff00;
+ v |= wd->gdmac.version;
+ }
}
- } else if (addr >= GVP_SERIES_I_RAM_OFFSET && !wd->gdmac.series2) {
+ } else if (addr >= wd->gdmac.s1_ramoffset && !wd->gdmac.series2) {
#if GVP_S1_DEBUG_IO > 1
int off = wd->gdmac.bufoffset;
#endif
v = wd->gdmac.buffer[wd->gdmac.bufoffset++] << 8;
- wd->gdmac.bufoffset &= GVP_SERIES_I_RAM_MASK;
+ wd->gdmac.bufoffset &= wd->gdmac.s1_rammask;
v |= wd->gdmac.buffer[wd->gdmac.bufoffset++] << 0;
- wd->gdmac.bufoffset &= GVP_SERIES_I_RAM_MASK;
+ wd->gdmac.bufoffset &= wd->gdmac.s1_rammask;
#if GVP_S1_DEBUG_IO > 1
write_log(_T("gvp_s1_wget sram %d %04x\n"), off, v);
#endif
write_log(_T("gvp_s2_wget %04X=%04X PC=%08X\n"), addr, v, M68K_GETPC);
#endif
} else {
+
+ v = dmac_gvp_read_byte(wd, addr) << 8;
+ v |= dmac_gvp_read_byte(wd, addr + 1);
+
#if GVP_S1_DEBUG_IO > 0
write_log(_T("gvp_s1_wget %04X=%04X PC=%08X\n"), addr, v, M68K_GETPC);
#endif
return v;
}
-static void dmac_gvp_write_word(struct wd_state *wd, uaecptr addr, uae_u32 b)
+static void dmac_gvp_write_byte(struct wd_state *wd, uaecptr addr, uae_u32 b)
{
- addr &= 0xffff;
+ addr &= wd->board_mask;
if (addr >= GVP_ROM_OFFSET)
return;
- if (addr >= GVP_SERIES_I_RAM_OFFSET && !wd->gdmac.series2) {
+ if (addr >= wd->gdmac.s1_ramoffset && !wd->gdmac.series2) {
#if GVP_S1_DEBUG_IO > 1
int off = wd->gdmac.bufoffset;
#endif
- wd->gdmac.buffer[wd->gdmac.bufoffset++] = b >> 8;
- wd->gdmac.bufoffset &= GVP_SERIES_I_RAM_MASK;
wd->gdmac.buffer[wd->gdmac.bufoffset++] = b;
- wd->gdmac.bufoffset &= GVP_SERIES_I_RAM_MASK;
+ wd->gdmac.bufoffset &= wd->gdmac.s1_rammask;
#if GVP_S1_DEBUG_IO > 1
- write_log(_T("gvp_s1_wput sram %d %04x\n"), off, b);
+ write_log(_T("gvp_s1_bput sram %d %04x\n"), off, b);
#endif
return;
}
- if (wd->gdmac.series2) {
-#if GVP_S2_DEBUG_IO > 0
- write_log(_T("gvp_s2_wput %04X=%04X PC=%08X\n"), addr, b & 65535, M68K_GETPC);
-#endif
- switch (addr)
- {
- case 0x40:
- b &= ~(1 | 2);
- wd->gdmac.cntr = b;
- break;
- case 0x68: // bank
- if (b != 0)
- write_log(_T("bank %02x\n"), b);
- break;
- case 0x70: // ACR
- wd->gdmac.addr &= 0x0000ffff;
- wd->gdmac.addr |= (b & 0xff) << 16;
- wd->gdmac.addr &= wd->gdmac.addr_mask;
- break;
- case 0x72: // ACR
- wd->gdmac.addr &= 0xffff0000;
- wd->gdmac.addr |= b;
- wd->gdmac.addr &= wd->gdmac.addr_mask;
- break;
- case 0x76: // START DMA
- wd->gdmac.dma_on = 1;
- break;
- case 0x78: // STOP DMA
- wd->gdmac.dma_on = 0;
- break;
- case 0x74: // "secret1"
- case 0x7a: // "secret2"
- case 0x7c: // "secret3"
- write_log(_T("gvp_s2_wput_config %04X=%04X PC=%08X\n"), addr, b & 65535, M68K_GETPC);
- break;
- default:
- write_log(_T("gvp_s2_wput_unk %04X=%04X PC=%08X\n"), addr, b & 65535, M68K_GETPC);
- break;
- }
- } else {
-#if GVP_S1_DEBUG_IO > 0
- write_log(_T("gvp_s1_wput %04X=%04X PC=%08X\n"), addr, b & 65535, M68K_GETPC);
-#endif
- }
-}
-
-static void dmac_gvp_write_byte(struct wd_state *wd, uaecptr addr, uae_u32 b)
-{
- addr &= 0xffff;
-
- if (addr >= GVP_ROM_OFFSET)
- return;
-
- if (addr >= GVP_SERIES_I_RAM_OFFSET && !wd->gdmac.series2) {
- wd->gdmac.buffer[wd->gdmac.bufoffset++] = b;
- wd->gdmac.bufoffset &= GVP_SERIES_I_RAM_MASK;
- return;
- }
-
if (wd->gdmac.series2) {
#if GVP_S2_DEBUG_IO > 0
write_log(_T("gvp_s2_bput %04X=%02X PC=%08X\n"), addr, b & 255, M68K_GETPC);
#if GVP_S1_DEBUG_IO > 0
write_log(_T("gvp_s1_bput_s1 %04X=%04X PC=%08X\n"), addr, b & 255, M68K_GETPC);
#endif
- wd->gdmac.cntr = b & 8;
+ if (!(wd->gdmac.cntr & 8) && (b & 8))
+ wd_master_reset(&wd->wc, true);
+ wd->gdmac.cntr = b;
break;
default:
}
+static void dmac_gvp_write_word(struct wd_state *wd, uaecptr addr, uae_u32 b)
+{
+ addr &= wd->board_mask;
+
+ if (addr >= GVP_ROM_OFFSET && addr < 65536)
+ return;
+
+ if (addr >= wd->gdmac.s1_ramoffset && !wd->gdmac.series2) {
+#if GVP_S1_DEBUG_IO > 1
+ int off = wd->gdmac.bufoffset;
+#endif
+ wd->gdmac.buffer[wd->gdmac.bufoffset++] = b >> 8;
+ wd->gdmac.bufoffset &= wd->gdmac.s1_rammask;
+ wd->gdmac.buffer[wd->gdmac.bufoffset++] = b;
+ wd->gdmac.bufoffset &= wd->gdmac.s1_rammask;
+#if GVP_S1_DEBUG_IO > 1
+ write_log(_T("gvp_s1_wput sram %d %04x\n"), off, b);
+#endif
+ return;
+ }
+
+ if (wd->gdmac.series2) {
+#if GVP_S2_DEBUG_IO > 0
+ write_log(_T("gvp_s2_wput %04X=%04X PC=%08X\n"), addr, b & 65535, M68K_GETPC);
+#endif
+ switch (addr)
+ {
+ case 0x40:
+ b &= ~(1 | 2);
+ wd->gdmac.cntr = b;
+ break;
+ case 0x68: // bank
+ if (b != 0)
+ write_log(_T("bank %02x\n"), b);
+ break;
+ case 0x70: // ACR
+ wd->gdmac.addr &= 0x0000ffff;
+ wd->gdmac.addr |= (b & 0xff) << 16;
+ wd->gdmac.addr &= wd->gdmac.addr_mask;
+ break;
+ case 0x72: // ACR
+ wd->gdmac.addr &= 0xffff0000;
+ wd->gdmac.addr |= b;
+ wd->gdmac.addr &= wd->gdmac.addr_mask;
+ break;
+ case 0x76: // START DMA
+ wd->gdmac.dma_on = 1;
+ break;
+ case 0x78: // STOP DMA
+ wd->gdmac.dma_on = 0;
+ break;
+ case 0x74: // "secret1"
+ case 0x7a: // "secret2"
+ case 0x7c: // "secret3"
+ write_log(_T("gvp_s2_wput_config %04X=%04X PC=%08X\n"), addr, b & 65535, M68K_GETPC);
+ break;
+ default:
+ write_log(_T("gvp_s2_wput_unk %04X=%04X PC=%08X\n"), addr, b & 65535, M68K_GETPC);
+ break;
+ }
+
+ } else {
+
+ dmac_gvp_write_byte(wd, addr, b >> 8);
+ dmac_gvp_write_byte(wd, addr + 1, b);
+
+#if GVP_S1_DEBUG_IO > 0
+ write_log(_T("gvp_s1_wput %04X=%04X PC=%08X\n"), addr, b & 65535, M68K_GETPC);
+#endif
+ }
+}
+
static uae_u32 REGPARAM2 dmac_gvp_lget(struct wd_state *wd, uaecptr addr)
{
uae_u32 v;
#ifdef JIT
special_mem |= S_READ;
#endif
- addr &= 65535;
+ addr &= wd->board_mask;
v = dmac_gvp_read_word(wd, addr) << 16;
v |= dmac_gvp_read_word(wd, addr + 2) & 0xffff;
return v;
#ifdef JIT
special_mem |= S_READ;
#endif
- addr &= 65535;
+ addr &= wd->board_mask;
v = dmac_gvp_read_word(wd, addr);
return v;
}
#ifdef JIT
special_mem |= S_READ;
#endif
- addr &= 65535;
+ addr &= wd->board_mask;
v = dmac_gvp_read_byte(wd, addr);
return v;
}
#ifdef JIT
special_mem |= S_WRITE;
#endif
- addr &= 65535;
+ addr &= wd->board_mask;
dmac_gvp_write_word(wd, addr + 0, l >> 16);
dmac_gvp_write_word(wd, addr + 2, l);
}
#ifdef JIT
special_mem |= S_WRITE;
#endif
- addr &= 65535;
+ addr &= wd->board_mask;
dmac_gvp_write_word(wd, addr, w);
}
static void REGPARAM2 dmac_gvp_bput(struct wd_state *wd, uaecptr addr, uae_u32 b)
special_mem |= S_WRITE;
#endif
b &= 0xff;
- addr &= 65535;
+ addr &= wd->board_mask;
if (wd->autoconfig) {
addrbank *ab = wd == &wd_gvp ? &gvp_bank : &gvp_2_bank;
if (addr == 0x48 && !wd->configured) {
- map_banks_z2(ab, b, 0x10000 >> 16);
+ map_banks_z2(ab, b, (wd->board_mask + 1) >> 16);
wd->configured = 1;
expamem_next(ab, NULL);
return;
#ifdef JIT
special_mem |= S_READ;
#endif
- addr &= 65535;
+ addr &= wd->board_mask;
if (addr >= GVP_ROM_OFFSET) {
addr -= GVP_ROM_OFFSET;
v = (wd->rom[addr & wd->rom_mask] << 8) | wd->rom[(addr + 1) & wd->rom_mask];
#ifdef JIT
special_mem |= S_READ;
#endif
- addr &= 65535;
+ addr &= wd->board_mask;
v = dmac_gvp_wgeti(wd, addr) << 16;
v |= dmac_gvp_wgeti(wd, addr + 2);
return v;
wd_cmd_sel_xfer (wd, wds, false);
break;
case WD_CMD_TRANS_INFO:
- wd_cmd_trans_info (wds, wd->scsi);
+ wd_cmd_trans_info (wds, wd->scsi, false);
break;
case WD_CMD_TRANS_ADDR:
wd_cmd_trans_addr(wd, wds);
if (wd->wd_phase == CSR_MSGIN && wd->wd_selected)
wd_do_transfer_in(wd, wd->scsi, false);
break;
+ case WD_CMD_TRANSFER_PAD:
+ wd_cmd_trans_info (wds, wd->scsi, true);
+ break;
default:
wd->wd_busy = false;
write_log (_T("%s unimplemented/unknown command %02X\n"), WD33C93, cmd);
}
}
+int a2090_add_scsi_unit(int ch, struct uaedev_config_info *ci)
+{
+ struct wd_state *wd = wda2091[ci->controller_type_unit];
+
+ if (ci->type == UAEDEV_CD)
+ return add_scsi_cd(wd->scsis, ch, ci->device_emu_unit);
+ else if (ci->type == UAEDEV_TAPE)
+ return add_scsi_tape(wd->scsis, ch, ci->rootdir, ci->readonly);
+ else
+ return add_scsi_hd(wd->scsis, ch, NULL, ci, 1);
+}
+
int a2091_add_scsi_unit(int ch, struct uaedev_config_info *ci)
{
struct wd_state *wd = wda2091[ci->controller_type_unit];
xt_reset(wd);
}
+static void a2090_reset_device(struct wd_state *wd)
+{
+ wd->configured = 0;
+ wd->wc.wd_used = 0;
+ wd->wc.wd33c93_ver = 1;
+ wd->dmac_type = COMMODORE_8727;
+ wd->cdmac.old_dmac = 0;
+ wd_cmd_reset (&wd->wc, false);
+ reset_dmac(wd);
+ if (wd == &wd_a2091)
+ wd->name = _T("A2090");
+ if (wd == &wd_a2091_2)
+ wd->name = _T("A2090 #2");
+}
+
void a2091_reset (void)
{
- a2091_reset_device(&wd_a2091);
- a2091_reset_device(&wd_a2091_2);
+ struct romconfig *rc;
+
+ rc = get_device_romconfig(&currprefs, 0, ROMTYPE_A2091);
+ if (rc) {
+ a2091_reset_device(&wd_a2091);
+ a2091_reset_device(&wd_a2091_2);
+ }
+ rc = get_device_romconfig(&currprefs, 0, ROMTYPE_A2090);
+ if (rc) {
+ a2090_reset_device(&wd_a2091);
+ a2090_reset_device(&wd_a2091_2);
+ }
}
addrbank *a2091_init (int devnum)
return &expamem_null;
init_wd_scsi(wd);
+
+ rc = get_device_romconfig(&currprefs, devnum, ROMTYPE_A2091);
+ if (rc)
+ wd->cdmac.old_dmac = rc->subtype == 0;
+
wd->configured = 0;
wd->autoconfig = true;
+ wd->board_mask = 65535;
+ wd->bank = devnum ? &dmaca2091_2_bank : &dmaca2091_bank;
+ wd->bank->name = devnum ? _T("A2091 2nd") : _T("A2091");
memset (wd->dmacmemory, 0xff, sizeof wd->dmacmemory);
ew (wd, 0x00, 0xc0 | 0x01 | 0x10);
/* A590/A2091 hardware id */
memset(wd->rom, 0xff, slotsize);
wd->rom_size = 16384;
wd->rom_mask = wd->rom_size - 1;
- rc = get_device_romconfig(&currprefs, devnum, ROMTYPE_A2091);
if (rc && !rc->autoboot_disabled) {
if (is_device_rom(&currprefs, devnum, ROMTYPE_A2091)) {
struct zfile *z = read_device_rom(&currprefs, devnum, ROMTYPE_A2091, roms);
return wd == &wd_a2091 ? &dmaca2091_bank : &dmaca2091_2_bank;
}
+addrbank *a2090_init (int devnum)
+{
+ struct wd_state *wd = wda2091[devnum];
+ int roms[6];
+ int slotsize;
+ struct romconfig *rc = NULL;
+
+ if (devnum > 0 && !wd->enabled)
+ return &expamem_null;
+
+ init_wd_scsi(wd);
+
+ rc = get_device_romconfig(&currprefs, devnum, ROMTYPE_A2090);
+
+ wd->configured = 0;
+ wd->autoconfig = true;
+ wd->board_mask = 65535;
+ wd->bank = devnum ? &dmaca2091_2_bank : &dmaca2091_bank;
+ wd->bank->name = devnum ? _T("A2090a 2nd") : _T("A2090a");
+ memset (wd->dmacmemory, 0xff, sizeof wd->dmacmemory);
+ ew (wd, 0x00, 0xc0 | 0x01 | 0x10);
+ /* A590/A2091 hardware id */
+ ew(wd, 0x04, rc->subtype ? 0x02 : 0x01);
+ /* commodore's manufacturer id */
+ ew (wd, 0x10, 0x02);
+ ew (wd, 0x14, 0x02);
+ /* rom vector */
+ ew (wd, 0x28, DMAC_8727_ROM_VECTOR >> 8);
+ ew (wd, 0x2c, DMAC_8727_ROM_VECTOR);
+
+ ew (wd, 0x18, 0x00); /* ser.no. Byte 0 */
+ ew (wd, 0x1c, 0x00); /* ser.no. Byte 1 */
+ ew (wd, 0x20, 0x00); /* ser.no. Byte 2 */
+ ew (wd, 0x24, 0x00); /* ser.no. Byte 3 */
+
+ ew(wd, 0x30, 0x80); // SCSI only flag
+
+ roms[0] = 122;
+ roms[1] = -1;
+
+ wd->rombankswitcher = 0;
+ wd->rombank = 0;
+ slotsize = 65536;
+ wd->rom = xcalloc (uae_u8, slotsize);
+ memset(wd->rom, 0xff, slotsize);
+ wd->rom_size = 16384;
+ wd->rom_mask = wd->rom_size - 1;
+ if (rc && !rc->autoboot_disabled) {
+ if (is_device_rom(&currprefs, devnum, ROMTYPE_A2090)) {
+ struct zfile *z = read_device_rom(&currprefs, devnum, ROMTYPE_A2090, roms);
+ if (z) {
+ write_log (_T("A2090a BOOT ROM '%s'\n"), zfile_getname (z));
+ wd->rom_size = zfile_size (z);
+ zfile_fread (wd->rom, wd->rom_size, 1, z);
+ zfile_fclose (z);
+ for (int i = 1; i < slotsize / wd->rom_size; i++) {
+ memcpy (wd->rom + i * wd->rom_size, wd->rom, wd->rom_size);
+ }
+ wd->rom_mask = wd->rom_size - 1;
+ } else {
+ romwarning (roms);
+ }
+ }
+ }
+ return wd->bank;
+}
+
void gvp_free_device (struct wd_state *wd)
{
scsi_freenative(wd->scsis);
gvp_reset_device(&wd_gvp_2);
}
-static const uae_u8 gvp_scsi_i_autoconfig[16] = { 0xd1, 0x02, 0x00, 0x00, 0x07, 0xe1, 0xee, 0xee, 0xee, 0xee, 0x80, 0x00 };
-static const uae_u8 gvp_scsi_ii_autoconfig[16] = { 0xd1, 0x0b, 0x00, 0x00, 0x07, 0xe1, 0xee, 0xee, 0xee, 0xee, 0x80, 0x00 };
+static const uae_u8 gvp_scsi_i_autoconfig_1[16] = { 0xd1, 0x01, 0x00, 0x00, 0x07, 0xe1, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00 };
+static const uae_u8 gvp_scsi_i_autoconfig_2[16] = { 0xd1, 0x02, 0x00, 0x00, 0x07, 0xe1, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00 };
+static const uae_u8 gvp_scsi_i_autoconfig_3[16] = { 0xd2, 0x03, 0x00, 0x00, 0x07, 0xe1, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00 };
+static const uae_u8 gvp_scsi_ii_autoconfig[16] = { 0xd1, 0x0b, 0x00, 0x00, 0x07, 0xe1, 0xee, 0xee, 0xee, 0xee, 0x80, 0x00 };
static bool is_gvp_accelerator(void)
{
- return currprefs.cpuboard_type == BOARD_GVP_A530 ||
- currprefs.cpuboard_type == BOARD_GVP_GFORCE_030;
+ return currprefs.cpuboard_type == BOARD_GVP;
}
static addrbank *gvp_init(int devnum, bool series2)
{
- struct wd_state *wd = gvpscsi[devnum];
+ struct wd_state *wd;
int roms[6];
bool isscsi = true;
struct romconfig *rc = NULL;
+ const uae_u8 *ac;
+ int romtype;
+
+ if (devnum >= 0) {
+ romtype = series2 ? ROMTYPE_GVPS2 : ROMTYPE_GVPS1;
+ } else {
+ devnum = 0;
+ romtype = ROMTYPE_CPUBOARD;
+ }
+ wd = gvpscsi[devnum];
- if (devnum > 0 && !wd->enabled && currprefs.cpuboard_type != BOARD_GVP_A530)
+ if (devnum > 0 && !wd->enabled)
return &expamem_null;
init_wd_scsi(wd);
wd->rombankswitcher = 0;
memset(wd->dmacmemory, 0xff, sizeof wd->dmacmemory);
wd->gdmac.series2 = series2;
+ wd->gdmac.use_version = series2;
+ wd->board_mask = 65535;
roms[0] = 109;
roms[1] = 110;
wd->rom = xcalloc(uae_u8, wd->rom_size);
memset(wd->rom, 0xff, wd->rom_size);
wd->rom_mask = 32768 - 1;
-
- rc = get_device_romconfig(&currprefs, devnum, series2 ? ROMTYPE_GVPS2 : ROMTYPE_GVPS1);
- if (rc && !rc->autoboot_disabled) {
- if (is_device_rom(&currprefs, devnum, series2 ? ROMTYPE_GVPS2 : ROMTYPE_GVPS1)) {
- struct zfile *z = read_device_rom(&currprefs, devnum, series2 ? ROMTYPE_GVPS2 : ROMTYPE_GVPS1, roms);
- if (z) {
- write_log(_T("GVP BOOT ROM '%s'\n"), zfile_getname(z));
- int size = zfile_size(z);
- if (series2) {
- zfile_fread(wd->rom, 1, wd->rom_size, z);
- } else {
- xfree(wd->gdmac.buffer);
- wd->gdmac.buffer = xcalloc(uae_u8, GVP_SERIES_I_RAM_MASK + 1);
- for (int i = 0; i < 16384; i++) {
- uae_u8 b;
- zfile_fread(&b, 1, 1, z);
- wd->rom[i] = b;
+ wd->gdmac.s1_subtype = 0;
+ ac = gvp_scsi_ii_autoconfig;
+
+ rc = get_device_romconfig(&currprefs, devnum, romtype);
+ if (rc) {
+ ac = gvp_scsi_ii_autoconfig;
+ if (!series2) {
+ ac = gvp_scsi_i_autoconfig_1;
+ wd->gdmac.s1_rammask = GVP_SERIES_I_RAM_MASK_1;
+ wd->gdmac.s1_ramoffset = GVP_SERIES_I_RAM_OFFSET_1;
+ if (rc->subtype == 1) {
+ ac = gvp_scsi_i_autoconfig_2;
+ wd->gdmac.s1_rammask = GVP_SERIES_I_RAM_MASK_2;
+ wd->gdmac.s1_ramoffset = GVP_SERIES_I_RAM_OFFSET_2;
+ } else if (rc->subtype == 2) {
+ ac = gvp_scsi_i_autoconfig_3;
+ wd->gdmac.s1_rammask = GVP_SERIES_I_RAM_MASK_3;
+ wd->gdmac.s1_ramoffset = GVP_SERIES_I_RAM_OFFSET_3;
+ wd->board_mask = 131071;
+ }
+ wd->gdmac.s1_subtype = rc->subtype;
+ }
+ xfree(wd->gdmac.buffer);
+ wd->gdmac.buffer = xcalloc(uae_u8, 16384);
+ if (!rc->autoboot_disabled) {
+ if (is_device_rom(&currprefs, devnum, romtype)) {
+ struct zfile *z = read_device_rom(&currprefs, devnum, romtype, roms);
+ if (z) {
+ write_log(_T("GVP BOOT ROM '%s'\n"), zfile_getname(z));
+ int size = zfile_size(z);
+ if (series2) {
+ zfile_fread(wd->rom, 1, wd->rom_size, z);
+ } else {
+ int j = 0;
+ bool oddonly = false;
+ for (int i = 0; i < 16384; i++) {
+ uae_u8 b;
+ zfile_fread(&b, 1, 1, z);
+ wd->rom[j++] = b;
+ if (i == 0 && (b & 0xc0) != 0x80) {
+ // was not wordwide
+ oddonly = true;
+ wd->gdmac.use_version = true;
+ }
+ if (oddonly) {
+ wd->rom[j++] = 0xff;
+ }
+ }
}
+ zfile_fclose(z);
+ if (series2 && size > 16384) {
+ wd->rombankswitcher = 1;
+ }
+ } else {
+ isscsi = false;
+ if (!is_gvp_accelerator())
+ romwarning(roms);
}
- zfile_fclose(z);
- if (series2 && size > 16384) {
- wd->rombankswitcher = 1;
- }
- } else {
- isscsi = false;
- if (!is_gvp_accelerator())
- romwarning(roms);
}
+ } else {
+ isscsi = false;
}
- } else {
- isscsi = false;
}
- wd->gdmac.version = GVP_SERIESII;
- wd->gdmac.addr_mask = 0x00ffffff;
- if (currprefs.cpuboard_type == BOARD_GVP_A530) {
- wd->gdmac.version = isscsi ? GVP_A530_SCSI : GVP_A530;
- wd->gdmac.addr_mask = 0x01ffffff;
- } else if (currprefs.cpuboard_type == BOARD_GVP_GFORCE_030) {
- wd->gdmac.version = isscsi ? GVP_GFORCE_030_SCSI : GVP_GFORCE_030;
- wd->gdmac.addr_mask = 0x01ffffff;
+ if (series2) {
+ wd->gdmac.version = GVP_SERIESII;
+ wd->gdmac.addr_mask = 0x00ffffff;
+ if (ISCPUBOARD(BOARD_GVP, BOARD_GVP_SUB_A530)) {
+ wd->gdmac.version = isscsi ? GVP_A530_SCSI : GVP_A530;
+ wd->gdmac.addr_mask = 0x01ffffff;
+ } else if (ISCPUBOARD(BOARD_GVP, BOARD_GVP_SUB_GFORCE030)) {
+ wd->gdmac.version = isscsi ? GVP_GFORCE_030_SCSI : GVP_GFORCE_030;
+ wd->gdmac.addr_mask = 0x01ffffff;
+ }
+ } else {
+ wd->gdmac.version = 0x00;
}
for (int i = 0; i < 16; i++) {
- uae_u8 b = wd->gdmac.series2 ? gvp_scsi_ii_autoconfig[i] : gvp_scsi_i_autoconfig[i];
+ uae_u8 b = ac[i];
ew(wd, i * 4, b);
}
gvp_reset_device(wd);
}
addrbank *gvp_init_accelerator(int devnum)
{
- return gvp_init(1, true);
+ return gvp_init(-1, true);
}
uae_u8 *save_scsi_dmac (int wdtype, int *len, uae_u8 *dstptr)
int cpulevel, uncpulevel, plevel, sduse;
int i;
- char patbits[16];
char opcstr[256];
int bitpos[16];
int flagset[5], flaguse[5];
bitmask |= 1;
if (nextch == '1')
bitpattern |= 1;
- patbits[i] = nextch;
getnextch();
}
_T("Spectrum28/24_Z2"), _T("Spectrum28/24_Z3"),
_T("PicassoIV_Z2"), _T("PicassoIV_Z3"),
0 };
-static const TCHAR *cpuboards[] = {
- _T("none"),
- _T("Blizzard1230IV"),
- _T("Blizzard1260"),
- _T("Blizzard2060"),
- _T("CyberStormMK1"),
- _T("CyberStormMK2"),
- _T("CyberStormMK3"),
- _T("CyberStormPPC"),
- _T("BlizzardPPC"),
- _T("WarpEngineA4000"),
- _T("TekMagic"),
- _T("A2630"),
- _T("DKB12x0"),
- _T("FusionForty"),
- _T("A3001SI"),
- _T("A3001SII"),
- _T("Apollo"),
- _T("GVPA530"),
- _T("GVPGFORCE030"),
- NULL
-};
static const TCHAR *ppc_implementations[] = {
_T("auto"),
_T("dummy"),
_stprintf(buf, _T("%s%s_rom"), name, i ? _T("_ext") : _T(""));
cfgfile_dwrite_str (f, buf, br->roms[i].romident);
}
- if (br->roms[i].autoboot_disabled) {
+ if (br->roms[i].autoboot_disabled || ert->subtypes) {
+ TCHAR buf2[256], *p;
+ buf2[0] = 0;
+ p = buf2;
_stprintf(buf, _T("%s%s_rom_options"), name, i ? _T("_ext") : _T(""));
- cfgfile_dwrite_str (f, buf, _T("autoboot_disabled=true")); // ",another_option=xx"
+ if (ert->subtypes) {
+ const struct expansionsubromtype *srt = ert->subtypes;
+ int k = br->roms[i].subtype;
+ while (k && srt[1].name) {
+ srt++;
+ k--;
+ }
+ _stprintf(p, _T("subtype=%s"), srt->configname);
+ }
+ if (br->roms[i].autoboot_disabled) {
+ if (buf2[0])
+ _tcscat(buf2, _T(","));
+ _tcscat(buf2, _T("autoboot_disabled=true"));
+ }
+ cfgfile_dwrite_str (f, buf, buf2);
}
if (br->roms[i].board_ram_size) {
cfgfile_dwrite_ext (f, _T("gfx_filter_contrast"), ext, _T("%d"), gf->gfx_filter_contrast);
cfgfile_dwrite_ext (f, _T("gfx_filter_saturation"), ext, _T("%d"), gf->gfx_filter_saturation);
cfgfile_dwrite_ext (f, _T("gfx_filter_gamma"), ext, _T("%d"), gf->gfx_filter_gamma);
+ cfgfile_dwrite_ext (f, _T("gfx_filter_gamma_r"), ext, _T("%d"), gf->gfx_filter_gamma_ch[0]);
+ cfgfile_dwrite_ext (f, _T("gfx_filter_gamma_g"), ext, _T("%d"), gf->gfx_filter_gamma_ch[1]);
+ cfgfile_dwrite_ext (f, _T("gfx_filter_gamma_b"), ext, _T("%d"), gf->gfx_filter_gamma_ch[2]);
cfgfile_dwrite_ext (f, _T("gfx_filter_blur"), ext, _T("%d"), gf->gfx_filter_blur);
cfgfile_dwrite_ext (f, _T("gfx_filter_noise"), ext, _T("%d"), gf->gfx_filter_noise);
cfgfile_dwrite_bool (f, _T("gfx_filter_bilinear"), ext, gf->gfx_filter_bilinear != 0);
cfgfile_dwrite (f, _T("gfx_luminance"), _T("%d"), p->gfx_luminance);
cfgfile_dwrite (f, _T("gfx_contrast"), _T("%d"), p->gfx_contrast);
cfgfile_dwrite (f, _T("gfx_gamma"), _T("%d"), p->gfx_gamma);
+ cfgfile_dwrite (f, _T("gfx_gamma_r"), _T("%d"), p->gfx_gamma_ch[0]);
+ cfgfile_dwrite (f, _T("gfx_gamma_g"), _T("%d"), p->gfx_gamma_ch[1]);
+ cfgfile_dwrite (f, _T("gfx_gamma_b"), _T("%d"), p->gfx_gamma_ch[2]);
cfgfile_dwrite (f, _T("gfx_center_horizontal_position"), _T("%d"), p->gfx_xcenter_pos);
cfgfile_dwrite (f, _T("gfx_center_vertical_position"), _T("%d"), p->gfx_ycenter_pos);
cfgfile_dwrite (f, _T("z3mem2_size"), _T("%d"), p->z3fastmem2_size / 0x100000);
cfgfile_write (f, _T("z3mem_start"), _T("0x%x"), p->z3autoconfig_start);
cfgfile_write(f, _T("bogomem_size"), _T("%d"), p->bogomem_size / 0x40000);
- cfgfile_dwrite_str(f, _T("cpuboard_type"), cpuboards[p->cpuboard_type]);
+ if (p->cpuboard_type) {
+ const struct cpuboardtype *cbt = &cpuboards[p->cpuboard_type];
+ const struct cpuboardsubtype *cbst = &cbt->subtypes[p->cpuboard_subtype];
+ const struct cpuboardsettings *cbs = cbst->settings;
+ cfgfile_dwrite_str(f, _T("cpuboard_type"), cbst->configname);
+ if (cbs && p->cpuboard_settings) {
+ tmp[0] = 0;
+ for (int i = 0; cbs[i].name; i++) {
+ if (tmp[0])
+ _tcscat(tmp, _T(","));
+ _tcscat(tmp, cbs[i].configname);
+ }
+ cfgfile_dwrite_str(f, _T("cpuboard_settings"), tmp);
+ }
+ } else {
+ cfgfile_dwrite_str(f, _T("cpuboard_type"), _T("none"));
+ }
cfgfile_dwrite(f, _T("cpuboardmem1_size"), _T("%d"), p->cpuboardmem1_size / 0x100000);
cfgfile_dwrite(f, _T("cpuboardmem2_size"), _T("%d"), p->cpuboardmem2_size / 0x100000);
cfgfile_write(f, _T("gfxcard_size"), _T("%d"), p->rtgmem_size / 0x100000);
|| cfgfile_intval (option, value, _T("gfx_luminance"), &p->gfx_luminance, 1)
|| cfgfile_intval (option, value, _T("gfx_contrast"), &p->gfx_contrast, 1)
|| cfgfile_intval (option, value, _T("gfx_gamma"), &p->gfx_gamma, 1)
+ || cfgfile_intval (option, value, _T("gfx_gamma_r"), &p->gfx_gamma_ch[0], 1)
+ || cfgfile_intval (option, value, _T("gfx_gamma_g"), &p->gfx_gamma_ch[1], 1)
+ || cfgfile_intval (option, value, _T("gfx_gamma_b"), &p->gfx_gamma_ch[2], 1)
|| cfgfile_floatval (option, value, _T("rtg_vert_zoom_multf"), &p->rtg_vert_zoom_mult)
|| cfgfile_floatval (option, value, _T("rtg_horiz_zoom_multf"), &p->rtg_horiz_zoom_mult)
|| cfgfile_intval (option, value, _T("gfx_horizontal_tweak"), &p->gfx_extrawidth, 1)
|| cfgfile_intval (option, value, _T("gfx_filter_contrast"), ext, &gf->gfx_filter_contrast, 1)
|| cfgfile_intval (option, value, _T("gfx_filter_saturation"), ext, &gf->gfx_filter_saturation, 1)
|| cfgfile_intval (option, value, _T("gfx_filter_gamma"), ext, &gf->gfx_filter_gamma, 1)
+ || cfgfile_intval (option, value, _T("gfx_filter_gamma_r"), ext, &gf->gfx_filter_gamma_ch[0], 1)
+ || cfgfile_intval (option, value, _T("gfx_filter_gamma_g"), ext, &gf->gfx_filter_gamma_ch[1], 1)
+ || cfgfile_intval (option, value, _T("gfx_filter_gamma_b"), ext, &gf->gfx_filter_gamma_ch[2], 1)
|| cfgfile_intval (option, value, _T("gfx_filter_blur"), ext, &gf->gfx_filter_blur, 1)
|| cfgfile_intval (option, value, _T("gfx_filter_noise"), ext, &gf->gfx_filter_noise, 1)
|| cfgfile_intval (option, value, _T("gfx_filter_bilinear"), ext, &gf->gfx_filter_bilinear, 1)
return brc->roms[idx].romfile[0] != 0;
}
+static bool cfgfile_option_find(TCHAR *s, const TCHAR *option)
+{
+ TCHAR buf[MAX_DPATH];
+ _tcscpy(buf, s);
+ _tcscat(buf, _T(","));
+ TCHAR *p = buf;
+ for (;;) {
+ TCHAR *tmpp = _tcschr (p, ',');
+ if (tmpp == NULL)
+ return false;
+ *tmpp++ = 0;
+ if (!strcasecmp(p, option)) {
+ return true;
+ }
+ p = tmpp;
+ }
+}
+
+static int cfgfile_option_select(TCHAR *s, const TCHAR *option, const TCHAR *select)
+{
+ TCHAR buf[MAX_DPATH];
+ _tcscpy(buf, s);
+ _tcscat(buf, _T(","));
+ TCHAR *p = buf;
+ for (;;) {
+ TCHAR *tmpp = _tcschr (p, ',');
+ if (tmpp == NULL)
+ return -1;
+ *tmpp++ = 0;
+ TCHAR *tmpp2 = _tcschr(p, '=');
+ if (!tmpp2)
+ return -1;
+ *tmpp2++ = 0;
+ if (!strcasecmp(p, option)) {
+ int idx = 0;
+ while (select[0]) {
+ if (!strcasecmp(select, tmpp2))
+ return idx;
+ idx++;
+ select += _tcslen(select) + 1;
+ }
+ }
+ p = tmpp;
+ }
+}
+
static int cfgfile_option_bool(TCHAR *s, const TCHAR *option)
{
- _tcscat(s, _T(","));
+ TCHAR buf[MAX_DPATH];
+ _tcscpy(buf, s);
+ _tcscat(buf, _T(","));
+ TCHAR *p = buf;
for (;;) {
- TCHAR *tmpp = _tcschr (s, ',');
+ TCHAR *tmpp = _tcschr (p, ',');
if (tmpp == NULL)
return -1;
*tmpp++ = 0;
- TCHAR *tmpp2 = _tcschr(s, '=');
+ TCHAR *tmpp2 = _tcschr(p, '=');
if (tmpp2)
*tmpp2++ = 0;
- if (!strcasecmp(s, option)) {
+ if (!strcasecmp(p, option)) {
+ TCHAR *tmpp3 = _tcschr (tmpp2, ',');
+ if (tmpp3)
+ *tmpp3 = 0;
if (tmpp2 && !strcasecmp(tmpp2, _T("true")))
return 1;
if (tmpp2 && !strcasecmp(tmpp2, _T("false")))
return 0;
return 1;
}
+ p = tmpp;
}
}
_stprintf(buf, _T("%s_rom_options"), ert->name);
if (cfgfile_string (option, value, buf, buf2, sizeof buf2 / sizeof (TCHAR))) {
+ brc = get_device_rom_new(p, ert->romtype, &idx);
if (cfgfile_option_bool(buf2, _T("autoboot_disabled")) == 1) {
- brc = get_device_rom_new(p, ert->romtype, &idx);
brc->roms[idx].autoboot_disabled = true;
}
+ if (ert->subtypes) {
+ const struct expansionsubromtype *srt = ert->subtypes;
+ TCHAR tmp[MAX_DPATH], *p;
+ p = tmp;
+ *p = 0;
+ while (srt->name) {
+ _tcscpy(p, srt->configname);
+ p += _tcslen(p) + 1;
+ p[0] = 0;
+ srt++;
+ }
+ int v = cfgfile_option_select(buf2, _T("subtype"), tmp);
+ if (v >= 0)
+ brc->roms[idx].subtype = v;
+ }
return true;
}
|| cfgfile_intval (option, value, _T("bogomem_size"), &p->bogomem_size, 0x40000)
|| cfgfile_intval (option, value, _T("gfxcard_size"), &p->rtgmem_size, 0x100000)
|| cfgfile_strval(option, value, _T("gfxcard_type"), &p->rtgmem_type, rtgtype, 0)
- || cfgfile_strval(option, value, _T("cpuboard_type"), &p->cpuboard_type, cpuboards, 0)
|| cfgfile_intval(option, value, _T("rtg_modes"), &p->picasso96_modeflags, 1)
|| cfgfile_intval (option, value, _T("floppy_speed"), &p->floppy_speed, 1)
|| cfgfile_intval (option, value, _T("cd_speed"), &p->cd_speed, 1)
|| cfgfile_string (option, value, _T("ghostscript_parameters"), p->ghostscript_parameters, sizeof p->ghostscript_parameters / sizeof (TCHAR)))
return 1;
+ if (cfgfile_string(option, value, _T("cpuboard_type"), tmpbuf, sizeof tmpbuf / sizeof(TCHAR))) {
+ p->cpuboard_type = 0;
+ p->cpuboard_subtype = 0;
+ for (i = 0; cpuboards[i].name && !p->cpuboard_type; i++) {
+ const struct cpuboardtype *cbt = &cpuboards[i];
+ if (cbt->subtypes) {
+ for (int j = 0; cbt->subtypes[j].name; j++) {
+ if (!_tcsicmp(cbt->subtypes[j].configname, tmpbuf)) {
+ p->cpuboard_type = i;
+ p->cpuboard_subtype = j;
+ }
+ }
+ }
+ }
+ return 1;
+ }
+ if (cfgfile_string(option, value, _T("cpuboard_settings"), tmpbuf, sizeof tmpbuf / sizeof(TCHAR))) {
+ p->cpuboard_settings = 0;
+ const struct cpuboardsubtype *cbst = &cpuboards[p->cpuboard_type].subtypes[p->cpuboard_subtype];
+ if (cbst->settings) {
+ const struct cpuboardsettings *cbs = cbst->settings;
+ for(i = 0; cbs[i].name; i++) {
+ if (cfgfile_option_find(tmpbuf, cbs[i].configname)) {
+ p->cpuboard_settings |= 1 << i;
+ break;
+ }
+ }
+ }
+ return 1;
+ }
+
if (cfgfile_strval (option, value, _T("chipset_compatible"), &p->cs_compatible, cscompa, 0)) {
built_in_chipset_prefs (p);
return 1;
_tcscpy (p->romextfile, _T(""));
_tcscpy (p->romextfile2, _T(""));
+ set_device_rom(p, NULL, ROMTYPE_CPUBOARD);
+ set_device_rom(p, NULL, ROMTYPE_CPUBOARDEXT);
p->prtname[0] = 0;
p->sername[0] = 0;
p->cpu_model = 68060;
p->fpu_model = 68060;
p->ppc_mode = 1;
- p->cpuboard_type = BOARD_CSPPC;
+ p->cpuboard_type = BOARD_CYBERSTORM;
+ p->cpuboard_subtype = BOARD_CYBERSTORM_SUB_PPC;
p->cpuboardmem1_size = 128 * 1024 * 1024;
+ int roms_ppc[] = { 98, -1 };
+ configure_rom(p, roms_ppc, romcheck);
break;
}
p->chipset_mask = CSMASK_AGA | CSMASK_ECS_AGNUS | CSMASK_ECS_DENISE;
static int bip_a1200 (struct uae_prefs *p, int config, int compa, int romcheck)
{
int roms[4];
+ int roms_bliz[2];
buildin_default_prefs_68020 (p);
roms[0] = 11;
roms[1] = 15;
roms[2] = 31;
roms[3] = -1;
+ roms_bliz[0] = -1;
+ roms_bliz[1] = -1;
p->cs_rtc = 0;
p->cs_compatible = CP_A1200;
built_in_chipset_prefs (p);
p->cs_rtc = 1;
break;
case 2:
- p->cpuboard_type = BOARD_BLIZZARD_1230_IV;
+ p->cpuboard_type = BOARD_BLIZZARD;
+ p->cpuboard_subtype = BOARD_BLIZZARD_SUB_1230IV;
p->cpuboardmem1_size = 32 * 1024 * 1024;
p->cpu_model = 68030;
p->cs_rtc = 1;
+ roms_bliz[0] = 90;
+ configure_rom(p, roms_bliz, romcheck);
break;
case 3:
- p->cpuboard_type = BOARD_BLIZZARD_1260;
+ p->cpuboard_type = BOARD_BLIZZARD;
+ p->cpuboard_subtype = BOARD_BLIZZARD_SUB_1260;
p->cpuboardmem1_size = 32 * 1024 * 1024;
p->cpu_model = 68040;
p->fpu_model = 68040;
p->cs_rtc = 1;
+ roms_bliz[0] = 90;
+ configure_rom(p, roms_bliz, romcheck);
break;
case 4:
- p->cpuboard_type = BOARD_BLIZZARD_1260;
+ p->cpuboard_type = BOARD_BLIZZARD;
+ p->cpuboard_subtype = BOARD_BLIZZARD_SUB_1260;
p->cpuboardmem1_size = 32 * 1024 * 1024;
p->cpu_model = 68060;
p->fpu_model = 68060;
p->cs_rtc = 1;
+ roms_bliz[0] = 90;
+ configure_rom(p, roms_bliz, romcheck);
break;
case 5:
- p->cpuboard_type = BOARD_BLIZZARDPPC;
+ p->cpuboard_type = BOARD_BLIZZARD;
+ p->cpuboard_subtype = BOARD_BLIZZARD_SUB_PPC;
p->cpuboardmem1_size = 256 * 1024 * 1024;
p->cpu_model = 68060;
p->fpu_model = 68060;
roms[0] = 15;
roms[1] = 11;
roms[2] = -1;
+ roms_bliz[0] = 100;
+ configure_rom(p, roms_bliz, romcheck);
break;
}
set_68020_compa (p, compa, 0);
- set_device_rom(p, NULL, ROMTYPE_CPUBOARD);
- set_device_rom(p, NULL, ROMTYPE_CPUBOARDEXT);
return configure_rom (p, roms, romcheck);
}
switch(p->cpuboard_type)
{
- case BOARD_BLIZZARD_1230_IV:
- roms[0] = 89;
- break;
- case BOARD_BLIZZARD_1260:
- roms[0] = 90;
- break;
- case BOARD_BLIZZARD_2060:
- roms[0] = 92;
- break;
- case BOARD_WARPENGINE_A4000:
- roms[0] = 93;
- break;
- case BOARD_CSMK1:
- roms[0] = p->cpu_model == 68040 ? 95 : 101;
- break;
- case BOARD_CSMK2:
- roms[0] = 96;
- break;
- case BOARD_CSMK3:
- roms[0] = 97;
+ case BOARD_MACROSYSTEM:
+ switch(p->cpuboard_subtype)
+ {
+ case BOARD_MACROSYSTEM_SUB_WARPENGINE_A4000:
+ roms[0] = 93;
+ break;
+ }
break;
- case BOARD_CSPPC:
- roms[0] = 98;
+ case BOARD_BLIZZARD:
+ switch(p->cpuboard_subtype)
+ {
+ case BOARD_BLIZZARD_SUB_1230IV:
+ roms[0] = 89;
+ break;
+ case BOARD_BLIZZARD_SUB_1260:
+ roms[0] = 90;
+ break;
+ case BOARD_BLIZZARD_SUB_2060:
+ roms[0] = 92;
+ break;
+ case BOARD_BLIZZARD_SUB_PPC:
+ roms[0] = p->cpu_model == 68040 ? 99 : 100;
+ break;
+ }
break;
- case BOARD_BLIZZARDPPC:
- roms[0] = p->cpu_model == 68040 ? 99 : 100;
+ case BOARD_CYBERSTORM:
+ switch(p->cpuboard_subtype)
+ {
+ case BOARD_CYBERSTORM_SUB_MK1:
+ roms[0] = p->cpu_model == 68040 ? 95 : 101;
+ break;
+ case BOARD_CYBERSTORM_SUB_MK2:
+ roms[0] = 96;
+ break;
+ case BOARD_CYBERSTORM_SUB_MK3:
+ roms[0] = 97;
+ break;
+ case BOARD_CYBERSTORM_SUB_PPC:
+ roms[0] = 98;
+ break;
+ }
break;
}
if (!configure_rom(p, roms, 0))
#include "uae/ppc.h"
#include "idecontrollers.h"
#include "scsi.h"
+#include "cpummu030.h"
#define CPUBOARD_IO_LOG 0
#define CPUBOARD_IRQ_LOG 0
return m68kint;
}
+static bool mapromconfigured(void)
+{
+ if (currprefs.maprom)
+ return true;
+ if (currprefs.cpuboard_settings)
+ return true;
+ return false;
+}
+
static bool is_blizzard(void)
{
- return currprefs.cpuboard_type == BOARD_BLIZZARD_1230_IV || currprefs.cpuboard_type == BOARD_BLIZZARD_1260;
+ return ISCPUBOARD(BOARD_BLIZZARD, BOARD_BLIZZARD_SUB_1230IV) || ISCPUBOARD(BOARD_BLIZZARD, BOARD_BLIZZARD_SUB_1260);
}
static bool is_blizzard2060(void)
{
- return currprefs.cpuboard_type == BOARD_BLIZZARD_2060;
+ return ISCPUBOARD(BOARD_BLIZZARD, BOARD_BLIZZARD_SUB_2060);
}
static bool is_csmk1(void)
{
- return currprefs.cpuboard_type == BOARD_CSMK1;
+ return ISCPUBOARD(BOARD_CYBERSTORM, BOARD_CYBERSTORM_SUB_MK1);
}
static bool is_csmk2(void)
{
- return currprefs.cpuboard_type == BOARD_CSMK2;
+ return ISCPUBOARD(BOARD_CYBERSTORM, BOARD_CYBERSTORM_SUB_MK2);
}
static bool is_csmk3(void)
{
- return currprefs.cpuboard_type == BOARD_CSMK3 || currprefs.cpuboard_type == BOARD_CSPPC;
+ return ISCPUBOARD(BOARD_CYBERSTORM, BOARD_CYBERSTORM_SUB_MK3) || ISCPUBOARD(BOARD_CYBERSTORM, BOARD_CYBERSTORM_SUB_PPC);
}
static bool is_blizzardppc(void)
{
- return currprefs.cpuboard_type == BOARD_BLIZZARDPPC;
+ return ISCPUBOARD(BOARD_BLIZZARD, BOARD_BLIZZARD_SUB_PPC);
}
static bool is_ppc(void)
{
- return currprefs.cpuboard_type == BOARD_BLIZZARDPPC || currprefs.cpuboard_type == BOARD_CSPPC;
+ return ISCPUBOARD(BOARD_BLIZZARD, BOARD_BLIZZARD_SUB_PPC) || ISCPUBOARD(BOARD_CYBERSTORM, BOARD_CYBERSTORM_SUB_PPC);
}
static bool is_tekmagic(void)
{
- return currprefs.cpuboard_type == BOARD_TEKMAGIC;
+ return ISCPUBOARD(BOARD_GVP, BOARD_GVP_SUB_TEKMAGIC);
}
static bool is_a2630(void)
{
- return currprefs.cpuboard_type == BOARD_A2630;
+ return ISCPUBOARD(BOARD_COMMODORE, BOARD_COMMODORE_SUB_A26x0);
}
static bool is_dkb(void)
{
- return currprefs.cpuboard_type == BOARD_DKB1200;
+ return ISCPUBOARD(BOARD_DKB, BOARD_DKB_SUB_12x0);
}
static bool is_fusionforty(void)
{
- return currprefs.cpuboard_type == BOARD_FUSIONFORTY;
+ return ISCPUBOARD(BOARD_RCS, BOARD_RCS_SUB_FUSIONFORTY);
}
static bool is_apollo(void)
{
- return currprefs.cpuboard_type == BOARD_APOLLO;
+ return ISCPUBOARD(BOARD_ACT, BOARD_ACT_SUB_APOLLO);
}
DECLARE_MEMORY_FUNCTIONS(blizzardio);
v = cpuboard_ncr710_io_bget(addr);
} else if (is_blizzard2060() && addr >= BLIZZARD_2060_SCSI_OFFSET) {
v = cpuboard_ncr9x_scsi_get(addr);
- } else if (currprefs.cpuboard_type == BOARD_BLIZZARD_1230_IV || currprefs.cpuboard_type == BOARD_BLIZZARD_1260) {
+ } else if (is_blizzard()) {
if (addr & BLIZZARD_SCSI_KIT_SCSI_OFFSET)
v = cpuboard_ncr9x_scsi_get(addr);
else
cpuboard_ncr710_io_bput(addr, b);
} else if (is_blizzard2060() && addr >= BLIZZARD_2060_SCSI_OFFSET) {
cpuboard_ncr9x_scsi_put(addr, b);
- } else if ((currprefs.cpuboard_type == BOARD_BLIZZARD_1230_IV || currprefs.cpuboard_type == BOARD_BLIZZARD_1260) && addr >= BLIZZARD_SCSI_KIT_SCSI_OFFSET) {
+ } else if ((is_blizzard()) && addr >= BLIZZARD_SCSI_KIT_SCSI_OFFSET) {
cpuboard_ncr9x_scsi_put(addr, b);
} else if (is_csmk1()) {
if (addr >= CYBERSTORM_MK1_SCSI_OFFSET) {
#ifdef JIT
special_mem |= S_WRITE;
#endif
- if (is_a2630()) {
- addr &= 65535;
- if (addr == 0x0040) {
- write_log(_T("A2630 write %04x PC=%08x\n"), b, M68K_GETPC);
- a2630_io = b;
- // bit 0: unmap 0x000000
- // bit 1: unmap 0xf80000
- if (b & 2) {
- map_banks(&kickmem_bank, 0xf80000 >> 16, 131072 >> 16, 0);
- write_log(_T("A2630 boot rom unmapped\n"));
- }
- // bit 2: autoconfig region enable
- if (b & 4) {
- write_log(_T("A2630 Autoconfig enabled\n"));
- expamem_next(NULL, NULL);
- }
- // bit 3: unknown
- // bit 4: 68000 mode
- if (b & 0x10) {
- write_log(_T("A2630 68000 mode!\n"));
- cpu_halt(4);
- }
- }
- }
}
static void REGPARAM2 blizzarde8_bput(uaecptr addr, uae_u32 b)
{
special_mem |= S_READ;
#endif
write_log(_T("CS IO LGET %08x PC=%08x\n"), addr, M68K_GETPC);
- if (is_blizzard2060() && currprefs.maprom) {
+ if (is_blizzard2060() && mapromconfigured()) {
if (addr & 0x10000000) {
maprom_state = 0;
} else {
}
} else if (is_blizzard()) {
if ((addr & 65535) == (BLIZZARD_MAPROM_ENABLE & 65535)) {
- if (v != 0x42 || maprom_state || !currprefs.maprom)
+ if (v != 0x42 || maprom_state || !mapromconfigured())
return;
maprom_state = 1;
write_log(_T("Blizzard: MAPROM enabled\n"));
cyberstormmk1_copymaprom();
}
}
- if (is_blizzard2060() && currprefs.maprom) {
+ if (is_blizzard2060() && mapromconfigured()) {
if (addr & 0x10000000) {
maprom_state = 0;
} else {
map_banks_nojitdirect(&blizzardram_nojit_bank, (BLIZZARD_RAM_BASE_48 + i) >> 16, cpuboard_size >> 16, 0);
map_banks_nojitdirect(&blizzardram_nojit_bank, (BLIZZARD_RAM_BASE_68 + i) >> 16, cpuboard_size >> 16, 0);
}
- if (currprefs.maprom && !is_blizzardppc()) {
+ if (mapromconfigured() && !is_blizzardppc()) {
for (int i = 0; i < 0x08000000; i += cpuboard_size) {
map_banks_nojitdirect(&blizzardmaprom_bank, (BLIZZARD_RAM_BASE_48 + i + cpuboard_size - 524288) >> 16, 524288 >> 16, 0);
map_banks_nojitdirect(&blizzardmaprom_bank, (BLIZZARD_RAM_BASE_68 + i + cpuboard_size - 524288) >> 16, 524288 >> 16, 0);
if (is_blizzard2060()) {
map_banks(&blizzardf0_bank, 0xf00000 >> 16, 65536 >> 16, 0);
map_banks(&blizzardio_bank, 0x80000000 >> 16, 0x10000000 >> 16, 0);
- if (currprefs.maprom)
+ if (mapromconfigured())
map_banks_nojitdirect(&blizzardmaprom_bank, (a3000hmem_bank.start + a3000hmem_bank.allocated - 524288) >> 16, 524288 >> 16, 0);
}
if (is_tekmagic()) {
configured = false;
delayed_rom_protect = 0;
currprefs.cpuboardmem1_size = changed_prefs.cpuboardmem1_size;
- if (hardreset || (!currprefs.maprom && (is_blizzard() || is_blizzard2060())))
+ if (hardreset || (!mapromconfigured() && (is_blizzard() || is_blizzard2060())))
maprom_state = 0;
if (is_csmk3() || is_blizzardppc()) {
if (hardreset)
bool is_ppc_cpu(struct uae_prefs *p)
{
- return p->cpuboard_type == BOARD_CSPPC || p->cpuboard_type == BOARD_BLIZZARDPPC;
+ return is_ppc();
}
bool cpuboard_maprom(void)
int cpuboard_memorytype(struct uae_prefs *p)
{
- switch (p->cpuboard_type)
- {
- case 0:
- return 0;
- case BOARD_BLIZZARD_2060:
- case BOARD_CSMK1:
- case BOARD_CSMK2:
- case BOARD_CSMK3:
- case BOARD_CSPPC:
- case BOARD_WARPENGINE_A4000:
- case BOARD_TEKMAGIC:
- case BOARD_FUSIONFORTY:
- case BOARD_DKB1200: // ??
- case BOARD_APOLLO:
- return BOARD_MEMORY_HIGHMEM;
- case BOARD_GVP_GFORCE_030:
- case BOARD_A2630:
- return BOARD_MEMORY_25BITMEM;
- case BOARD_GVP_A530:
- return BOARD_MEMORY_Z2;
- case BOARD_BLIZZARD_1230_IV:
- case BOARD_BLIZZARD_1260:
- return BOARD_MEMORY_BLIZZARD_12xx;
- case BOARD_BLIZZARDPPC:
- return BOARD_MEMORY_BLIZZARD_PPC;
- default:
- write_log(_T("Missing board type %d!\n"), p->cpuboard_type);
- return BOARD_MEMORY_HIGHMEM;
- }
+ if (cpuboards[p->cpuboard_type].subtypes)
+ return cpuboards[p->cpuboard_type].subtypes[p->cpuboard_subtype].memorytype;
+ return 0;
}
int cpuboard_maxmemory(struct uae_prefs *p)
{
- if (p->cpuboard_type == BOARD_BLIZZARDPPC)
- return 256 * 1024 * 1024;
- int type = cpuboard_memorytype(p);
- switch (type)
- {
- case BOARD_MEMORY_BLIZZARD_12xx:
- case BOARD_MEMORY_BLIZZARD_PPC:
- return 256 * 1024 * 1024;
- case BOARD_MEMORY_HIGHMEM:
- return 128 * 1024 * 1024;
- case BOARD_MEMORY_Z2:
- return 8 * 1024 * 1024;
- case BOARD_MEMORY_25BITMEM:
- return 128 * 1024 * 1024;
- default:
- return 0;
- }
+ if (cpuboards[p->cpuboard_type].subtypes)
+ return cpuboards[p->cpuboard_type].subtypes[p->cpuboard_subtype].maxmemory;
+ return 0;
}
-void cpuboard_io_special_write(uaecptr addr, uae_u32 val)
+bool cpuboard_io_special(int addr, uae_u32 *val, int size, bool write)
{
- blizzarde8_wput(addr, val);
+ addr &= 65535;
+ if (write) {
+ uae_u16 w = *val;
+ if (is_a2630()) {
+ if ((addr == 0x0040 && size == 2) || (addr == 0x0041 && size == 1)) {
+ write_log(_T("A2630 write %04x PC=%08x\n"), w, M68K_GETPC);
+ a2630_io = w;
+ // bit 0: unmap 0x000000
+ // bit 1: unmap 0xf80000
+ if (w & 2) {
+ if (currprefs.mmu_model == 68030) {
+ // HACK!
+ mmu030_fake_prefetch = 0x4ed0;
+ }
+ map_banks(&kickmem_bank, 0xF8, 8, 0);
+ write_log(_T("A2630 boot rom unmapped\n"));
+ }
+ // bit 2: autoconfig region enable
+ if (w & 4) {
+ write_log(_T("A2630 Autoconfig enabled\n"));
+ expamem_next(NULL, NULL);
+ }
+ // bit 3: unknown
+ // bit 4: 68000 mode
+ if (w & 0x10) {
+ write_log(_T("A2630 68000 mode!\n"));
+ cpu_halt(4);
+ }
+ return true;
+ }
+ }
+ return false;
+ } else {
+ if (is_a2630()) {
+ if (addr == 0x0c) {
+ (*val) |= 0x80;
+ if (currprefs.cpuboard_settings & 1)
+ (*val) &= ~0x80;
+ return true;
+ }
+ }
+ }
+ return false;
}
static void fixserial(uae_u8 *rom, int size)
return;
#endif
- if (currprefs.cpuboard_type == BOARD_BLIZZARDPPC) {
+ if (ISCPUBOARD(BOARD_BLIZZARD, BOARD_BLIZZARD_SUB_PPC)) {
value1 = 'I';
value2 = 'D';
if (currprefs.cpu_model == 68060)
value3 = 'A';
seroffset = 19;
sprintf(serial, "%04X", serialnum);
- } else if (currprefs.cpuboard_type == BOARD_CSPPC) {
+ } else if (ISCPUBOARD(BOARD_CYBERSTORM, BOARD_CYBERSTORM_SUB_PPC)) {
value1 = 'D';
value2 = 'B';
sprintf(serial, "%05X", serialnum);
value3 = 0;
seroffset = 18;
- } else if (currprefs.cpuboard_type == BOARD_CSMK3) {
+ } else if (ISCPUBOARD(BOARD_CYBERSTORM, BOARD_CYBERSTORM_SUB_MK3)) {
value1 = 'F';
sprintf(serial, "%05X", serialnum);
value2 = value3 = 0;
TCHAR path[MAX_DPATH];
bool rw = true;
- if (!name[0])
+ if (name == NULL || !name[0])
return NULL;
f = zfile_fopen(name, _T("rb"), ZFD_NORMAL);
if (f) {
cpuboard_non_byte_ea = false;
switch (currprefs.cpuboard_type)
{
- case BOARD_A2630:
- roms[0] = 105;
- roms[1] = 106;
- break;
- case BOARD_GVP_A530:
- case BOARD_GVP_GFORCE_030:
- return &expamem_null;
- case BOARD_APOLLO:
- roms[0] = 119;
- break;
- case BOARD_A3001_I:
- case BOARD_A3001_II:
- return &expamem_null;
- case BOARD_BLIZZARD_1230_IV:
- roms[0] = 89;
- roms2[0] = 94;
- break;
- case BOARD_BLIZZARD_1260:
- roms[0] = 90;
- roms2[0] = 94;
- break;
- case BOARD_BLIZZARD_2060:
- roms[0] = 92;
+ case BOARD_COMMODORE:
+ switch(currprefs.cpuboard_subtype)
+ {
+ case BOARD_COMMODORE_SUB_A26x0:
+ roms[0] = 105;
+ roms[1] = 106;
+ break;
+ }
break;
- case BOARD_WARPENGINE_A4000:
- return &expamem_null;
- case BOARD_DKB1200:
- return &expamem_null;
- case BOARD_TEKMAGIC:
- roms[0] = 104;
+
+ case BOARD_ACT:
+ switch(currprefs.cpuboard_subtype)
+ {
+ case BOARD_ACT_SUB_APOLLO:
+ roms[0] = 119;
+ break;
+ }
break;
- case BOARD_CSMK1:
- roms[0] = currprefs.cpu_model == 68040 ? 95 : 101;
- isflashrom = true;
+
+ case BOARD_MACROSYSTEM:
+ switch(currprefs.cpuboard_subtype)
+ {
+ case BOARD_MACROSYSTEM_SUB_WARPENGINE_A4000:
+ return &expamem_null;
+ }
break;
- case BOARD_CSMK2:
- roms[0] = 96;
- isflashrom = true;
+
+ case BOARD_DKB:
+ switch(currprefs.cpuboard_subtype)
+ {
+ case BOARD_DKB_SUB_12x0:
+ return &expamem_null;
+ }
break;
- case BOARD_CSMK3:
- roms[0] = 97;
- isflashrom = true;
+
+ case BOARD_RCS:
+ switch(currprefs.cpuboard_subtype)
+ {
+ case BOARD_RCS_SUB_FUSIONFORTY:
+ roms[0] = 113;
+ break;
+ }
break;
- case BOARD_CSPPC:
- roms[0] = 98;
- isflashrom = true;
+
+ case BOARD_GVP:
+ switch(currprefs.cpuboard_subtype)
+ {
+ case BOARD_GVP_SUB_A530:
+ case BOARD_GVP_SUB_GFORCE030:
+ return &expamem_null;
+ case BOARD_GVP_SUB_A3001SI:
+ case BOARD_GVP_SUB_A3001SII:
+ return &expamem_null;
+ case BOARD_GVP_SUB_TEKMAGIC:
+ roms[0] = 104;
+ break;
+ }
break;
- case BOARD_BLIZZARDPPC:
- roms[0] = currprefs.cpu_model == 68040 ? 99 : 100;
- isflashrom = true;
+
+ case BOARD_CYBERSTORM:
+ switch(currprefs.cpuboard_subtype)
+ {
+ case BOARD_CYBERSTORM_SUB_MK1:
+ roms[0] = currprefs.cpu_model == 68040 ? 95 : 101;
+ isflashrom = true;
+ break;
+ case BOARD_CYBERSTORM_SUB_MK2:
+ roms[0] = 96;
+ isflashrom = true;
+ break;
+ case BOARD_CYBERSTORM_SUB_MK3:
+ roms[0] = 97;
+ isflashrom = true;
+ break;
+ case BOARD_CYBERSTORM_SUB_PPC:
+ roms[0] = 98;
+ isflashrom = true;
+ break;
+ }
break;
- case BOARD_FUSIONFORTY:
- roms[0] = 113;
+
+ case BOARD_BLIZZARD:
+ switch(currprefs.cpuboard_subtype)
+ {
+ case BOARD_BLIZZARD_SUB_1230IV:
+ roms[0] = 89;
+ roms2[0] = 94;
+ break;
+ case BOARD_BLIZZARD_SUB_1260:
+ roms[0] = 90;
+ roms2[0] = 94;
+ break;
+ case BOARD_BLIZZARD_SUB_2060:
+ roms[0] = 92;
+ break;
+ case BOARD_BLIZZARD_SUB_PPC:
+ roms[0] = currprefs.cpu_model == 68040 ? 99 : 100;
+ isflashrom = true;
+ break;
+ }
break;
- default:
- return &expamem_null;
+
+ default:
+ return &expamem_null;
}
struct romlist *rl = NULL;
// "enable MMU" unmaps memory under us.
TRY (prb) {
mmu030_fake_prefetch = x_prefetch(0);
+ // A26x0 ROM code switches off rom
+ // NOP
+ // JMP (a0)
+ if (mmu030_fake_prefetch == 0x4e71)
+ mmu030_fake_prefetch = x_prefetch(2);
} CATCH (prb) {
// didn't work, oh well..
mmu030_fake_prefetch = -1;
int doublescan;
bool programmedmode;
int syncbase;
-static int fmode;
+static int fmode_saved, fmode;
uae_u16 beamcon0, new_beamcon0;
static bool varsync_changed;
uae_u16 vtotal = MAXVPOS_PAL, htotal = MAXHPOS_PAL;
alloc_cycle (hpos, CYCLE_BLITTER);
}
+static void set_chipset_mode(void)
+{
+ if (currprefs.chipset_mask & CSMASK_AGA) {
+ fmode = fmode_saved;
+ } else {
+ fmode = 0;
+ }
+ sprite_width = GET_SPRITEWIDTH (fmode);
+}
+
static void update_mirrors (void)
{
aga_mode = (currprefs.chipset_mask & CSMASK_AGA) != 0;
sprite_sprctlmask = 0x01 | 0x10;
else
sprite_sprctlmask = 0x01;
+ set_chipset_mode();
}
STATIC_INLINE uae_u8 *pfield_xlateptr (uaecptr plpt, int bytecount)
if (fmode == v)
return;
SET_LINE_CYCLEBASED;
- fmode = v;
- sprite_width = GET_SPRITEWIDTH (fmode);
+ fmode_saved = v;
+ set_chipset_mode();
bpldmainitdelay (hpos);
}
return s;
}
-static void print_task_info (uaecptr node)
+static void print_task_info (uaecptr node, bool nonactive)
{
TCHAR *s;
int process = get_byte_debug (node + 8) == 13 ? 1 : 0;
console_out_f (_T("%08X: "), node);
s = au ((char*)get_real_address (get_long_debug (node + 10)));
- console_out_f (process ? _T(" PROCESS '%s'\n") : _T(" TASK '%s'\n"), s);
+ console_out_f (process ? _T("PROCESS '%s'\n") : _T("TASK '%s'\n"), s);
xfree (s);
if (process) {
uaecptr cli = BPTR2APTR (get_long_debug (node + 172));
console_out (_T("\n"));
}
}
+ if (nonactive) {
+ uae_u32 sigwait = get_long_debug(node + 22);
+ if (sigwait)
+ console_out_f(_T(" Waiting signals: %08x\n"), sigwait);
+ uae_u32 sp = get_long_debug(node + 54) + 70;
+ uae_u32 pc = get_long_debug(sp);
+ console_out_f(_T(" SP: %08x PC: %08x\n"), sp, pc);
+ }
}
static void show_exec_tasks (void)
{
uaecptr execbase = get_long_debug (4);
- uaecptr taskready = get_long_debug (execbase + 406);
- uaecptr taskwait = get_long_debug (execbase + 420);
- uaecptr node, end;
+ uaecptr taskready = execbase + 406;
+ uaecptr taskwait = execbase + 420;
+ uaecptr node;
console_out_f (_T("Execbase at 0x%08X\n"), execbase);
console_out (_T("Current:\n"));
node = get_long_debug (execbase + 276);
- print_task_info (node);
+ print_task_info (node, false);
console_out_f (_T("Ready:\n"));
node = get_long_debug (taskready);
- end = get_long_debug (taskready + 4);
- while (node) {
- print_task_info (node);
+ while (node && get_long_debug(node)) {
+ print_task_info (node, true);
node = get_long_debug (node);
}
console_out (_T("Waiting:\n"));
node = get_long_debug (taskwait);
- end = get_long_debug (taskwait + 4);
- while (node) {
- print_task_info (node);
+ while (node && get_long_debug(node)) {
+ print_task_info (node, true);
node = get_long_debug (node);
}
}
return;
}
+ bool full = false;
switch (c)
{
case 'r': // resources
break;
case 'd': // devices
list = execbase + 350;
+ full = true;
break;
case 'l': // libraries
list = execbase + 378;
+ full = true;
break;
case 'p': // ports
list = execbase + 392;
while (get_long_debug (node)) {
TCHAR *name = au ((char*)get_real_address (get_long_debug (node + 10)));
uae_u16 v = get_word_debug (node + 8);
- console_out_f (_T("%08x %d %d %s\n"), node, (int)((v >> 8) & 0xff), (uae_s8)(v & 0xff), name);
+ console_out_f (_T("%08x %d %d"), node, (int)((v >> 8) & 0xff), (uae_s8)(v & 0xff));
+ if (full) {
+ uae_u16 ver = get_word_debug(node + 20);
+ uae_u16 rev = get_word_debug(node + 22);
+ uae_u32 op = get_word_debug(node + 32);
+ console_out_f(_T(" %d.%d %d"), ver, rev, op);
+ }
+ console_out_f(_T(" %s"), name);
xfree (name);
+ if (full) {
+ uaecptr idstring = get_long_debug(node + 24);
+ if (idstring) {
+ name = au((char*)get_real_address(idstring));
+ console_out_f(_T(" (%s)"), name);
+ xfree(name);
+ }
+ }
+ console_out_f(_T("\n"));
node = get_long_debug (node);
}
}
next_char(c);
if (more_params(c)) {
int count = readint(c);
- if (nc == 'L') {
+ if (nc == 'S') {
if (more_params(c)) {
int hp = readint(c);
if (count >= vpos) {
inptr++;
if (process_breakpoint (&inptr))
return true;
- } else if (inptr[0] == 'c' || inptr[0] == 'l') {
+ } else if (inptr[0] == 'c' || inptr[0] == 's') {
if (cycle_breakpoint(&inptr))
return true;
} else {
return expamem_bank_current->bget(addr) << 8;
}
uae_u32 v = (expamem_bget (addr) << 8) | expamem_bget (addr + 1);
+ if (cpuboards[currprefs.cpuboard_type].subtypes[currprefs.cpuboard_subtype].e8) {
+ uae_u32 val = v;
+ cpuboards[currprefs.cpuboard_type].subtypes[currprefs.cpuboard_subtype].e8(addr, &val, 2, false);
+ v = val;
+ }
write_log (_T("warning: READ.W from address $%08x=%04x PC=%x\n"), addr, v & 0xffff, M68K_GETPC);
return v;
}
return expamem_bank_current->bget(addr);
addr &= 0xFFFF;
b = expamem[addr];
+ if (cpuboards[currprefs.cpuboard_type].subtypes[currprefs.cpuboard_subtype].e8) {
+ uae_u32 val = b;
+ cpuboards[currprefs.cpuboard_type].subtypes[currprefs.cpuboard_subtype].e8(addr, &val, 1, false);
+ b = val;
+ }
#if EXP_DEBUG
write_log (_T("expamem_bget %x %x\n"), addr, b);
#endif
special_mem |= S_WRITE;
#endif
value &= 0xffff;
- if ((addr & 0xff) == 0x40) {
- if (currprefs.cpuboard_type == BOARD_A2630) {
- /* ARGH! Word write to E80040 always goes to A2630 special IO address! */
- cpuboard_io_special_write(addr, value);
+ if (cpuboards[currprefs.cpuboard_type].subtypes[currprefs.cpuboard_subtype].e8) {
+ if (cpuboards[currprefs.cpuboard_type].subtypes[currprefs.cpuboard_subtype].e8(addr, &value, 2, true))
return;
- }
}
if (ecard >= cardno)
return;
case 0x48:
// A2630 boot rom writes WORDs to Z2 boards!
if (expamem_type() == zorroII) {
+ expamem_lo = 0;
expamem_hi = (value >> 8) & 0xff;
expamem_z2_pointer = (expamem_hi | (expamem_lo >> 4)) << 16;
expamem_board_pointer = expamem_z2_pointer;
#ifdef JIT
special_mem |= S_WRITE;
#endif
+ value &= 0xff;
+ if (cpuboards[currprefs.cpuboard_type].subtypes[currprefs.cpuboard_subtype].e8) {
+ if (cpuboards[currprefs.cpuboard_type].subtypes[currprefs.cpuboard_subtype].e8(addr, &value, 1, true))
+ return;
+ }
if (ecard >= cardno)
return;
- value &= 0xff;
switch (addr & 0xff) {
case 0x48:
if (expamem_type() == zorroII) {
else if (allocated == 0x800000)
type |= Z2_MEM_8MB;
- if (currprefs.cpuboard_type == BOARD_A2630 && boardnum != 0) {
+ if (ISCPUBOARD(BOARD_COMMODORE, BOARD_COMMODORE_SUB_A26x0) && boardnum != 0) {
for (int i = 1; i < 16; i++)
expamem_write(i * 4, a2630_autoconfig[i]);
type &= 7;
}
for (int i = 0; expansionroms[i].name; i++) {
const struct expansionromtype *erc = &expansionroms[i];
- if (erc->zorro == 2 && cfgfile_board_enabled(&currprefs, erc->romtype) && erc->memory_mid) {
- mid = erc->memory_mid;
- pid = erc->memory_pid;
- serial = erc->memory_serial;
- type |= chainedconfig;
+ if (erc->zorro == 2 && cfgfile_board_enabled(&currprefs, erc->romtype)) {
+ struct romconfig *rc = get_device_romconfig(&currprefs, 0, erc->romtype);
+ if (erc->subtypes) {
+ const struct expansionsubromtype *srt = &erc->subtypes[rc->subtype];
+ if (srt->memory_mid) {
+ mid = srt->memory_mid;
+ pid = srt->memory_pid;
+ serial = srt->memory_serial;
+ type |= chainedconfig;
+ }
+ } else {
+ if (erc->memory_mid) {
+ mid = erc->memory_mid;
+ pid = erc->memory_pid;
+ serial = erc->memory_serial;
+ type |= chainedconfig;
+ }
+ }
break;
}
}
if (!expamem_z3hack(&currprefs))
z3fastmem_bank.start = Z3BASE_REAL;
if (z3fastmem_bank.start == Z3BASE_REAL) {
- if (currprefs.cpuboard_type == BOARD_WARPENGINE_A4000) {
- z3fastmem_bank.start += 0x01000000;
+ int z3off = cpuboards[currprefs.cpuboard_type].subtypes[currprefs.cpuboard_subtype].z3extra;
+ if (z3off) {
+ z3fastmem_bank.start += z3off;
z3fastmem_bank.start = expansion_startaddress(z3fastmem_bank.start, currprefs.z3fastmem_size);
}
}
if (currprefs.cs_mbdmac == 1 || currprefs.cpuboard_type)
b = RTAREA_BACKUP;
// CSPPC enables MMU at boot and remaps 0xea0000->0xeffff.
- if (currprefs.cpuboard_type == BOARD_BLIZZARDPPC)
+ if (ISCPUBOARD(BOARD_BLIZZARD, BOARD_BLIZZARD_SUB_PPC))
b = RTAREA_BACKUP_2;
ab = &get_mem_bank (RTAREA_DEFAULT);
if (ab) {
// immediately after Z2Fast so that they can be emulated as A590/A2091 with fast ram.
- if (currprefs.cpuboard_type == BOARD_A3001_I) {
- card_flags[cardno] = 0;
- card_name[cardno] = _T("A3001 IDE");
- card_init[cardno] = gvp_ide_rom_autoconfig_init;
- card_map[cardno++] = NULL;
- } else if (currprefs.cpuboard_type == BOARD_A3001_II) {
- card_flags[cardno] = 0;
- card_name[cardno] = _T("A3001 BOOT");
- card_init[cardno] = gvp_ide_rom_autoconfig_init;
- card_map[cardno++] = NULL;
- card_flags[cardno] = 0;
- card_name[cardno] = _T("A3001 IDE");
- card_init[cardno] = gvp_ide_controller_autoconfig_init;
- card_map[cardno++] = NULL;
- }
- if (currprefs.cpuboard_type == BOARD_GVP_A530) {
- card_flags[cardno] = 1;
- card_name[cardno] = _T("GVP A530");
- card_init[cardno] = gvp_init_accelerator;
- card_map[cardno++] = NULL;
- }
-
- if (currprefs.cpuboard_type == BOARD_APOLLO) {
- card_name[cardno] = _T("Apollo");
- card_init[cardno] = apollo_init_cpu;
+ const struct cpuboardsubtype *cst = &cpuboards[currprefs.cpuboard_type].subtypes[currprefs.cpuboard_subtype];
+ if (cst->init && cst->initzorro == 2) {
+ card_flags[cardno] = cst->initflag;
+ card_name[cardno] = cst->name;
+ card_init[cardno] = cst->init;
card_map[cardno++] = NULL;
+ if (cst->init2) {
+ card_flags[cardno] = cst->initflag;
+ card_name[cardno] = cst->name;
+ card_init[cardno] = cst->init2;
+ card_map[cardno++] = NULL;
+ }
}
for (int i = 0; expansionroms[i].name; i++) {
/* Z3 boards last */
if (!currprefs.address_space_24) {
- if (currprefs.cpuboard_type == BOARD_WARPENGINE_A4000) {
- card_flags[cardno] = 1;
- card_name[cardno] = _T("Warp Engine");
- card_init[cardno] = ncr710_warpengine_autoconfig_init;
- card_map[cardno++] = NULL;
- }
- if (currprefs.cpuboard_type == BOARD_DKB1200) {
- card_name[cardno] = _T("DKB SCSI");
- card_init[cardno] = ncr_dkb_autoconfig_init;
+ const struct cpuboardsubtype *cst = &cpuboards[currprefs.cpuboard_type].subtypes[currprefs.cpuboard_subtype];
+ if (cst->init && cst->initzorro == 3) {
+ card_flags[cardno] = cst->initflag;
+ card_name[cardno] = cst->name;
+ card_init[cardno] = cst->init;
card_map[cardno++] = NULL;
}
+
if (z3fastmem_bank.baseaddr != NULL) {
z3num = 0;
card_flags[cardno] = 2 | 1;
int add_cpuboard_unit(int unit, struct uaedev_config_info *uci);
+#if 0
+static const struct expansionsubromtype a2090_sub[] = {
+ {
+ _T("A2090a"), _T("a2090a"),
+ 0, 0, 0,
+ { 0 },
+ },
+ {
+ _T("A2090a + 1M RAM"), _T("a2090a_2"),
+ 0, 0, 0,
+ { 0 },
+ },
+ {
+ NULL
+ }
+};
+#endif
+static const struct expansionsubromtype a2091_sub[] = {
+ {
+ _T("DMAC-01"), _T("dmac01"),
+ commodore, commodore_a2091_ram, 0,
+ { 0 },
+ },
+ {
+ _T("DMAC-02"), _T("dmac02"),
+ commodore, commodore_a2091_ram, 0,
+ { 0 },
+ },
+ {
+ NULL
+ }
+};
+static const struct expansionsubromtype gvp1_sub[] = {
+ {
+ _T("Impact A2000-1/X"), _T("a2000-1"),
+ 1761, 8, 0,
+ { 0 },
+ },
+ {
+ _T("Impact A2000-HC"), _T("a2000-hc"),
+ 1761, 8, 0,
+ { 0 },
+ },
+ {
+ _T("Impact A2000-HC+2"), _T("a2000-hc+"),
+ 1761, 8, 0,
+ { 0 },
+ },
+ {
+ NULL
+ }
+};
+static const struct expansionsubromtype masoboshi_sub[] = {
+ {
+ _T("MC-302"), _T("mc-302"),
+ 2157, 3, 0,
+ { 0 },
+ },
+ {
+ _T("MC-702"), _T("mc-702"),
+ 2157, 3, 0,
+ { 0 },
+ },
+ {
+ NULL
+ }
+};
+static const struct expansionsubromtype supra_sub[] = {
+ {
+ _T("A500 ByteSync/XP"), _T("bytesync"),
+ 1056, 3, 9,
+ { 0 },
+ },
+ {
+ _T("A2000 Word Sync"), _T("wordsync"),
+ 1056, 3, 9,
+ { 0 },
+ },
+ {
+ _T("A500 Autoboot"), _T("500"),
+ 1056, 3, 5,
+ { 0 },
+ },
+ {
+ _T("Non Autoboot (4x4)"), _T("4x4"),
+ 1056, 3, 2,
+ { 0 },
+ },
+ {
+ NULL
+ }
+};
+
const struct expansionromtype expansionroms[] = {
{
_T("cpuboard"), _T("Accelerator board"),
- NULL, add_cpuboard_unit, ROMTYPE_CPUBOARD, 0, 0,
+ NULL, add_cpuboard_unit, ROMTYPE_CPUBOARD, 0, 0, 0,
+ NULL, 0,
false, EXPANSIONTYPE_SCSI | EXPANSIONTYPE_IDE
},
{
_T("cpuboard_ext"), _T("Blizzard SCSI Kit IV"),
- NULL, NULL, ROMTYPE_CPUBOARDEXT, ROMTYPE_CPUBOARD, 0,
+ NULL, NULL, ROMTYPE_CPUBOARDEXT, ROMTYPE_CPUBOARD, 0, 0,
+ NULL, 0,
false, EXPANSIONTYPE_SCSI
},
+ {
+ _T("a2090a"), _T("A2090a"),
+ a2090_init, a2090_add_scsi_unit, ROMTYPE_A2090 | ROMTYPE_NONE, 0, 0, 2,
+ NULL, 0,
+ true, EXPANSIONTYPE_SCSI
+ },
{
_T("a2091"), _T("A590/A2091"),
- a2091_init, a2091_add_scsi_unit, ROMTYPE_A2091 | ROMTYPE_NONE, 0, 2,
- true, EXPANSIONTYPE_SCSI, commodore, commodore_a2091_ram, 0
+ a2091_init, a2091_add_scsi_unit, ROMTYPE_A2091 | ROMTYPE_NONE, 0, 0, 2,
+ a2091_sub, 1,
+ true, EXPANSIONTYPE_SCSI
},
{
_T("a4091"), _T("A4091"),
- ncr710_a4091_autoconfig_init, a4091_add_scsi_unit, ROMTYPE_A4091, 0, 3,
+ ncr710_a4091_autoconfig_init, a4091_add_scsi_unit, ROMTYPE_A4091, 0, 0, 3,
+ NULL, 0,
false, EXPANSIONTYPE_SCSI
},
{
_T("fastlane"), _T("Fastlane"),
- ncr_fastlane_autoconfig_init, fastlane_add_scsi_unit, ROMTYPE_FASTLANE, 0, 3,
+ ncr_fastlane_autoconfig_init, fastlane_add_scsi_unit, ROMTYPE_FASTLANE, 0, 0, 3,
+ NULL, 0,
false, EXPANSIONTYPE_SCSI
},
{
_T("oktagon2008"), _T("Oktagon 2008"),
- ncr_oktagon_autoconfig_init, oktagon_add_scsi_unit, ROMTYPE_OKTAGON, 0, 2,
+ ncr_oktagon_autoconfig_init, oktagon_add_scsi_unit, ROMTYPE_OKTAGON, 0, 0, 2,
+ NULL, 0,
false, EXPANSIONTYPE_SCSI
},
{
_T("gvp1"), _T("GVP Series I"),
- gvp_init_s1, gvp_add_scsi_unit, ROMTYPE_GVPS1 | ROMTYPE_NONE, 0, 2,
- true, EXPANSIONTYPE_SCSI, 2017, 10, 0
+ gvp_init_s1, gvp_add_scsi_unit, ROMTYPE_GVPS1 | ROMTYPE_NONE, ROMTYPE_GVPS12, 0, 2,
+ gvp1_sub, 1,
+ true, EXPANSIONTYPE_SCSI
},
{
_T("gvp"), _T("GVP Series II"),
- gvp_init_s2, gvp_add_scsi_unit, ROMTYPE_GVPS2 | ROMTYPE_NONE, 0, 2,
- true, EXPANSIONTYPE_SCSI, 2017, 10, 0
+ gvp_init_s2, gvp_add_scsi_unit, ROMTYPE_GVPS2 | ROMTYPE_NONE, ROMTYPE_GVPS12, 0, 2,
+ NULL, 0,
+ true, EXPANSIONTYPE_SCSI,
+ 2017, 10, 0
},
{
_T("amax"), _T("AMAX ROM dongle"),
- NULL, NULL, ROMTYPE_AMAX | ROMTYPE_NONE, 0, 0
+ NULL, 0,
+ NULL, NULL, ROMTYPE_AMAX | ROMTYPE_NONE, 0, 0, 0
},
{
_T("alfapower"), _T("AlfaPower/AT-Bus 2008"),
- alf_init, alf_add_ide_unit, ROMTYPE_ALFA, 0, 2,
- false, EXPANSIONTYPE_IDE, 2092, 8, 0
+ alf_init, alf_add_ide_unit, ROMTYPE_ALFA, 0, 0, 2,
+ NULL, 0,
+ false, EXPANSIONTYPE_IDE,
+ 2092, 8, 0
},
{
_T("alfapowerplus"), _T("AlfaPower Plus"),
- alf_init, alf_add_ide_unit, ROMTYPE_ALFAPLUS, 0, 2,
- false, EXPANSIONTYPE_IDE, 2092, 8, 0
+ alf_init, alf_add_ide_unit, ROMTYPE_ALFAPLUS, 0, 0, 2,
+ NULL, 0,
+ false, EXPANSIONTYPE_IDE,
+ 2092, 8, 0
},
{
_T("apollo"), _T("Apollo"),
- apollo_init, apollo_add_scsi_unit, ROMTYPE_APOLLO, 0, 2,
- false, EXPANSIONTYPE_SCSI | EXPANSIONTYPE_IDE, 8738, 0, 0
+ apollo_init, apollo_add_scsi_unit, ROMTYPE_APOLLO, 0, 0, 2,
+ NULL, 0,
+ false, EXPANSIONTYPE_SCSI | EXPANSIONTYPE_IDE,
+ 8738, 0, 0
},
{
_T("masoboshi"), _T("Masoboshi"),
- masoboshi_init, masoboshi_add_scsi_unit, ROMTYPE_MASOBOSHI | ROMTYPE_NONE, 0, 2,
- true, EXPANSIONTYPE_SCSI | EXPANSIONTYPE_IDE, 2157, 3, 0
+ masoboshi_init, masoboshi_add_idescsi_unit, ROMTYPE_MASOBOSHI | ROMTYPE_NONE, 0, 0, 2,
+ masoboshi_sub, 0,
+ true, EXPANSIONTYPE_SCSI | EXPANSIONTYPE_IDE
+ },
+ {
+ _T("supradrive"), _T("SupraDrive"),
+ supra_init, supra_add_scsi_unit, ROMTYPE_SUPRA | ROMTYPE_NONE, 0, 0, 2,
+ supra_sub, 0,
+ true, EXPANSIONTYPE_SCSI | EXPANSIONTYPE_IDE
+ },
+ {
+ NULL
+ }
+};
+
+static const struct cpuboardsettings blizzardboard_settings[] = {
+ {
+ _T("MapROM"),
+ _T("maprom")
+ },
+ {
+ NULL
+ }
+};
+
+static const struct cpuboardsubtype gvpboard_sub[] = {
+ {
+ _T("A3001 Series I"),
+ _T("A3001SI"),
+ ROMTYPE_CB_A3001S1, 0,
+ gvp_add_ide_unit, EXPANSIONTYPE_IDE,
+ BOARD_MEMORY_Z2,
+ 8 * 1024 * 1024,
+ 0,
+ gvp_ide_rom_autoconfig_init, NULL, 2, 0
+ },
+ {
+ _T("A3001 Series II"),
+ _T("A3001SII"),
+ 0, 0,
+ gvp_add_ide_unit, EXPANSIONTYPE_IDE,
+ BOARD_MEMORY_Z2,
+ 8 * 1024 * 1024,
+ 0,
+ gvp_ide_rom_autoconfig_init, gvp_ide_controller_autoconfig_init, 2, 0
+ },
+ {
+ _T("A530"),
+ _T("GVPA530"),
+ ROMTYPE_GVPS2, 0,
+ gvp_add_scsi_unit, EXPANSIONTYPE_SCSI,
+ BOARD_MEMORY_Z2,
+ 8 * 1024 * 1024,
+ 0,
+ gvp_init_accelerator, NULL, 2, 1
+ },
+ {
+ _T("G-Force 030"),
+ _T("GVPGFORCE030"),
+ ROMTYPE_GVPS2, 0,
+ gvp_add_scsi_unit, EXPANSIONTYPE_SCSI,
+ BOARD_MEMORY_25BITMEM,
+ 128 * 1024 * 1024,
+ 0,
+ gvp_init_accelerator, NULL, 2, 1
+ },
+ {
+ _T("Tek Magic 2040/2060"),
+ _T("TekMagic"),
+ ROMTYPE_CB_TEKMAGIC, 0,
+ tekmagic_add_scsi_unit, EXPANSIONTYPE_SCSI,
+ BOARD_MEMORY_HIGHMEM,
+ 128 * 1024 * 1024
+ },
+ {
+ NULL
+ }
+};
+static const struct cpuboardsubtype blizzardboard_sub[] = {
+ {
+ _T("1230 IV"),
+ _T("Blizzard1230IV"),
+ ROMTYPE_CB_BLIZ1230, 0,
+ cpuboard_ncr9x_add_scsi_unit, EXPANSIONTYPE_SCSI,
+ BOARD_MEMORY_BLIZZARD_12xx,
+ 256 * 1024 * 1024,
+ 0,
+ NULL, NULL, 0, 0,
+ blizzardboard_settings
+ },
+ {
+ _T("1260"),
+ _T("Blizzard1260"),
+ ROMTYPE_CB_BLIZ1260, 0,
+ cpuboard_ncr9x_add_scsi_unit, EXPANSIONTYPE_SCSI,
+ BOARD_MEMORY_BLIZZARD_12xx,
+ 256 * 1024 * 1024,
+ 0,
+ NULL, NULL, 0, 0,
+ blizzardboard_settings
+ },
+ {
+ _T("2060"),
+ _T("Blizzard2060"),
+ ROMTYPE_CB_BLIZ2060, 0,
+ cpuboard_ncr9x_add_scsi_unit, EXPANSIONTYPE_SCSI,
+ BOARD_MEMORY_HIGHMEM,
+ 128 * 1024 * 1024,
+ 0,
+ NULL, NULL, 0, 0,
+ blizzardboard_settings
+ },
+ {
+ _T("PPC"),
+ _T("BlizzardPPC"),
+ ROMTYPE_CB_BLIZPPC, 0,
+ blizzardppc_add_scsi_unit, EXPANSIONTYPE_SCSI,
+ BOARD_MEMORY_BLIZZARD_PPC,
+ 256 * 1024 * 1024
+ },
+ {
+ NULL
+ }
+};
+static const struct cpuboardsubtype cyberstormboard_sub[] = {
+ {
+ _T("MK I"),
+ _T("CyberStormMK1"),
+ ROMTYPE_CB_CSMK1, 0,
+ cpuboard_ncr9x_add_scsi_unit, EXPANSIONTYPE_SCSI,
+ BOARD_MEMORY_HIGHMEM,
+ 128 * 1024 * 1024
+ },
+ {
+ _T("MK II"),
+ _T("CyberStormMK2"),
+ ROMTYPE_CB_CSMK2, 0,
+ cpuboard_ncr9x_add_scsi_unit, EXPANSIONTYPE_SCSI,
+ BOARD_MEMORY_HIGHMEM,
+ 128 * 1024 * 1024
+ },
+ {
+ _T("MK III"),
+ _T("CyberStormMK3"),
+ ROMTYPE_CB_CSMK3, 0,
+ cyberstorm_add_scsi_unit, EXPANSIONTYPE_SCSI,
+ BOARD_MEMORY_HIGHMEM,
+ 128 * 1024 * 1024
+ },
+ {
+ _T("PPC"),
+ _T("CyberStormPPC"),
+ ROMTYPE_CB_CSPPC, 0,
+ cyberstorm_add_scsi_unit, EXPANSIONTYPE_SCSI,
+ BOARD_MEMORY_HIGHMEM,
+ 128 * 1024 * 1024
+ },
+ {
+ NULL
+ }
+};
+static const struct cpuboardsubtype warpengine_sub[] = {
+ {
+ _T("Warp Engine A4000"),
+ _T("WarpEngineA4000"),
+ ROMTYPE_CB_WENGINE, 0,
+ warpengine_add_scsi_unit, EXPANSIONTYPE_SCSI,
+ BOARD_MEMORY_HIGHMEM,
+ 128 * 1024 * 1024,
+ 0x01000000,
+ ncr710_warpengine_autoconfig_init, NULL, 3, 1
+ },
+ {
+ NULL
+ }
+};
+static const struct cpuboardsettings a26x0board_settings[] = {
+ {
+ _T("OSMODE (J304)"),
+ _T("j304")
+ },
+ {
+ NULL
+ }
+};
+static const struct cpuboardsubtype commodore_sub[] = {
+ {
+ _T("A2620/A2630"),
+ _T("A2630"),
+ ROMTYPE_CB_A26x0, 0,
+ NULL, 0,
+ BOARD_MEMORY_25BITMEM,
+ 128 * 1024 * 1024,
+ 0,
+ NULL, NULL, 0, 0,
+ a26x0board_settings,
+ cpuboard_io_special
+ },
+ {
+ NULL
+ }
+};
+static const struct cpuboardsubtype dbk_sub[] = {
+ {
+ _T("1230/1240"),
+ _T("DKB12x0"),
+ ROMTYPE_CB_DKB12x0, 0,
+ cpuboard_dkb_add_scsi_unit, EXPANSIONTYPE_SCSI,
+ BOARD_MEMORY_HIGHMEM,
+ 128 * 1024 * 1024,
+ 0,
+ ncr_dkb_autoconfig_init, NULL, 2, 0
+ },
+ {
+ NULL
+ }
+};
+static const struct cpuboardsubtype fusionforty_sub[] = {
+ {
+ _T("Fusion Forty"),
+ _T("FusionForty"),
+ ROMTYPE_CB_FUSION, 0,
+ NULL, 0,
+ BOARD_MEMORY_HIGHMEM,
+ 128 * 1024 * 1024
+ },
+ {
+ NULL
+ }
+};
+static const struct cpuboardsubtype apollo_sub[] = {
+ {
+ _T("Apollo 1240/1260"),
+ _T("Apollo"),
+ ROMTYPE_CB_APOLLO, 0,
+ apollo_add_scsi_unit, EXPANSIONTYPE_SCSI,
+ BOARD_MEMORY_HIGHMEM,
+ 128 * 1024 * 1024,
+ 0,
+ apollo_init_cpu, NULL, 2, 0
+ },
+ {
+ NULL
+ }
+};
+static const struct cpuboardsubtype dummy_sub[] = {
+ { NULL }
+};
+
+const struct cpuboardtype cpuboards[] = {
+ {
+ _T("-"),
+ dummy_sub, 0
+ },
+ {
+ _T("Phase 5 - Blizzard"),
+ blizzardboard_sub, 0
+ },
+ {
+ _T("Phase 5 - CyberStorm"),
+ cyberstormboard_sub, 0
+ },
+ {
+ _T("MacroSystem"),
+ warpengine_sub, 0
+ },
+ {
+ _T("Commodore"),
+ commodore_sub, 0
+ },
+ {
+ _T("DKB"),
+ dbk_sub, 0
+ },
+ {
+ _T("RCS Management"),
+ fusionforty_sub, 0
+ },
+ {
+ _T("ACT"),
+ apollo_sub, 0
},
{
- _T("suprabytesync"), _T("SupraDrive 500XP"),
- supra_init, supra_add_scsi_unit, ROMTYPE_SUPRA | ROMTYPE_NONE, 0, 2,
- true, EXPANSIONTYPE_SCSI | EXPANSIONTYPE_IDE, 1056, 9, 0
+ _T("GVP"),
+ gvpboard_sub, 0
},
{
NULL
bool wasisempty; /* if true, this unit was created empty */
bool canremove; /* if true, this unit can be safely ejected and remounted */
bool configureddrive; /* if true, this is drive that was manually configured */
+ bool inject_icons; /* inject icons if directory filesystem */
struct hardfiledata hf;
if (c.bootpri > 127)
c.bootpri = 127;
ui->bootpri = c.bootpri;
+ ui->inject_icons = c.inject_icons;
ui->open = 1;
return nr;
int add_cpuboard_unit(int unit, struct uaedev_config_info *uci)
{
bool added = false;
- bool ide = uci->controller_type >= HD_CONTROLLER_TYPE_IDE_FIRST && uci->controller_type <= HD_CONTROLLER_TYPE_IDE_LAST;
- if (!ide) {
-#ifdef NCR
- if (currprefs.cpuboard_type == BOARD_WARPENGINE_A4000) {
- warpengine_add_scsi_unit(unit, uci);
- added = true;
- } else if (currprefs.cpuboard_type == BOARD_DKB1200) {
- cpuboard_dkb_add_scsi_unit(unit, uci);
- added = true;
- } else if (currprefs.cpuboard_type == BOARD_TEKMAGIC) {
- tekmagic_add_scsi_unit(unit, uci);
- added = true;
- } else if (currprefs.cpuboard_type == BOARD_CSMK3 || currprefs.cpuboard_type == BOARD_CSPPC) {
- cyberstorm_add_scsi_unit(unit, uci);
- added = true;
- } else if (currprefs.cpuboard_type == BOARD_BLIZZARDPPC) {
- blizzardppc_add_scsi_unit(unit, uci);
- added = true;
- } else if (currprefs.cpuboard_type == BOARD_BLIZZARD_2060 ||
- currprefs.cpuboard_type == BOARD_CSMK1 ||
- currprefs.cpuboard_type == BOARD_CSMK2) {
- cpuboard_ncr9x_add_scsi_unit(unit, uci);
- added = true;
- } else if (currprefs.cpuboard_type == BOARD_BLIZZARD_1230_IV ||
- currprefs.cpuboard_type == BOARD_BLIZZARD_1260) {
- if (cfgfile_board_enabled(&currprefs, ROMTYPE_CPUBOARDEXT)) {
- cpuboard_ncr9x_add_scsi_unit(unit, uci);
- added = true;
- }
- }
-#endif
- if (currprefs.cpuboard_type == BOARD_APOLLO) {
- apollo_add_scsi_unit(unit, uci);
- added = true;
- } else if (currprefs.cpuboard_type == BOARD_GVP_A530) {
- gvp_add_scsi_unit(unit, uci);
- added = true;
- }
- } else {
- if (currprefs.cpuboard_type == BOARD_A3001_I || currprefs.cpuboard_type == BOARD_A3001_II) {
- gvp_add_ide_unit(unit, uci);
- added = true;
- }
+ int flags = (uci->controller_type >= HD_CONTROLLER_TYPE_IDE_FIRST && uci->controller_type <= HD_CONTROLLER_TYPE_IDE_LAST) ? EXPANSIONTYPE_IDE : EXPANSIONTYPE_SCSI;
+ const struct cpuboardtype *cbt = &cpuboards[currprefs.cpuboard_type];
+ if (cbt->subtypes) {
+ if (cbt->subtypes[currprefs.cpuboard_subtype].add && (cbt->subtypes[currprefs.cpuboard_subtype].deviceflags & flags))
+ added = cbt->subtypes[currprefs.cpuboard_subtype].add(unit, uci);
}
return added;
}
if (i == type - HD_CONTROLLER_TYPE_SCSI_EXPANSION_FIRST) {
const struct expansionromtype *ert = &expansionroms[i];
if ((ert->deviceflags & 1) && cfgfile_board_enabled(&currprefs, ert->romtype)) {
- if (ert->add)
- ert->add(unit, uci);
- added = true;
+ if (ert->add) {
+ added = ert->add(unit, uci);
+ } else {
+ added = true;
+ }
}
}
}
aino = lookup_child_aino_for_exnext (unit, base, fn, &err, uniq, NULL);
}
fs_closedir (d);
- if (currprefs.filesys_inject_icons)
+ if (currprefs.filesys_inject_icons || unit->ui.inject_icons)
inject_icons_to_directory(unit, base);
}
switch (currprefs.fpu_model)
{
case 68881:
- v = 0x1f;
- break;
case 68882:
- v = 0x20;
+ v = 0x1f;
break;
case 68040:
if (currprefs.fpu_revision == 0x40)
fpset (®s.fp_result, 1);
}
-uae_u32 get_ftag (uae_u32 w1, uae_u32 w2, uae_u32 w3, int size)
+static uae_u32 get_ftag (uae_u32 w1, uae_u32 w2, uae_u32 w3, int size)
{
int exp = (w1 >> 16) & 0x7fff;
fpd->fp = d;
}
-void from_pack (fpdata *src, uae_u32 *wrd, int kfactor)
+static void from_pack (fpdata *src, uae_u32 *wrd, int kfactor)
{
int i, j, t;
int exp;
static int get_fp_value (uae_u32 opcode, uae_u16 extra, fpdata *src, uaecptr oldpc, uae_u32 *adp)
{
int size, mode, reg;
- uae_u32 ad = 0, ad2;
+ uae_u32 ad = 0;
static const int sz1[8] = { 4, 4, 12, 12, 2, 8, 1, 0 };
static const int sz2[8] = { 4, 4, 12, 12, 2, 8, 2, 0 };
uae_u32 exts[3];
}
*adp = ad;
- ad2 = ad;
if (currprefs.fpu_model == 68060 && fault_if_unimplemented_680x0 (opcode, extra, ad, oldpc, src, -1))
return -1;
void fpuop_restore (uae_u32 opcode)
{
- int fpu_version = get_fpu_version ();
+ int fpu_version = get_fpu_version (); // TODO: check version of stack frame
uaecptr pc = m68k_getpc () - 2;
uae_u32 ad;
uae_u32 d;
return;
regs.fpiar = pc;
- uae_u32 pad = ad;
if (incr < 0) {
ad -= 4;
d = x_get_long (ad);
void gayle_hsync (void)
{
- if (ide_interrupt_check(idedrive[0]) || ide_interrupt_check(idedrive[2]) || ide_interrupt_check(idedrive[4]))
+ if (ide_interrupt_hsync(idedrive[0]) || ide_interrupt_hsync(idedrive[2]) || ide_interrupt_hsync(idedrive[4]))
rethink_gayle ();
}
static int using_prefetch, using_indirect, using_mmu;
static int using_prefetch_020, using_ce020;
static int using_exception_3;
+static int using_bus_error;
static int using_ce;
static int using_tracer;
static int using_waitstates;
static const char *srcbrmw, *srcwrmw, *srclrmw;
static const char *dstbrmw, *dstwrmw, *dstlrmw;
static const char *prefetch_long, *prefetch_word;
-static const char *srcli, *srcwi, *srcbi, *nextl, *nextw, *nextb;
+static const char *srcli, *srcwi, *srcbi, *nextl, *nextw;
static const char *srcld, *dstld;
static const char *srcwd, *dstwd;
static const char *do_cycles, *disp000, *disp020, *getpc;
static void genamode2x (amodes mode, const char *reg, wordsizes size, const char *name, int getv, int movem, int flags, int fetchmode)
{
char namea[100];
- int m68k_pc_offset_last = m68k_pc_offset;
bool rmw = false;
+ int pc_68000_offset = m68k_pc_offset;
+ int pc_68000_offset_fetch = 0;
+ int pc_68000_offset_store = 0;
sprintf (namea, "%sa", name);
if ((flags & GF_RMW) && using_mmu == 68060) {
addcycles000 (2);
insn_n_cycles += 2;
count_cycles_ea += 2;
+ pc_68000_offset_fetch += 2;
}
break;
case Ad16: // (d16,An)
printf ("\tuaecptr %sa;\n", name);
add_mmu040_movem (movem);
printf ("\t%sa = (uae_s32)(uae_s16)%s;\n", name, gen_nextiword (flags));
+ pc_68000_offset_fetch += 2;
break;
case absl:
gen_nextilong2 ("uaecptr", namea, flags, movem);
count_read_ea += 2;
+ pc_68000_offset_fetch += 4;
+ pc_68000_offset_store += 2;
break;
case imm:
// fetch immediate address
/* We get here for all non-reg non-immediate addressing modes to
* actually fetch the value. */
- if ((using_prefetch || using_ce) && using_exception_3 && getv != 0 && size != sz_byte) {
- int offset = 0;
- if (flags & GF_MOVE) {
- offset = m68k_pc_offset;
- if (getv == 2)
- offset += 2;
- } else {
- offset = m68k_pc_offset_last;
+ int exception_pc_offset = 0;
+ if (getv == 2) {
+ // store
+ if (pc_68000_offset) {
+ exception_pc_offset = pc_68000_offset + pc_68000_offset_store + 2;
}
+ } else {
+ // fetch
+ pc_68000_offset_fetch += 2;
+ exception_pc_offset = pc_68000_offset_fetch;
+ }
+
+ if ((using_prefetch || using_ce) && using_exception_3 && getv != 0 && size != sz_byte) {
printf ("\tif (%sa & 1) {\n", name);
- if (offset > 2)
- incpc ("%d", offset - 2);
- printf ("\t\texception3 (opcode, %sa);\n", name);
+ if (exception_pc_offset)
+ incpc("%d", exception_pc_offset);
+ printf ("\t\texception3_%s(opcode, %sa);\n", getv == 2 ? "write" : "read", name);
printf ("\t\tgoto %s;\n", endlabelstr);
printf ("\t}\n");
need_endlabel = 1;
start_brace ();
}
+ if ((using_prefetch || using_ce) && using_bus_error && getv != 0) {
+ if (exception_pc_offset)
+ printf("\tbus_error_offset = %d;\n", exception_pc_offset);
+ }
+
if (flags & GF_PREFETCH)
fill_prefetch_next ();
else if (flags & GF_IR2IRC)
static void movem_mmu060 (const char *code, int size, bool put, bool aipi, bool apdi)
{
const char *index;
- int dphase, aphase;
+ int dphase;
+
if (apdi) {
- dphase = 1; aphase = 0;
+ dphase = 1;
index = "movem_index2";
} else {
- dphase = 0; aphase = 1;
+ dphase = 0;
index = "movem_index1";
}
static void movem_mmu030 (const char *code, int size, bool put, bool aipi, bool apdi)
{
const char *index;
- int dphase, aphase;
+ int dphase;
+
if (apdi) {
- dphase = 1; aphase = 0;
+ dphase = 1;
index = "movem_index2";
} else {
- dphase = 0; aphase = 1;
+ dphase = 0;
index = "movem_index1";
}
printf ("\tmmu030_state[1] |= MMU030_STATEFLAG1_MOVEM1;\n");
count_read += table68k[opcode].size == sz_long ? 2 : 1;
printf ("\tuae_u16 mask = %s;\n", gen_nextiword (0));
printf ("\tuae_u32 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
- genamode (NULL, table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, mmu040_special_movem (opcode) ? 3 : 1, 0);
+ genamode (NULL, table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, mmu040_special_movem (opcode) ? 3 : 1, GF_MOVE);
addcycles_ce020 (8 - 2);
start_brace ();
if (using_mmu == 68030) {
printf ("\tuae_u32 v;\n");
if (table68k[opcode].dmode == Ad8r || table68k[opcode].dmode == PC8r)
addcycles000 (2);
- genamode (NULL, table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1, GF_AA);
+ genamode (NULL, table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1, GF_AA | GF_MOVE);
start_brace ();
if (table68k[opcode].size == sz_long) {
printf ("\twhile (dmask) {\n");
count_write += table68k[opcode].size == sz_long ? 2 : 1;
printf ("\tuae_u16 mask = %s;\n", gen_nextiword (0));
- genamode (NULL, table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, mmu040_special_movem (opcode) ? 3 : 1, 0);
+ genamode (NULL, table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, mmu040_special_movem (opcode) ? 3 : 1, GF_MOVE);
addcycles_ce020 (4 - 2);
start_brace ();
if (using_mmu >= 68030) {
printf ("\tuae_u16 mask = %s;\n", gen_nextiword (0));
if (table68k[opcode].dmode == Ad8r || table68k[opcode].dmode == PC8r)
addcycles000 (2);
- genamode (NULL, table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1, GF_AA);
+ genamode (NULL, table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1, GF_AA | GF_MOVE);
start_brace ();
if (table68k[opcode].size == sz_long) {
if (table68k[opcode].dmode == Apdi) {
else
subhead = gence020cycles_fea (curi->smode);
}
- genamode2x (curi->smode, "srcreg", curi->size, "src", 1, 0, GF_MOVE, fea ? fetchmode_fea : -1);
+ genamode2x (curi->smode, "srcreg", curi->size, "src", 1, 0, 0, fea ? fetchmode_fea : -1);
genamode2 (curi->dmode, "dstreg", curi->size, "dst", 2, 0, GF_MOVE);
addopcycles_ce20 (h, t, c, -subhead);
if (curi->mnemo == i_MOVEA && curi->size == sz_word)
} else {
int prefetch_done = 0, flags;
int dualprefetch = curi->dmode == absl && (curi->smode != Dreg && curi->smode != Areg && curi->smode != imm);
- genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, GF_MOVE);
+ genamode (curi, curi->smode, "srcreg", curi->size, "src", 1, 0, 0);
flags = GF_MOVE | GF_APDI;
//if (curi->size == sz_long && (curi->smode == Dreg || curi->smode == Areg))
// flags &= ~GF_APDI;
single_check_ipl();
}
}
-
genastore ("src", curi->dmode, "dstreg", curi->size, "dst");
sync_m68k_pc ();
if (dualprefetch) {
case i_BFINS:
{
const char *getb, *putb;
- int flags = 0;
if (using_mmu == 68060 && (curi->mnemo == i_BFCHG || curi->mnemo == i_BFCLR || curi->mnemo == i_BFSET || curi->mnemo == i_BFINS)) {
getb = "mmu060_get_rmw_bitfield";
return ret;
}
-static uae_u32 gamma[256 * 3];
+static uae_u32 gamma[256 * 3][3];
static int lf, hf;
static void video_calc_gammatable (void)
{
- int i;
- float bri, con, gam, v;
+ float bri, con, gam, gams[3], v;
uae_u32 vi;
bri = ((float)(currprefs.gfx_luminance)) * (128.0f / 1000.0f);
con = ((float)(currprefs.gfx_contrast + 1000)) / 1000.0f;
gam = ((float)(1000 - currprefs.gfx_gamma)) / 1000.0f;
+ gams[0] = gam + ((float)(1000 - currprefs.gfx_gamma_ch[0])) / 1000.0f;
+ gams[1] = gam + ((float)(1000 - currprefs.gfx_gamma_ch[1])) / 1000.0f;
+ gams[2] = gam + ((float)(1000 - currprefs.gfx_gamma_ch[2])) / 1000.0f;
lf = 64 * currprefs.gf[picasso_on].gfx_filter_blur / 1000;
hf = 256 - lf * 2;
- for (i = 0; i < (256 * 3); i++) {
- v = video_gamma((float)(i - 256), gam, bri, con);
+ for (int i = 0; i < (256 * 3); i++) {
+ for (int j = 0; j < 3; j++) {
+ v = video_gamma((float)(i - 256), gams[j], bri, con);
- vi = (uae_u32)v;
- if (vi > 255)
- vi = 255;
+ vi = (uae_u32)v;
+ if (vi > 255)
+ vi = 255;
- if (currprefs.gfx_luminance == 0 && currprefs.gfx_contrast == 0 && currprefs.gfx_gamma == 0)
- vi = i & 0xff;
+ if (currprefs.gfx_luminance == 0 && currprefs.gfx_contrast == 0 && currprefs.gfx_gamma == 0)
+ vi = i & 0xff;
- gamma[i] = vi;
+ gamma[i][j] = vi;
+ }
}
}
}
j += 256;
- rc[i] = doColor (gamma[j], rw, rs) | doAlpha (alpha, aw, as);
- gc[i] = doColor (gamma[j], gw, gs) | doAlpha (alpha, aw, as);
- bc[i] = doColor (gamma[j], bw, bs) | doAlpha (alpha, aw, as);
+ rc[i] = doColor (gamma[j][0], rw, rs) | doAlpha (alpha, aw, as);
+ gc[i] = doColor (gamma[j][1], gw, gs) | doAlpha (alpha, aw, as);
+ bc[i] = doColor (gamma[j][2], bw, bs) | doAlpha (alpha, aw, as);
if (byte_swap) {
if (bpp <= 16) {
rc[i] = bswap_16 (rc[i]);
int r = ((i >> 8) << 4) | (i >> 8);
int g = (((i >> 4) & 0xf) << 4) | ((i >> 4) & 0x0f);
int b = ((i & 0xf) << 4) | (i & 0x0f);
- r = gamma[r + j];
- g = gamma[g + j];
- b = gamma[b + j];
+ r = gamma[r + j][0];
+ g = gamma[g + j][1];
+ b = gamma[b + j][2];
xcolors[i] = doMask(r, rw, rs) | doMask(g, gw, gs) | doMask(b, bw, bs) | doAlpha (alpha, aw, as);
if (byte_swap) {
if (bpp <= 16)
/* create internal 5:6:5 color tables */
for (i = 0; i < 256; i++) {
j = i + 256;
- xredcolors[i] = doColor (gamma[j], 5, 11);
- xgreencolors[i] = doColor (gamma[j], 6, 5);
- xbluecolors[i] = doColor (gamma[j], 5, 0);
+ xredcolors[i] = doColor (gamma[j][0], 5, 11);
+ xgreencolors[i] = doColor (gamma[j][1], 6, 5);
+ xbluecolors[i] = doColor (gamma[j][2], 5, 0);
if (bpp <= 16) {
/* Fill upper 16 bits of each colour value with
* a copy of the colour. */
int r = ((i >> 8) << 4) | (i >> 8);
int g = (((i >> 4) & 0xf) << 4) | ((i >> 4) & 0x0f);
int b = ((i & 0xf) << 4) | (i & 0x0f);
- r = gamma[r + 256];
- g = gamma[g + 256];
- b = gamma[b + 256];
+ r = gamma[r + 256][0];
+ g = gamma[g + 256][1];
+ b = gamma[b + 256][2];
xcolors[i] = doMask(r, 5, 11) | doMask(g, 6, 5) | doMask(b, 5, 0);
if (byte_swap) {
if (bpp <= 16)
for (i = 0; i < 65536; i++) {
uae_u32 r, g, b;
r = (((i >> 11) & 31) << 3) | lowbits (i, 11, 3);
- r = gamma[r + 256];
+ r = gamma[r + 256][0];
g = (((i >> 5) & 63) << 2) | lowbits (i, 5, 2);
- g = gamma[g + 256];
+ g = gamma[g + 256][1];
b = (((i >> 0) & 31) << 3) | lowbits (i, 0, 3);
- b = gamma[b + 256];
+ b = gamma[b + 256][2];
tyhrgb[i] = get_yh (r, g, b) * 256 * 256;
tylrgb[i] = get_yl (r, g, b) * 256 * 256;
tcbrgb[i] = ((uae_s8)get_cb (r, g, b)) * 256;
s[12] = 0x25; /* INVALID LUN */
ls = 0x12;
write_log (_T("UAEHF: CMD=%02X LUN=%d ignored\n"), cmdbuf[0], lun);
- goto err_exit;
+ goto scsi_done;
}
+ switch (cmdbuf[0])
+ {
+ case 0x12: /* INQUIRY */
+ {
+ if ((cmdbuf[1] & 1) || cmdbuf[2] != 0)
+ goto err;
+ int alen = (cmdbuf[3] << 8) | cmdbuf[4];
+ if (lun != 0) {
+ r[0] = 0x7f;
+ } else {
+ r[0] = 0;
+ if (hfd->drive_empty) {
+ r[1] |= 0x80; // removable..
+ r[0] |= 0x20; // not present
+ }
+ }
+ r[2] = 2; /* supports SCSI-2 */
+ r[3] = 2; /* response data format */
+ r[4] = 32; /* additional length */
+ r[7] = 0;
+ scsi_len = lr = alen < 36 ? alen : 36;
+ if (hdhfd) {
+ r[2] = hdhfd->ansi_version;
+ r[3] = hdhfd->ansi_version >= 2 ? 2 : 0;
+ }
+ setdrivestring(hfd->vendor_id, r, 8, 8);
+ setdrivestring(hfd->product_id, r, 16, 16);
+ setdrivestring(hfd->product_rev, r, 32, 4);
+ }
+ goto scsi_done;
+ case 0x1b: /* START/STOP UNIT */
+ scsi_len = 0;
+ hfd->unit_stopped = (cmdbuf[4] & 1) == 0;
+ goto scsi_done;
+ }
+
+ if (hfd->unit_stopped) {
+ status = 2; /* CHECK CONDITION */
+ s[0] = 0x70;
+ s[2] = 2; /* NOT READY */
+ s[12] = 4; /* not ready */
+ s[13] = 2; /* need initialise command */
+ ls = 0x12;
+ goto scsi_done;
+ }
+
switch (cmdbuf[0])
{
case 0x00: /* TEST UNIT READY */
goto nodisk;
scsi_len = 0;
break;
- case 0x03: /* REQUEST SENSE */
- scsi_len = cmdbuf[4] > MAX_SCSI_SENSE ? MAX_SCSI_SENSE : cmdbuf[4];
- memcpy (r, hfd->scsi_sense, scsi_len);
- memset (hfd->scsi_sense, 0, MAX_SCSI_SENSE);
+ case 0x04: /* FORMAT UNIT */
+ // do nothing
+ if (nodisk (hfd))
+ goto nodisk;
+ if (hfd->ci.readonly || hfd->dangerous)
+ goto readprot;
+ scsi_len = 0;
break;
case 0x08: /* READ (6) */
if (nodisk (hfd))
goto outofbounds;
scsi_len = (uae_u32)cmd_writex (hfd, scsi_data, offset, len);
break;
- case 0x12: /* INQUIRY */
- {
- if ((cmdbuf[1] & 1) || cmdbuf[2] != 0)
- goto err;
- int alen = (cmdbuf[3] << 8) | cmdbuf[4];
- if (lun != 0) {
- r[0] = 0x7f;
- } else {
- r[0] = 0;
- if (hfd->drive_empty) {
- r[1] |= 0x80; // removable..
- r[0] |= 0x20; // not present
- }
- }
- r[2] = 2; /* supports SCSI-2 */
- r[3] = 2; /* response data format */
- r[4] = 32; /* additional length */
- r[7] = 0;
- scsi_len = lr = alen < 36 ? alen : 36;
- if (hdhfd) {
- r[2] = hdhfd->ansi_version;
- r[3] = hdhfd->ansi_version >= 2 ? 2 : 0;
- }
- setdrivestring(hfd->vendor_id, r, 8, 8);
- setdrivestring(hfd->product_id, r, 16, 16);
- setdrivestring(hfd->product_rev, r, 32, 4);
- }
- break;
case 0x1a: /* MODE SENSE(6) */
{
uae_u8 *p;
s[12] = 0x1c; /* DEFECT LIST NOT FOUND */
ls = 0x12;
break;
- case 0x1b: /* START/STOP UNIT */
- scsi_len = 0;
- break;
readprot:
status = 2; /* CHECK CONDITION */
s[0] = 0x70;
ls = 0x12;
break;
}
-err_exit:
+scsi_done:
if (log_scsiemu && ls) {
write_log (_T("-> SENSE STATUS: KEY=%d ASC=%02X ASCQ=%02X\n"), s[2], s[12], s[13]);
write_log (_T("\n"));
}
- if (cmdbuf[0] && log_scsiemu)
+ if (log_scsiemu)
write_log (_T("-> DATAOUT=%d ST=%d SENSELEN=%d REPLYLEN=%d\n"), scsi_len, status, ls, lr);
*data_len = scsi_len;
return false;
}
-bool ide_interrupt_check(struct ide_hdf *idep)
+bool ide_irq_check(struct ide_hdf *idep)
+{
+ for (int i = 0; i < 2; i++) {
+ struct ide_hdf *ide = i == 0 ? idep : idep->pair;
+ if (ide->irq)
+ return true;
+ }
+ return false;
+}
+
+bool ide_interrupt_hsync(struct ide_hdf *idep)
{
bool irq = false;
for (int i = 0; i < 2; i++) {
start_ide_thread(&idecontroller_its);
}
-static bool ide_irq_check(struct ide_board *board)
+static bool ide_interrupt_check(struct ide_board *board)
{
if (!board->configured)
return false;
- bool irq = ide_interrupt_check(board->ide);
+ bool irq = ide_irq_check(board->ide);
+#if 1
+ if (board->irq != irq)
+ write_log(_T("IDE irq %d -> %d\n"), board->irq, irq);
+#endif
board->irq = irq;
return irq;
}
{
bool irq = false;
if (board->configured) {
- if (board->intena && ide_irq_check(board)) {
+ if (board->intena && ide_interrupt_check(board)) {
irq = true;
}
}
void idecontroller_hsync(void)
{
for (int i = 0; ide_boards[i]; i++) {
- if (ide_irq_check(ide_boards[i])) {
- idecontroller_rethink();
+ struct ide_board *board = ide_boards[i];
+ if (board->configured) {
+ ide_interrupt_hsync(board->ide);
+ if (ide_interrupt_check(board)) {
+ idecontroller_rethink();
+ }
}
}
}
static bool is_gvp2_intreq(uaecptr addr)
{
- if (currprefs.cpuboard_type == BOARD_A3001_II && (addr & 0x440) == 0x440)
+ if (ISCPUBOARD(BOARD_GVP, BOARD_GVP_SUB_A3001SII) && (addr & 0x440) == 0x440)
return true;
return false;
}
static bool is_gvp1_intreq(uaecptr addr)
{
- if (currprefs.cpuboard_type == BOARD_A3001_I && (addr & 0x440) == 0x40)
+ if (ISCPUBOARD(BOARD_GVP, BOARD_GVP_SUB_A3001SI) && (addr & 0x440) == 0x40)
return true;
return false;
}
rom = true;
}
} else if (addr >= 0xf000 && addr <= 0xf007) {
- v = masoboshi_ncr9x_scsi_get(addr, board == &masoboshi_board[0] ? 0 : 1);
+ if (board->subtype)
+ v = masoboshi_ncr9x_scsi_get(addr, board == &masoboshi_board[0] ? 0 : 1);
} else if (addr == 0xf040) {
- v = 0;
- if (ide_drq_check(board->ide))
+ v = 1;
+ if (ide_irq_check(board->ide)) {
v |= 2;
- if (ide_interrupt_check(board->ide)) {
- v |= 1;
+ board->irq = true;
+ }
+ if (board->irq) {
+ v &= ~1;
}
v |= masoboshi_ncr9x_scsi_get(addr, board == &masoboshi_board[0] ? 0 : 1);
} else if (addr == 0xf047) {
if (regnum >= 0) {
v = ide_read_reg(ide, regnum);
} else if (addr >= MASOBOSHI_SCSI_OFFSET && addr < MASOBOSHI_SCSI_OFFSET_END) {
- v = masoboshi_ncr9x_scsi_get(addr, board == &masoboshi_board[0] ? 0 : 1);
+ if (board->subtype)
+ v = masoboshi_ncr9x_scsi_get(addr, board == &masoboshi_board[0] ? 0 : 1);
+ else
+ v = 0xff;
}
}
#if DEBUG_IDE_MASOBOSHI
return v;
}
if (board->configured) {
- if (board == &gvp_ide_rom_board && currprefs.cpuboard_type == BOARD_A3001_II) {
+ if (board == &gvp_ide_rom_board && ISCPUBOARD(BOARD_GVP, BOARD_GVP_SUB_A3001SII)) {
if (addr == 0x42) {
v = 0xff;
}
#if DEBUG_IDE_GVP
write_log(_T("GVP IRQ %02x\n"), v);
#endif
- ide_irq_check(board);
+ ide_interrupt_check(board);
} else if (is_gvp1_intreq(addr)) {
v = gvp_ide_controller_board.irq ? 0x80 : 0x00;
#if DEBUG_IDE_GVP
write_log(_T("GVP IRQ %02x\n"), v);
#endif
- ide_irq_check(board);
+ ide_interrupt_check(board);
}
}
} else {
} else if (board->type == GVP_IDE) {
- if (board == &gvp_ide_controller_board || currprefs.cpuboard_type == BOARD_A3001_I) {
+ if (board == &gvp_ide_controller_board || ISCPUBOARD(BOARD_GVP, BOARD_GVP_SUB_A3001SI)) {
if (addr < 0x60) {
if (is_gvp1_intreq(addr))
v = gvp_ide_controller_board.irq ? 0x8000 : 0x0000;
else if (addr == 0x40) {
- if (currprefs.cpuboard_type == BOARD_A3001_II)
+ if (ISCPUBOARD(BOARD_GVP, BOARD_GVP_SUB_A3001SII))
v = board->intena ? 8 : 0;
}
#if DEBUG_IDE_GVP
if (regnum >= 0) {
ide_write_reg(ide, regnum, v);
} else if (addr >= MASOBOSHI_SCSI_OFFSET && addr < MASOBOSHI_SCSI_OFFSET_END) {
- masoboshi_ncr9x_scsi_put(addr, v, board == &masoboshi_board[0] ? 0 : 1);
+ if (board->subtype)
+ masoboshi_ncr9x_scsi_put(addr, v, board == &masoboshi_board[0] ? 0 : 1);
} else if ((addr >= 0xf000 && addr <= 0xf007) || (addr >= 0xf04a && addr <= 0xf04f)) {
- masoboshi_ncr9x_scsi_put(addr, v, board == &masoboshi_board[0] ? 0 : 1);
+ if (board->subtype)
+ masoboshi_ncr9x_scsi_put(addr, v, board == &masoboshi_board[0] ? 0 : 1);
} else if (addr >= 0xf040 && addr < 0xf048) {
masoboshi_ncr9x_scsi_put(addr, v, board == &masoboshi_board[0] ? 0 : 1);
if (addr == 0xf047) {
}
} else if (board->type == GVP_IDE) {
- if (board == &gvp_ide_rom_board && currprefs.cpuboard_type == BOARD_A3001_II) {
+ if (board == &gvp_ide_rom_board && ISCPUBOARD(BOARD_GVP, BOARD_GVP_SUB_A3001SII)) {
#if DEBUG_IDE_GVP
write_log(_T("GVP BOOT PUT %08x %02x %08x\n"), addr, v, M68K_GETPC);
#endif
} else if (board->type == GVP_IDE) {
- if (board == &gvp_ide_controller_board || currprefs.cpuboard_type == BOARD_A3001_I) {
+ if (board == &gvp_ide_controller_board || ISCPUBOARD(BOARD_GVP, BOARD_GVP_SUB_A3001SI)) {
if (addr < 0x60) {
#if DEBUG_IDE_GVP
write_log(_T("GVP IO WORD WRITE %08x %04x %08x\n"), addr, v, M68K_GETPC);
#endif
- if (addr == 0x40 && currprefs.cpuboard_type == BOARD_A3001_II)
+ if (addr == 0x40 && ISCPUBOARD(BOARD_GVP, BOARD_GVP_SUB_A3001SII))
board->intena = (v & 8) != 0;
} else {
struct ide_hdf *ide;
struct romlist *rl;
const uae_u8 *autoconfig;
- if (currprefs.cpuboard_type == BOARD_A3001_I) {
+ if (ISCPUBOARD(BOARD_GVP, BOARD_GVP_SUB_A3001SI)) {
ide->bank = &gvp_ide_rom_bank;
autoconfig = gvp_ide1_controller_autoconfig;
init_ide(ide, GVP_IDE, true);
ide->type = MASOBOSHI_IDE + devnum;
ide->rom_size = 65536;
ide->mask = 65536 - 1;
+ ide->subtype = 0;
ide->rom = xcalloc(uae_u8, ide->rom_size);
memset(ide->rom, 0xff, ide->rom_size);
}
zfile_fclose(z);
rc = get_device_romconfig(&currprefs, devnum, ROMTYPE_MASOBOSHI);
+ ide->subtype = rc->subtype;
if (rc && rc->autoboot_disabled)
memcpy(ide->acmemory, ide->rom + 0x100, sizeof ide->acmemory);
else
return ide->bank;
}
-int masoboshi_add_ide_unit(int ch, struct uaedev_config_info *ci)
+static int masoboshi_add_ide_unit(int ch, struct uaedev_config_info *ci)
{
struct ide_hdf *ide;
return 0;
return 1;
}
+
+int masoboshi_add_idescsi_unit (int ch, struct uaedev_config_info *ci)
+{
+ if (ci->controller_type < HD_CONTROLLER_TYPE_SCSI_FIRST)
+ return masoboshi_add_ide_unit(ch, ci);
+ else
+ return masoboshi_add_scsi_unit(ch, ci);
+}
int wd33c93_ver;// 0 or 1
};
+#define COMMODORE_8727 0
#define COMMODORE_DMAC 1
#define COMMODORE_SDMAC 2
#define GVP_DMAC_S2 3
int xt_datalen;
uae_u8 xt_cmd[6];
uae_u8 xt_statusbyte;
+
+ uae_u8 c8727_pcss;
+ uae_u8 c8727_ctl;
};
struct gvp_dmac
{
uae_u16 bank;
int dma_on;
uae_u8 version;
+ bool use_version;
uae_u32 addr_mask;
bool series2;
+ int s1_subtype;
+ int s1_ramoffset;
+ int s1_rammask;
uae_u8 *buffer;
int bufoffset;
};
bool autoconfig;
uae_u8 dmacmemory[100];
uae_u8 *rom;
+ int board_mask;
int rombankswitcher, rombank;
int rom_size, rom_mask;
-
+ addrbank *bank;
smp_comm_pipe requests;
volatile int scsi_thread_running;
extern void scsi_dmac_a2091_start_dma (struct wd_state*);
extern void scsi_dmac_a2091_stop_dma (struct wd_state*);
+extern addrbank *a2090_init (int devnum);
+
extern addrbank *a2091_init (int devnum);
extern void a2091_free(void);
extern void a2091_reset (void);
#define WD33C93 _T("WD33C93")
+extern int a2090_add_scsi_unit(int ch, struct uaedev_config_info *ci);
extern int a2091_add_scsi_unit(int ch, struct uaedev_config_info *ci);
extern int gvp_add_scsi_unit(int ch, struct uaedev_config_info *ci);
extern int a3000_add_scsi_unit(int ch, struct uaedev_config_info *ci);
typedef addrbank*(*DEVICE_INIT)(int);
typedef int(*DEVICE_ADD)(int, struct uaedev_config_info*);
+typedef bool(*E8ACCESS)(int, uae_u32*, int, bool);
#define EXPANSIONTYPE_SCSI 1
#define EXPANSIONTYPE_IDE 2
+struct expansionsubromtype
+{
+ const TCHAR *name;
+ const TCHAR *configname;
+ int memory_mid, memory_pid;
+ uae_u32 memory_serial;
+ uae_u8 autoconfig[16];
+};
struct expansionromtype
{
const TCHAR *name;
DEVICE_INIT init;
DEVICE_ADD add;
int romtype;
+ int romtype_extra;
int parentromtype;
int zorro;
+ const struct expansionsubromtype *subtypes;
+ int defaultsubtype;
bool autoboot_jumper;
int deviceflags;
int memory_mid, memory_pid;
uae_u32 memory_serial;
+ uae_u8 autoconfig[16];
};
extern const struct expansionromtype expansionroms[];
+struct cpuboardsettings
+{
+ const TCHAR *name;
+ const TCHAR *configname;
+};
+struct cpuboardsubtype
+{
+ const TCHAR *name;
+ const TCHAR *configname;
+ int romtype, romtype_extra;
+ DEVICE_ADD add;
+ int deviceflags;
+ int memorytype;
+ int maxmemory;
+ int z3extra;
+ DEVICE_INIT init, init2;
+ int initzorro;
+ int initflag;
+ const struct cpuboardsettings *settings;
+ E8ACCESS e8;
+};
+struct cpuboardtype
+{
+ const TCHAR *name;
+ const struct cpuboardsubtype *subtypes;
+ int defaultsubtype;
+};
+extern const struct cpuboardtype cpuboards[];
extern bool cpuboard_32bit(struct uae_prefs *p);
extern bool cpuboard_jitdirectompatible(struct uae_prefs *p);
extern bool is_ppc_cpu(struct uae_prefs *);
-extern void cpuboard_io_special_write(uaecptr addr, uae_u32 val);
+extern bool cpuboard_io_special(int addr, uae_u32 *val, int size, bool write);
extern void cpuboard_overlay_override(void);
extern bool ppc_interrupt(int new_m68k_ipl);
#define BOARD_MEMORY_BLIZZARD_PPC 5
#define BOARD_MEMORY_25BITMEM 6
-#define BOARD_BLIZZARD_1230_IV 1
-#define BOARD_BLIZZARD_1260 2
-#define BOARD_BLIZZARD_2060 3
-#define BOARD_CSMK1 4
-#define BOARD_CSMK2 5
-#define BOARD_CSMK3 6
-#define BOARD_CSPPC 7
-#define BOARD_BLIZZARDPPC 8
-#define BOARD_WARPENGINE_A4000 9
-#define BOARD_TEKMAGIC 10
-#define BOARD_A2630 11
-#define BOARD_DKB1200 12
-#define BOARD_FUSIONFORTY 13
-#define BOARD_A3001_I 14
-#define BOARD_A3001_II 15
-#define BOARD_APOLLO 16
-#define BOARD_GVP_A530 17
-#define BOARD_GVP_GFORCE_030 18
+#define ISCPUBOARD(type,subtype) (currprefs.cpuboard_type == type && currprefs.cpuboard_subtype == subtype)
+
+#define BOARD_BLIZZARD 1
+#define BOARD_BLIZZARD_SUB_1230IV 0
+#define BOARD_BLIZZARD_SUB_1260 1
+#define BOARD_BLIZZARD_SUB_2060 2
+#define BOARD_BLIZZARD_SUB_PPC 3
+#define BOARD_CYBERSTORM 2
+#define BOARD_CYBERSTORM_SUB_MK1 0
+#define BOARD_CYBERSTORM_SUB_MK2 1
+#define BOARD_CYBERSTORM_SUB_MK3 2
+#define BOARD_CYBERSTORM_SUB_PPC 3
+#define BOARD_MACROSYSTEM 3
+#define BOARD_MACROSYSTEM_SUB_WARPENGINE_A4000 0
+#define BOARD_COMMODORE 4
+#define BOARD_COMMODORE_SUB_A26x0 0
+#define BOARD_DKB 5
+#define BOARD_DKB_SUB_12x0 0
+#define BOARD_RCS 6
+#define BOARD_RCS_SUB_FUSIONFORTY 0
+#define BOARD_ACT 7
+#define BOARD_ACT_SUB_APOLLO 0
+#define BOARD_GVP 8
+#define BOARD_GVP_SUB_A3001SI 0
+#define BOARD_GVP_SUB_A3001SII 1
+#define BOARD_GVP_SUB_A530 2
+#define BOARD_GVP_SUB_GFORCE030 3
+#define BOARD_GVP_SUB_TEKMAGIC 4
struct uaedev_config_info delayedci;
int reinsertdelay;
bool isreinsert;
+ bool unit_stopped;
};
#define HFD_FLAGS_REALDRIVE 1
int state;
int type;
int userdata;
+ int subtype;
};
struct ide_hdf
void ide_put_data (struct ide_hdf *ide, uae_u16 v);
uae_u16 ide_get_data (struct ide_hdf *ide);
-bool ide_interrupt_check(struct ide_hdf *ide);
+bool ide_interrupt_hsync(struct ide_hdf *ide);
+bool ide_irq_check(struct ide_hdf *ide);
bool ide_drq_check(struct ide_hdf *ide);
bool ide_isdrive(struct ide_hdf *ide);
void ide_initialize(struct ide_hdf **idetable, int chpair);
addrbank *apollo_init(int devnum);
addrbank *apollo_init_cpu(int devnum);
-int masoboshi_add_ide_unit(int ch, struct uaedev_config_info *ci);
+int masoboshi_add_idescsi_unit (int ch, struct uaedev_config_info *ci);
addrbank *masoboshi_init(int devnum);
uae_u32 REGPARAM3 apollo_ide_lget (uaecptr addr) REGPARAM;
extern int fpp_movem_next[256];
#endif
+extern int bus_error_offset;
+
typedef uae_u32 REGPARAM3 cpuop_func (uae_u32) REGPARAM;
typedef void REGPARAM3 cpuop_func_ce (uae_u32) REGPARAM;
extern bool fpu_get_constant(fpdata *fp, int cr);
extern int fpp_cond(int condition);
-extern void exception3 (uae_u32 opcode, uaecptr addr);
+extern void exception3_read(uae_u32 opcode, uaecptr addr);
+extern void exception3_write(uae_u32 opcode, uaecptr addr);
extern void exception3i (uae_u32 opcode, uaecptr addr);
extern void exception3b (uae_u32 opcode, uaecptr addr, bool w, bool i, uaecptr pc);
extern void exception2 (uaecptr addr, bool read, int size, uae_u32 fc);
int gfx_filter_filtermode;
int gfx_filter_bilinear;
int gfx_filter_noise, gfx_filter_blur;
- int gfx_filter_saturation, gfx_filter_luminance, gfx_filter_contrast, gfx_filter_gamma;
+ int gfx_filter_saturation, gfx_filter_luminance, gfx_filter_contrast;
+ int gfx_filter_gamma, gfx_filter_gamma_ch[3];
int gfx_filter_keep_aspect, gfx_filter_aspect;
int gfx_filter_autoscale;
int gfx_filter_keep_autoscale_aspect;
TCHAR romident[256];
uae_u32 board_ram_size;
bool autoboot_disabled;
+ int subtype;
};
#define MAX_BOARD_ROMS 2
struct boardromconfig
int gfx_xcenter_pos, gfx_ycenter_pos;
int gfx_xcenter_size, gfx_ycenter_size;
int gfx_max_horizontal, gfx_max_vertical;
- int gfx_saturation, gfx_luminance, gfx_contrast, gfx_gamma;
+ int gfx_saturation, gfx_luminance, gfx_contrast, gfx_gamma, gfx_gamma_ch[3];
bool gfx_blackerthanblack;
int gfx_api;
int color_mode;
uae_u32 mem25bit_size;
uae_u32 rtgmem_size;
int cpuboard_type;
+ int cpuboard_subtype;
+ int cpuboard_settings;
uae_u32 cpuboardmem1_size;
uae_u32 cpuboardmem2_size;
int ppc_implementation;
#define ROMTYPE_CD32CART 0x00008000
#define ROMTYPE_SPECIALKICK 0x00010000
#define ROMTYPE_PIV 0x00020000
+
#define ROMTYPE_CPUBOARD 0x00040000
+#define ROMTYPE_CB_A3001S1 0x00040001
+#define ROMTYPE_CB_APOLLO 0x00040002
+#define ROMTYPE_CB_FUSION 0x00040003
+#define ROMTYPE_CB_DKB12x0 0x00040004
+#define ROMTYPE_CB_WENGINE 0x00040005
+#define ROMTYPE_CB_TEKMAGIC 0x00040006
+#define ROMTYPE_CB_BLIZ1230 0x00040007
+#define ROMTYPE_CB_BLIZ1260 0x00040008
+#define ROMTYPE_CB_BLIZ2060 0x00040009
+#define ROMTYPE_CB_A26x0 0x0004000a
+#define ROMTYPE_CB_CSMK1 0x0004000b
+#define ROMTYPE_CB_CSMK2 0x0004000c
+#define ROMTYPE_CB_CSMK3 0x0004000d
+#define ROMTYPE_CB_CSPPC 0x0004000e
+#define ROMTYPE_CB_BLIZPPC 0x0004000f
#define ROMTYPE_FREEZER 0x00080000
#define ROMTYPE_AR 0x00080001
#define ROMTYPE_FASTLANE 0x00100004
#define ROMTYPE_OKTAGON 0x00100005
#define ROMTYPE_GVPS1 0x00100006
-#define ROMTYPE_GVPS2 0x00100007
-#define ROMTYPE_AMAX 0x00100008
-#define ROMTYPE_ALFA 0x00100009
-#define ROMTYPE_ALFAPLUS 0x0010000a
-#define ROMTYPE_APOLLO 0x0010000b
-#define ROMTYPE_MASOBOSHI 0x0010000c
-#define ROMTYPE_SUPRA 0x0010000d
+#define ROMTYPE_GVPS12 0x00100007
+#define ROMTYPE_GVPS2 0x00100008
+#define ROMTYPE_AMAX 0x00100009
+#define ROMTYPE_ALFA 0x0010000a
+#define ROMTYPE_ALFAPLUS 0x0010000b
+#define ROMTYPE_APOLLO 0x0010000c
+#define ROMTYPE_MASOBOSHI 0x0010000d
+#define ROMTYPE_SUPRA 0x0010000e
+#define ROMTYPE_A2090 0x0010000f
#define ROMTYPE_QUAD 0x01000000
#define ROMTYPE_EVEN 0x02000000
const struct expansionromtype *get_unit_expansion_rom(int hdunit);
struct boardromconfig *get_device_rom_new(struct uae_prefs *p, int romtype, int *index);
void clear_device_rom(struct uae_prefs *p, int romtype);
+struct boardromconfig *get_boardromconfig(struct uae_prefs *p, int romtype, int *index);
uae_u8 *scsi_data, int *data_len, uae_u8 *r, int *reply_len, uae_u8 *s, int *sense_len);
extern int scsi_tape_emulate(struct scsi_data_tape *sd, uae_u8 *cmdbuf, int scsi_cmd_len,
uae_u8 *scsi_data, int *data_len, uae_u8 *r, int *reply_len, uae_u8 *s, int *sense_len);
-extern void scsi_emulate_analyze (struct scsi_data*);
+extern bool scsi_emulate_analyze (struct scsi_data*);
extern bool tape_get_info (int, struct device_info*);
extern struct scsi_data_tape *tape_alloc (int unitnum, const TCHAR *tape_directory, bool readonly);
if (p->cpu_frequency == 1000000)
p->cpu_frequency = 0;
- if (p->cpu_model >= 68020 && p->cpuboard_type && cpuboard_32bit(p)) {
+ if (p->cpu_model >= 68020 && p->cpuboard_type && p->address_space_24 && cpuboard_32bit(p)) {
error_log (_T("24-bit address space is not supported with selected accelerator board configuration."));
p->address_space_24 = 0;
}
// 1 = "automatic" PPC config
if (p->ppc_mode == 1) {
- p->cpuboard_type = BOARD_CSPPC;
+ p->cpuboard_type = BOARD_CYBERSTORM;
+ p->cpuboard_subtype = BOARD_CYBERSTORM_SUB_PPC;
if (p->cs_compatible == CP_A1200) {
- p->cpuboard_type = BOARD_BLIZZARDPPC;
+ p->cpuboard_type = BOARD_BLIZZARD;
+ p->cpuboard_subtype = BOARD_BLIZZARD_SUB_PPC;
} else if (p->cs_compatible != CP_A4000 && p->cs_compatible != CP_A4000T && p->cs_compatible != CP_A3000 && p->cs_compatible != CP_A3000T) {
- if ((p->cs_ide == IDE_A600A1200 || p->cs_pcmcia) && p->cs_mbdmac <= 0)
- p->cpuboard_type = BOARD_BLIZZARDPPC;
+ if ((p->cs_ide == IDE_A600A1200 || p->cs_pcmcia) && p->cs_mbdmac <= 0) {
+ p->cpuboard_type = BOARD_BLIZZARD;
+ p->cpuboard_subtype = BOARD_BLIZZARD_SUB_PPC;
+ }
}
if (p->cpuboardmem1_size < 8 * 1024 * 1024)
p->cpuboardmem1_size = 8 * 1024 * 1024;
static void set_irq2_masoboshi(struct ncr9x_state *ncr)
{
- if (!ncr->intena || !ncr->chipirq)
- ncr->boardirq = false;
if (ncr->chipirq && ncr->intena) {
ncr->boardirq = true;
ncr9x_rethink();
if (val & 0x80)
ncr->states[8] = 0x80;
}
- write_log(_T("MASOBOSHI DMA %08x = %02X %08x\n"), addr, val, M68K_GETPC);
+ //write_log(_T("MASOBOSHI DMA %08x = %02X %08x\n"), addr, val, M68K_GETPC);
return;
}
set_irq2_masoboshi(ncr);
}
if (addr == 0xf007) {
- ncr->intena = true;
+ ncr->intena = (val & 8) != 0;
ncr9x_rethink();
}
#if 0
esp_dma_enable(ncr->devobject.lsistate, 1);
return;
}
- } else if (currprefs.cpuboard_type == BOARD_BLIZZARD_2060) {
+ } else if (currprefs.cpuboard_type == BOARD_BLIZZARD && currprefs.cpuboard_subtype == BOARD_BLIZZARD_SUB_2060) {
if (addr >= BLIZZARD_2060_DMA_OFFSET) {
//write_log (_T("Blizzard DMA PUT %08x %02X\n"), addr, (uae_u8)val);
addr &= 0xf;
ncr->led = val;
return;
}
- } else if (currprefs.cpuboard_type == BOARD_BLIZZARD_1230_IV || currprefs.cpuboard_type == BOARD_BLIZZARD_1260) {
+ } else if (currprefs.cpuboard_type == BOARD_BLIZZARD && (currprefs.cpuboard_subtype == BOARD_BLIZZARD_SUB_1230IV || currprefs.cpuboard_subtype == BOARD_BLIZZARD_SUB_1260)) {
if (!cfgfile_board_enabled(&currprefs, ROMTYPE_CPUBOARDEXT))
return;
if (addr >= BLIZZARD_SCSI_KIT_DMA_OFFSET) {
//write_log(_T("Blizzard DMA PUT %08x %02X\n"), addr, (uae_u8)val);
return;
}
- } else if (currprefs.cpuboard_type == BOARD_CSMK1) {
+ } else if (currprefs.cpuboard_type == BOARD_CYBERSTORM && currprefs.cpuboard_subtype == BOARD_CYBERSTORM_SUB_MK1) {
if (addr >= CYBERSTORM_MK1_JUMPER_OFFSET) {
if (addr == CYBERSTORM_MK1_JUMPER_OFFSET)
esp_dma_enable(ncr->devobject.lsistate, 1);
ncr->led = val;
return;
}
- } else if (currprefs.cpuboard_type == BOARD_CSMK2) {
+ } else if (currprefs.cpuboard_type == BOARD_CYBERSTORM && currprefs.cpuboard_subtype == BOARD_CYBERSTORM_SUB_MK2) {
if (addr >= CYBERSTORM_MK2_DMA_OFFSET) {
addr &= 0xf;
addr >>= 2;
ncr->led = val;
return;
}
- } else if (currprefs.cpuboard_type == BOARD_DKB1200) {
+ } else if (ISCPUBOARD(BOARD_DKB, BOARD_DKB_SUB_12x0)) {
if (addr == 0x10100) {
ncr->states[0] = val;
esp_dma_enable(ncr->devobject.lsistate, 1);
int idx = addr - 0xf000;
if (addr == 0xf000) {
ncr->states[0] &= ~3;
- if (esp_dreq(&ncr->devobject)) {
- write_log(_T("DREQ\n"));
- ncr->states[0] |= 2; // dma data waiting
+ //ncr->states[0] |= 1;
+// if (esp_dreq(&ncr->devobject)) {
+// write_log(_T("DREQ\n"));
+// ncr->states[0] |= 2; // dma data waiting
+// }
+ if (ncr->boardirq || ncr->chipirq) {
+ ncr->states[0] |= 2; // scsi interrupt
}
if (ncr->chipirq) {
- ncr->states[0] |= 1; // scsi interrupt
+ ncr->states[0] |= 1;
}
}
v = ncr->states[idx];
}
return 0;
}
- } else if (currprefs.cpuboard_type == BOARD_BLIZZARD_2060) {
+ } else if (currprefs.cpuboard_type == BOARD_BLIZZARD && currprefs.cpuboard_subtype == BOARD_BLIZZARD_SUB_2060) {
if (addr >= BLIZZARD_2060_DMA_OFFSET) {
write_log(_T("Blizzard DMA GET %08x\n"), addr);
return 0;
} else if (addr >= BLIZZARD_2060_LED_OFFSET) {
return ncr->led;
}
- } else if (currprefs.cpuboard_type == BOARD_BLIZZARD_1230_IV || currprefs.cpuboard_type == BOARD_BLIZZARD_1260) {
+ } else if (currprefs.cpuboard_type == BOARD_BLIZZARD && (currprefs.cpuboard_subtype == BOARD_BLIZZARD_SUB_1230IV || currprefs.cpuboard_subtype == BOARD_BLIZZARD_SUB_1260)) {
if (!cfgfile_board_enabled(&currprefs, ROMTYPE_CPUBOARDEXT))
return 0;
if (addr >= BLIZZARD_SCSI_KIT_DMA_OFFSET)
return 0;
- } else if (currprefs.cpuboard_type == BOARD_CSMK1) {
+ } else if (currprefs.cpuboard_type == BOARD_CYBERSTORM && currprefs.cpuboard_subtype == BOARD_CYBERSTORM_SUB_MK1) {
if (addr >= CYBERSTORM_MK1_JUMPER_OFFSET) {
return 0xff;
} else if (addr >= CYBERSTORM_MK1_DMA_OFFSET) {
} else if (addr >= CYBERSTORM_MK1_LED_OFFSET) {
return ncr->led;
}
- } else if (currprefs.cpuboard_type == BOARD_CSMK2) {
+ } else if (currprefs.cpuboard_type == BOARD_CYBERSTORM && currprefs.cpuboard_subtype == BOARD_CYBERSTORM_SUB_MK2) {
if (addr >= CYBERSTORM_MK2_DMA_OFFSET) {
return 0;
} else if (addr >= CYBERSTORM_MK2_LED_OFFSET) {
return ncr->led;
}
- } else if (currprefs.cpuboard_type == BOARD_DKB1200) {
+ } else if (ISCPUBOARD(BOARD_DKB, BOARD_DKB_SUB_12x0)) {
if (addr == 0x10100) {
uae_u8 v = 0;
- if (ncr->chipirq)
+ if (ncr->chipirq || ncr->boardirq)
v |= 0x40;
if (ncr->fakedma_data_offset < ncr->fakedma_data_size)
v |= 0x80;
+ ncr->boardirq = false;
//write_log(_T("DKB IO GET %02x %08x\n"), v, M68K_GETPC);
return v;
}
static void ncr9x_reset_board(struct ncr9x_state *ncr)
{
ncr->configured = 0;
- if (currprefs.cpuboard_type == BOARD_CSMK1)
+ if (currprefs.cpuboard_type == BOARD_CYBERSTORM && currprefs.cpuboard_subtype == BOARD_CYBERSTORM_SUB_MK1)
ncr->board_mask = 0xffff;
else
ncr->board_mask = 0x1ffff;
void ncr9x_init(void)
{
if (!ncr_blizzard_scsi.devobject.lsistate) {
- if (currprefs.cpuboard_type == BOARD_CSMK2 || currprefs.cpuboard_type == BOARD_CSMK1)
+ if (currprefs.cpuboard_type == BOARD_CYBERSTORM && (currprefs.cpuboard_subtype == BOARD_CYBERSTORM_SUB_MK1 || currprefs.cpuboard_subtype == BOARD_CYBERSTORM_SUB_MK2)) {
esp_scsi_init(&ncr_blizzard_scsi.devobject, cyberstorm_mk1_mk2_dma_read, cyberstorm_mk1_mk2_dma_write);
- else
+ } else {
esp_scsi_init(&ncr_blizzard_scsi.devobject, blizzard_dma_read, blizzard_dma_write);
+ }
esp_scsi_init(&ncr_fastlane_scsi[0].devobject, fastlane_dma_read, fastlane_dma_write);
esp_scsi_init(&ncr_fastlane_scsi[1].devobject, fastlane_dma_read, fastlane_dma_write);
esp_scsi_init(&ncr_oktagon2008_scsi[0].devobject, fake2_dma_read, fake2_dma_write);
ncr_a4000t.configured = -1;
ncr_a4000t.enabled = true;
}
- if (currprefs.cpuboard_type == BOARD_BLIZZARDPPC) {
+ if (ISCPUBOARD(BOARD_BLIZZARD, BOARD_BLIZZARD_SUB_PPC)) {
ncr_bppc.configured = -1;
ncr_bppc.enabled = true;
}
static int last_instructionaccess_for_exception_3;
int mmu_enabled, mmu_triggered;
int cpu_cycles;
+int bus_error_offset;
static int baseclock;
int m68k_pc_indirect;
bool m68k_interrupt_delay;
x_put_word (m68k_areg (regs, 7) + 0, mode);
x_put_word (m68k_areg (regs, 7) + 2, last_fault_for_exception_3 >> 16);
x_do_cycles (2 * cpucycleunit);
- write_log (_T("Exception %d (%x) at %x -> %x!\n"), nr, last_addr_for_exception_3, currpc, get_long_debug (4 * nr));
+ write_log (_T("Exception %d (%04x %x) at %x -> %x!\n"),
+ nr, last_op_for_exception_3, last_addr_for_exception_3, currpc, get_long_debug (4 * nr));
goto kludge_me_do;
}
if (currprefs.cpu_model == 68010) {
if (nr == 2 || nr == 3)
cpu_halt (2);
else
- exception3 (regs.ir, newpc);
+ exception3_read(regs.ir, newpc);
return;
}
m68k_setpc (newpc);
if (nr == 2 || nr == 3)
cpu_halt (2);
else
- exception3 (regs.ir, newpc);
+ exception3_read(regs.ir, newpc);
return;
}
m68k_setpci (newpc);
if (nr == 2 || nr == 3)
cpu_halt (2);
else
- exception3 (regs.ir, newpc);
+ exception3_read(regs.ir, newpc);
return;
}
m68k_setpci (newpc);
if (nr == 2 || nr == 3)
cpu_halt (2);
else
- exception3 (regs.ir, newpc);
+ exception3_read(regs.ir, newpc);
return;
}
m68k_setpc (newpc);
// 68000 address error
uae_u16 mode = (sv ? 4 : 0) | (last_instructionaccess_for_exception_3 ? 2 : 1);
mode |= last_writeaccess_for_exception_3 ? 0 : 16;
+ // undocumented bits seem to contain opcode
+ mode |= last_op_for_exception_3 & ~31;
m68k_areg (regs, 7) -= 14;
/* fixme: bit3=I/N */
x_put_word (m68k_areg (regs, 7) + 0, mode);
if (nr == 2 || nr == 3)
cpu_halt (2);
else
- exception3 (regs.ir, newpc);
+ exception3_write(regs.ir, newpc);
return;
}
m68k_setpc (newpc);
{
struct regstruct *r = ®s;
-retry:
- TRY (prb) {
- for (;;) {
- uae_u16 opcode = r->ir;
-
- count_instr (opcode);
-
- #if DEBUG_CD32CDTVIO
- out_cd32io (m68k_getpc ());
- #endif
-
- #if 0
- int pc = m68k_getpc ();
- if (pc == 0xdff002)
- write_log (_T("hip\n"));
- if (pc != pcs[0] && (pc < 0xd00000 || pc > 0x1000000)) {
- memmove (pcs + 1, pcs, 998 * 4);
- pcs[0] = pc;
- //write_log (_T("%08X-%04X "), pc, opcode);
- }
- #endif
- do_cycles (cpu_cycles);
- r->instruction_pc = m68k_getpc ();
- cpu_cycles = (*cpufunctbl[opcode])(opcode);
- cpu_cycles = adjust_cycles (cpu_cycles);
- if (r->spcflags) {
- if (do_specialties (cpu_cycles)) {
- regs.ipl = regs.ipl_pin;
- return;
+ for (;;) {
+ TRY (prb) {
+ for (;;) {
+ r->opcode = r->ir;
+
+ count_instr (r->opcode);
+
+#if DEBUG_CD32CDTVIO
+ out_cd32io (m68k_getpc ());
+#endif
+
+#if 0
+ int pc = m68k_getpc ();
+ if (pc == 0xdff002)
+ write_log (_T("hip\n"));
+ if (pc != pcs[0] && (pc < 0xd00000 || pc > 0x1000000)) {
+ memmove (pcs + 1, pcs, 998 * 4);
+ pcs[0] = pc;
+ //write_log (_T("%08X-%04X "), pc, r->opcode);
+ }
+#endif
+ do_cycles (cpu_cycles);
+ r->instruction_pc = m68k_getpc ();
+ cpu_cycles = (*cpufunctbl[r->opcode])(r->opcode);
+ cpu_cycles = adjust_cycles (cpu_cycles);
+ if (r->spcflags) {
+ if (do_specialties (cpu_cycles)) {
+ regs.ipl = regs.ipl_pin;
+ return;
+ }
}
+ regs.ipl = regs.ipl_pin;
+ if (!currprefs.cpu_compatible || (currprefs.cpu_cycle_exact && currprefs.cpu_model <= 68000))
+ return;
}
- regs.ipl = regs.ipl_pin;
- if (!currprefs.cpu_compatible || (currprefs.cpu_cycle_exact && currprefs.cpu_model <= 68000))
- return;
- }
- } CATCH (prb) {
- bus_error();
- goto retry;
- } ENDTRY
+ } CATCH (prb) {
+ bus_error();
+ } ENDTRY
+ }
}
#endif /* CPUEMU_11 */
struct regstruct *r = ®s;
bool first = true;
-retry:
- TRY (prb) {
- if (first) {
- if (cpu_tracer < 0) {
- memcpy (&r->regs, &cputrace.regs, 16 * sizeof (uae_u32));
- r->ir = cputrace.ir;
- r->irc = cputrace.irc;
- r->sr = cputrace.sr;
- r->usp = cputrace.usp;
- r->isp = cputrace.isp;
- r->intmask = cputrace.intmask;
- r->stopped = cputrace.stopped;
- m68k_setpc (cputrace.pc);
- if (!r->stopped) {
- if (cputrace.state > 1) {
- write_log (_T("CPU TRACE: EXCEPTION %d\n"), cputrace.state);
- Exception (cputrace.state);
- } else if (cputrace.state == 1) {
- write_log (_T("CPU TRACE: %04X\n"), cputrace.opcode);
- (*cpufunctbl[cputrace.opcode])(cputrace.opcode);
+ for(;;) {
+ TRY (prb) {
+ if (first) {
+ if (cpu_tracer < 0) {
+ memcpy (&r->regs, &cputrace.regs, 16 * sizeof (uae_u32));
+ r->ir = cputrace.ir;
+ r->irc = cputrace.irc;
+ r->sr = cputrace.sr;
+ r->usp = cputrace.usp;
+ r->isp = cputrace.isp;
+ r->intmask = cputrace.intmask;
+ r->stopped = cputrace.stopped;
+ m68k_setpc (cputrace.pc);
+ if (!r->stopped) {
+ if (cputrace.state > 1) {
+ write_log (_T("CPU TRACE: EXCEPTION %d\n"), cputrace.state);
+ Exception (cputrace.state);
+ } else if (cputrace.state == 1) {
+ write_log (_T("CPU TRACE: %04X\n"), cputrace.opcode);
+ (*cpufunctbl[cputrace.opcode])(cputrace.opcode);
+ }
+ } else {
+ write_log (_T("CPU TRACE: STOPPED\n"));
}
- } else {
- write_log (_T("CPU TRACE: STOPPED\n"));
+ if (r->stopped)
+ set_special (SPCFLAG_STOP);
+ set_cpu_tracer (false);
+ goto cont;
}
- if (r->stopped)
- set_special (SPCFLAG_STOP);
set_cpu_tracer (false);
- goto cont;
- }
- set_cpu_tracer (false);
- first = false;
- }
-
- for (;;) {
- r->opcode = r->ir;
-
- #if DEBUG_CD32CDTVIO
- out_cd32io (m68k_getpc ());
- #endif
- if (cpu_tracer) {
- memcpy (&cputrace.regs, &r->regs, 16 * sizeof (uae_u32));
- cputrace.opcode = r->opcode;
- cputrace.ir = r->ir;
- cputrace.irc = r->irc;
- cputrace.sr = r->sr;
- cputrace.usp = r->usp;
- cputrace.isp = r->isp;
- cputrace.intmask = r->intmask;
- cputrace.stopped = r->stopped;
- cputrace.state = 1;
- cputrace.pc = m68k_getpc ();
- cputrace.startcycles = get_cycles ();
- cputrace.memoryoffset = 0;
- cputrace.cyclecounter = cputrace.cyclecounter_pre = cputrace.cyclecounter_post = 0;
- cputrace.readcounter = cputrace.writecounter = 0;
+ first = false;
}
- if (inputrecord_debug & 4) {
- if (input_record > 0)
- inprec_recorddebug_cpu (1);
- else if (input_play > 0)
- inprec_playdebug_cpu (1);
- }
+ for (;;) {
+ r->opcode = r->ir;
- r->instruction_pc = m68k_getpc ();
- (*cpufunctbl[r->opcode])(r->opcode);
- wait_memory_cycles();
- if (cpu_tracer) {
- cputrace.state = 0;
- }
+#if DEBUG_CD32CDTVIO
+ out_cd32io (m68k_getpc ());
+#endif
+ if (cpu_tracer) {
+ memcpy (&cputrace.regs, &r->regs, 16 * sizeof (uae_u32));
+ cputrace.opcode = r->opcode;
+ cputrace.ir = r->ir;
+ cputrace.irc = r->irc;
+ cputrace.sr = r->sr;
+ cputrace.usp = r->usp;
+ cputrace.isp = r->isp;
+ cputrace.intmask = r->intmask;
+ cputrace.stopped = r->stopped;
+ cputrace.state = 1;
+ cputrace.pc = m68k_getpc ();
+ cputrace.startcycles = get_cycles ();
+ cputrace.memoryoffset = 0;
+ cputrace.cyclecounter = cputrace.cyclecounter_pre = cputrace.cyclecounter_post = 0;
+ cputrace.readcounter = cputrace.writecounter = 0;
+ }
+
+ if (inputrecord_debug & 4) {
+ if (input_record > 0)
+ inprec_recorddebug_cpu (1);
+ else if (input_play > 0)
+ inprec_playdebug_cpu (1);
+ }
+
+ r->instruction_pc = m68k_getpc ();
+ (*cpufunctbl[r->opcode])(r->opcode);
+ wait_memory_cycles();
+ if (cpu_tracer) {
+ cputrace.state = 0;
+ }
cont:
- if (cputrace.needendcycles) {
- cputrace.needendcycles = 0;
- write_log (_T("STARTCYCLES=%08x ENDCYCLES=%08lx\n"), cputrace.startcycles, get_cycles ());
- log_dma_record ();
- }
+ if (cputrace.needendcycles) {
+ cputrace.needendcycles = 0;
+ write_log (_T("STARTCYCLES=%08x ENDCYCLES=%08lx\n"), cputrace.startcycles, get_cycles ());
+ log_dma_record ();
+ }
- if (r->spcflags || time_for_interrupt ()) {
- if (do_specialties (0))
+ if (r->spcflags || time_for_interrupt ()) {
+ if (do_specialties (0))
+ return;
+ }
+
+ if (!currprefs.cpu_cycle_exact || currprefs.cpu_model > 68000)
return;
}
-
- if (!currprefs.cpu_cycle_exact || currprefs.cpu_model > 68000)
- return;
- }
- } CATCH (prb) {
- bus_error();
- goto retry;
- } ENDTRY
+ } CATCH (prb) {
+ bus_error();
+ } ENDTRY
+ }
}
#endif
{
uaecptr pc;
struct flag_struct f;
+ int halt = 0;
-retry:
- TRY (prb) {
- for (;;) {
- f.cznv = regflags.cznv;
- f.x = regflags.x;
- pc = regs.instruction_pc = m68k_getpc ();
+ while (!halt) {
+ TRY (prb) {
+ for (;;) {
+ f.cznv = regflags.cznv;
+ f.x = regflags.x;
+ pc = regs.instruction_pc = m68k_getpc ();
- do_cycles (cpu_cycles);
+ do_cycles (cpu_cycles);
- mmu_opcode = -1;
- mmu060_state = 0;
- mmu_opcode = regs.opcode = x_prefetch (0);
- mmu060_state = 1;
+ mmu_opcode = -1;
+ mmu060_state = 0;
+ mmu_opcode = regs.opcode = x_prefetch (0);
+ mmu060_state = 1;
- count_instr (regs.opcode);
- cpu_cycles = (*cpufunctbl[regs.opcode])(regs.opcode);
+ count_instr (regs.opcode);
+ cpu_cycles = (*cpufunctbl[regs.opcode])(regs.opcode);
- cpu_cycles = adjust_cycles (cpu_cycles);
+ cpu_cycles = adjust_cycles (cpu_cycles);
- if (regs.spcflags) {
- if (do_specialties (cpu_cycles))
- return;
+ if (regs.spcflags) {
+ if (do_specialties (cpu_cycles))
+ return;
+ }
}
- }
- } CATCH (prb) {
-
- m68k_setpci (regs.instruction_pc);
- regflags.cznv = f.cznv;
- regflags.x = f.x;
+ } CATCH (prb) {
+ m68k_setpci (regs.instruction_pc);
+ regflags.cznv = f.cznv;
+ regflags.x = f.x;
- if (mmufixup[0].reg >= 0) {
- m68k_areg (regs, mmufixup[0].reg) = mmufixup[0].value;
- mmufixup[0].reg = -1;
- }
- if (mmufixup[1].reg >= 0) {
- m68k_areg (regs, mmufixup[1].reg) = mmufixup[1].value;
- mmufixup[1].reg = -1;
- }
+ if (mmufixup[0].reg >= 0) {
+ m68k_areg (regs, mmufixup[0].reg) = mmufixup[0].value;
+ mmufixup[0].reg = -1;
+ }
+ if (mmufixup[1].reg >= 0) {
+ m68k_areg (regs, mmufixup[1].reg) = mmufixup[1].value;
+ mmufixup[1].reg = -1;
+ }
- TRY (prb2) {
- Exception (prb);
- } CATCH (prb2) {
- cpu_halt (1);
- return;
+ TRY (prb2) {
+ Exception (prb);
+ } CATCH (prb2) {
+ halt = 1;
+ } ENDTRY
} ENDTRY
- goto retry;
- } ENDTRY
-
+ }
+ cpu_halt(halt);
}
#endif
{
flag_struct f;
uaecptr pc;
+ int halt = 0;
-retry:
- TRY (prb) {
- for (;;) {
- f.cznv = regflags.cznv;
- f.x = regflags.x;
- mmu_restart = true;
- pc = regs.instruction_pc = m68k_getpc ();
+ while (!halt) {
+ TRY (prb) {
+ for (;;) {
+ f.cznv = regflags.cznv;
+ f.x = regflags.x;
+ mmu_restart = true;
+ pc = regs.instruction_pc = m68k_getpc ();
- do_cycles (cpu_cycles);
+ do_cycles (cpu_cycles);
- mmu_opcode = -1;
- mmu_opcode = regs.opcode = x_prefetch (0);
- count_instr (regs.opcode);
- cpu_cycles = (*cpufunctbl[regs.opcode])(regs.opcode);
- cpu_cycles = adjust_cycles (cpu_cycles);
+ mmu_opcode = -1;
+ mmu_opcode = regs.opcode = x_prefetch (0);
+ count_instr (regs.opcode);
+ cpu_cycles = (*cpufunctbl[regs.opcode])(regs.opcode);
+ cpu_cycles = adjust_cycles (cpu_cycles);
- if (regs.spcflags) {
- if (do_specialties (cpu_cycles))
- return;
+ if (regs.spcflags) {
+ if (do_specialties (cpu_cycles))
+ return;
+ }
}
- }
- } CATCH (prb) {
+ } CATCH (prb) {
- if (mmu_restart) {
- /* restore state if instruction restart */
- regflags.cznv = f.cznv;
- regflags.x = f.x;
- m68k_setpci (regs.instruction_pc);
- }
+ if (mmu_restart) {
+ /* restore state if instruction restart */
+ regflags.cznv = f.cznv;
+ regflags.x = f.x;
+ m68k_setpci (regs.instruction_pc);
+ }
- if (mmufixup[0].reg >= 0) {
- m68k_areg (regs, mmufixup[0].reg) = mmufixup[0].value;
- mmufixup[0].reg = -1;
- }
+ if (mmufixup[0].reg >= 0) {
+ m68k_areg (regs, mmufixup[0].reg) = mmufixup[0].value;
+ mmufixup[0].reg = -1;
+ }
- TRY (prb2) {
- Exception (prb);
- } CATCH (prb2) {
- cpu_halt (1);
- return;
+ TRY (prb2) {
+ Exception (prb);
+ } CATCH (prb2) {
+ halt = 1;
+ } ENDTRY
} ENDTRY
- goto retry;
- } ENDTRY
-
+ }
+ cpu_halt(halt);
}
#endif
{
uaecptr pc;
struct flag_struct f;
+ int halt = 0;
mmu030_opcode_stageb = -1;
mmu030_fake_prefetch = -1;
-retry:
- TRY (prb) {
- for (;;) {
- int cnt;
+ while(!halt) {
+ TRY (prb) {
+ for (;;) {
+ int cnt;
insretry:
- pc = regs.instruction_pc = m68k_getpc ();
- f.cznv = regflags.cznv;
- f.x = regflags.x;
-
- mmu030_state[0] = mmu030_state[1] = mmu030_state[2] = 0;
- mmu030_opcode = -1;
- if (mmu030_fake_prefetch >= 0) {
- regs.opcode = mmu030_fake_prefetch;
- mmu030_fake_prefetch = -1;
- } else if (mmu030_opcode_stageb < 0) {
- regs.opcode = x_prefetch (0);
- } else {
- regs.opcode = mmu030_opcode_stageb;
- mmu030_opcode_stageb = -1;
- }
-
- mmu030_opcode = regs.opcode;
- mmu030_ad[0].done = false;
+ pc = regs.instruction_pc = m68k_getpc ();
+ f.cznv = regflags.cznv;
+ f.x = regflags.x;
+
+ mmu030_state[0] = mmu030_state[1] = mmu030_state[2] = 0;
+ mmu030_opcode = -1;
+ if (mmu030_fake_prefetch >= 0) {
+ regs.opcode = mmu030_fake_prefetch;
+ mmu030_fake_prefetch = -1;
+ } else if (mmu030_opcode_stageb < 0) {
+ regs.opcode = x_prefetch (0);
+ } else {
+ regs.opcode = mmu030_opcode_stageb;
+ mmu030_opcode_stageb = -1;
+ }
- cnt = 50;
- for (;;) {
- regs.opcode = mmu030_opcode;
- mmu030_idx = 0;
- count_instr (regs.opcode);
- do_cycles (cpu_cycles);
- mmu030_retry = false;
+ mmu030_opcode = regs.opcode;
+ mmu030_ad[0].done = false;
- cpu_cycles = (*cpufunctbl[regs.opcode])(regs.opcode);
- cnt--; // so that we don't get in infinite loop if things go horribly wrong
- if (!mmu030_retry)
- break;
- if (cnt < 0) {
- cpu_halt (9);
- break;
+ cnt = 50;
+ for (;;) {
+ regs.opcode = mmu030_opcode;
+ mmu030_idx = 0;
+ count_instr (regs.opcode);
+ do_cycles (cpu_cycles);
+ mmu030_retry = false;
+
+ cpu_cycles = (*cpufunctbl[regs.opcode])(regs.opcode);
+ cnt--; // so that we don't get in infinite loop if things go horribly wrong
+ if (!mmu030_retry)
+ break;
+ if (cnt < 0) {
+ cpu_halt (9);
+ break;
+ }
+ if (mmu030_retry && mmu030_opcode == -1)
+ goto insretry; // urgh
}
- if (mmu030_retry && mmu030_opcode == -1)
- goto insretry; // urgh
- }
- mmu030_opcode = -1;
+ mmu030_opcode = -1;
- cpu_cycles = adjust_cycles (cpu_cycles);
- if (regs.spcflags) {
- if (do_specialties (cpu_cycles))
- return;
+ cpu_cycles = adjust_cycles (cpu_cycles);
+ if (regs.spcflags) {
+ if (do_specialties (cpu_cycles))
+ return;
+ }
}
- }
- } CATCH (prb) {
+ } CATCH (prb) {
- regflags.cznv = f.cznv;
- regflags.x = f.x;
+ regflags.cznv = f.cznv;
+ regflags.x = f.x;
- m68k_setpci (regs.instruction_pc);
+ m68k_setpci (regs.instruction_pc);
- if (mmufixup[0].reg >= 0) {
- m68k_areg (regs, mmufixup[0].reg) = mmufixup[0].value;
- mmufixup[0].reg = -1;
- }
- if (mmufixup[1].reg >= 0) {
- m68k_areg (regs, mmufixup[1].reg) = mmufixup[1].value;
- mmufixup[1].reg = -1;
- }
+ if (mmufixup[0].reg >= 0) {
+ m68k_areg (regs, mmufixup[0].reg) = mmufixup[0].value;
+ mmufixup[0].reg = -1;
+ }
+ if (mmufixup[1].reg >= 0) {
+ m68k_areg (regs, mmufixup[1].reg) = mmufixup[1].value;
+ mmufixup[1].reg = -1;
+ }
- TRY (prb2) {
- Exception (prb);
- } CATCH (prb2) {
- cpu_halt (1);
- return;
+ TRY (prb2) {
+ Exception (prb);
+ } CATCH (prb2) {
+ halt = 1;
+ } ENDTRY
} ENDTRY
- goto retry;
- } ENDTRY
-
+ }
+ cpu_halt (halt);
}
#endif
struct regstruct *r = ®s;
bool exit = false;
-retry:
- TRY(prb) {
- for (;;) {
- r->instruction_pc = m68k_getpc();
- r->opcode = get_iword_cache_040(0);
- // "prefetch"
- if (regs.cacr & 0x8000)
- fill_icache040(r->instruction_pc + 16);
-
- (*cpufunctbl[r->opcode])(r->opcode);
-
- if (r->spcflags) {
- if (do_specialties (0))
- exit = true;
- }
+ for(;;) {
+ TRY(prb) {
+ for (;;) {
+ r->instruction_pc = m68k_getpc();
+ r->opcode = get_iword_cache_040(0);
+ // "prefetch"
+ if (regs.cacr & 0x8000)
+ fill_icache040(r->instruction_pc + 16);
- if (exit)
- return;
- }
- } CATCH(prb) {
- bus_error();
- goto retry;
- } ENDTRY
+ (*cpufunctbl[r->opcode])(r->opcode);
+
+ if (r->spcflags) {
+ if (do_specialties (0))
+ exit = true;
+ }
+
+ if (exit)
+ return;
+ }
+ } CATCH(prb) {
+ bus_error();
+ } ENDTRY
+ }
}
/* "prefetch" 68040/060 */
bool exit = false;
int cycles;
-retry:
- TRY(prb) {
- for (;;) {
- r->instruction_pc = m68k_getpc();
- r->opcode = get_iword_cache_040(0);
- // "prefetch"
- if (regs.cacr & 0x8000)
- fill_icache040(r->instruction_pc + 16);
-
- (*cpufunctbl[r->opcode])(r->opcode);
-
- cpu_cycles = 1 * CYCLE_UNIT;
- cycles = adjust_cycles(cpu_cycles);
- do_cycles(cycles);
-
- if (r->spcflags) {
- if (do_specialties(0))
- exit = true;
- }
+ for(;;) {
+ TRY(prb) {
+ for (;;) {
+ r->instruction_pc = m68k_getpc();
+ r->opcode = get_iword_cache_040(0);
+ // "prefetch"
+ if (regs.cacr & 0x8000)
+ fill_icache040(r->instruction_pc + 16);
- if (exit)
- return;
- }
- } CATCH(prb) {
- bus_error();
- goto retry;
- } ENDTRY
+ (*cpufunctbl[r->opcode])(r->opcode);
+
+ cpu_cycles = 1 * CYCLE_UNIT;
+ cycles = adjust_cycles(cpu_cycles);
+ do_cycles(cycles);
+
+ if (r->spcflags) {
+ if (do_specialties(0))
+ exit = true;
+ }
+
+ if (exit)
+ return;
+ }
+ } CATCH(prb) {
+ bus_error();
+ } ENDTRY
+ }
}
/* "cycle exact" 68020/030 */
bool exit = false;
bool first = true;
-retry:
- TRY(prb) {
- if (first) {
- if (cpu_tracer < 0) {
- memcpy (&r->regs, &cputrace.regs, 16 * sizeof (uae_u32));
- r->ir = cputrace.ir;
- r->irc = cputrace.irc;
- r->sr = cputrace.sr;
- r->usp = cputrace.usp;
- r->isp = cputrace.isp;
- r->intmask = cputrace.intmask;
- r->stopped = cputrace.stopped;
-
- r->msp = cputrace.msp;
- r->vbr = cputrace.vbr;
- r->caar = cputrace.caar;
- r->cacr = cputrace.cacr;
- r->cacheholdingdata020 = cputrace.cacheholdingdata020;
- r->cacheholdingaddr020 = cputrace.cacheholdingaddr020;
- r->prefetch020addr = cputrace.prefetch020addr;
- memcpy (&r->prefetch020, &cputrace.prefetch020, CPU_PIPELINE_MAX * sizeof (uae_u32));
- memcpy (&caches020, &cputrace.caches020, sizeof caches020);
-
- m68k_setpc (cputrace.pc);
- if (!r->stopped) {
- if (cputrace.state > 1)
- Exception (cputrace.state);
- else if (cputrace.state == 1)
- (*cpufunctbl[cputrace.opcode])(cputrace.opcode);
+ for(;;) {
+ TRY(prb) {
+ if (first) {
+ if (cpu_tracer < 0) {
+ memcpy (&r->regs, &cputrace.regs, 16 * sizeof (uae_u32));
+ r->ir = cputrace.ir;
+ r->irc = cputrace.irc;
+ r->sr = cputrace.sr;
+ r->usp = cputrace.usp;
+ r->isp = cputrace.isp;
+ r->intmask = cputrace.intmask;
+ r->stopped = cputrace.stopped;
+
+ r->msp = cputrace.msp;
+ r->vbr = cputrace.vbr;
+ r->caar = cputrace.caar;
+ r->cacr = cputrace.cacr;
+ r->cacheholdingdata020 = cputrace.cacheholdingdata020;
+ r->cacheholdingaddr020 = cputrace.cacheholdingaddr020;
+ r->prefetch020addr = cputrace.prefetch020addr;
+ memcpy (&r->prefetch020, &cputrace.prefetch020, CPU_PIPELINE_MAX * sizeof (uae_u32));
+ memcpy (&caches020, &cputrace.caches020, sizeof caches020);
+
+ m68k_setpc (cputrace.pc);
+ if (!r->stopped) {
+ if (cputrace.state > 1)
+ Exception (cputrace.state);
+ else if (cputrace.state == 1)
+ (*cpufunctbl[cputrace.opcode])(cputrace.opcode);
+ }
+ if (regs.stopped)
+ set_special (SPCFLAG_STOP);
+ set_cpu_tracer (false);
+ goto cont;
}
- if (regs.stopped)
- set_special (SPCFLAG_STOP);
set_cpu_tracer (false);
- goto cont;
+ first = false;
}
- set_cpu_tracer (false);
- first = false;
- }
- for (;;) {
- static int prevopcode;
- r->instruction_pc = m68k_getpc ();
+ for (;;) {
+ static int prevopcode;
+ r->instruction_pc = m68k_getpc ();
- if (regs.irc == 0xfffb) {
- gui_message (_T("OPCODE %04X HAS FAULTY PREFETCH! PC=%08X"), prevopcode, r->instruction_pc);
- }
+ if (regs.irc == 0xfffb) {
+ gui_message (_T("OPCODE %04X HAS FAULTY PREFETCH! PC=%08X"), prevopcode, r->instruction_pc);
+ }
- //write_log (_T("%x %04x\n"), r->instruction_pc, regs.irc);
-
- r->opcode = regs.irc;
- prevopcode = r->opcode;
- regs.irc = 0xfffb;
-
- //write_log (_T("%08x %04x\n"), r->instruction_pc, opcode);
-
- #if DEBUG_CD32CDTVIO
- out_cd32io (r->instruction_pc);
- #endif
-
- if (cpu_tracer) {
-
- #if CPUTRACE_DEBUG
- validate_trace ();
- #endif
- memcpy (&cputrace.regs, &r->regs, 16 * sizeof (uae_u32));
- cputrace.opcode = r->opcode;
- cputrace.ir = r->ir;
- cputrace.irc = r->irc;
- cputrace.sr = r->sr;
- cputrace.usp = r->usp;
- cputrace.isp = r->isp;
- cputrace.intmask = r->intmask;
- cputrace.stopped = r->stopped;
- cputrace.state = 1;
- cputrace.pc = m68k_getpc ();
-
- cputrace.msp = r->msp;
- cputrace.vbr = r->vbr;
- cputrace.caar = r->caar;
- cputrace.cacr = r->cacr;
- cputrace.cacheholdingdata020 = r->cacheholdingdata020;
- cputrace.cacheholdingaddr020 = r->cacheholdingaddr020;
- cputrace.prefetch020addr = r->prefetch020addr;
- memcpy (&cputrace.prefetch020, &r->prefetch020, CPU_PIPELINE_MAX * sizeof (uae_u32));
- memcpy (&cputrace.caches020, &caches020, sizeof caches020);
-
- cputrace.memoryoffset = 0;
- cputrace.cyclecounter = cputrace.cyclecounter_pre = cputrace.cyclecounter_post = 0;
- cputrace.readcounter = cputrace.writecounter = 0;
- }
+ //write_log (_T("%x %04x\n"), r->instruction_pc, regs.irc);
- if (inputrecord_debug & 4) {
- if (input_record > 0)
- inprec_recorddebug_cpu (1);
- else if (input_play > 0)
- inprec_playdebug_cpu (1);
- }
+ r->opcode = regs.irc;
+ prevopcode = r->opcode;
+ regs.irc = 0xfffb;
- (*cpufunctbl[r->opcode])(r->opcode);
+ //write_log (_T("%08x %04x\n"), r->instruction_pc, opcode);
+
+#if DEBUG_CD32CDTVIO
+ out_cd32io (r->instruction_pc);
+#endif
+
+ if (cpu_tracer) {
+
+#if CPUTRACE_DEBUG
+ validate_trace ();
+#endif
+ memcpy (&cputrace.regs, &r->regs, 16 * sizeof (uae_u32));
+ cputrace.opcode = r->opcode;
+ cputrace.ir = r->ir;
+ cputrace.irc = r->irc;
+ cputrace.sr = r->sr;
+ cputrace.usp = r->usp;
+ cputrace.isp = r->isp;
+ cputrace.intmask = r->intmask;
+ cputrace.stopped = r->stopped;
+ cputrace.state = 1;
+ cputrace.pc = m68k_getpc ();
+
+ cputrace.msp = r->msp;
+ cputrace.vbr = r->vbr;
+ cputrace.caar = r->caar;
+ cputrace.cacr = r->cacr;
+ cputrace.cacheholdingdata020 = r->cacheholdingdata020;
+ cputrace.cacheholdingaddr020 = r->cacheholdingaddr020;
+ cputrace.prefetch020addr = r->prefetch020addr;
+ memcpy (&cputrace.prefetch020, &r->prefetch020, CPU_PIPELINE_MAX * sizeof (uae_u32));
+ memcpy (&cputrace.caches020, &caches020, sizeof caches020);
+
+ cputrace.memoryoffset = 0;
+ cputrace.cyclecounter = cputrace.cyclecounter_pre = cputrace.cyclecounter_post = 0;
+ cputrace.readcounter = cputrace.writecounter = 0;
+ }
+
+ if (inputrecord_debug & 4) {
+ if (input_record > 0)
+ inprec_recorddebug_cpu (1);
+ else if (input_play > 0)
+ inprec_playdebug_cpu (1);
+ }
+
+ (*cpufunctbl[r->opcode])(r->opcode);
- wait_memory_cycles();
+ wait_memory_cycles();
- cont:
- if (r->spcflags || time_for_interrupt ()) {
- if (do_specialties (0))
- exit = true;
- }
+ cont:
+ if (r->spcflags || time_for_interrupt ()) {
+ if (do_specialties (0))
+ exit = true;
+ }
- regs.ipl = regs.ipl_pin;
+ regs.ipl = regs.ipl_pin;
- if (exit)
- return;
- }
- } CATCH(prb) {
- bus_error();
- goto retry;
- } ENDTRY
+ if (exit)
+ return;
+ }
+ } CATCH(prb) {
+ bus_error();
+ } ENDTRY
+ }
}
#ifdef CPUEMU_20
{
struct regstruct *r = ®s;
-retry:
- TRY(prb) {
- for (;;) {
- r->instruction_pc = m68k_getpc ();
+ for(;;) {
+ TRY(prb) {
+ for (;;) {
+ r->instruction_pc = m68k_getpc ();
- #if DEBUG_CD32CDTVIO
- out_cd32io (m68k_getpc ());
- #endif
+ #if DEBUG_CD32CDTVIO
+ out_cd32io (m68k_getpc ());
+ #endif
- x_do_cycles (cpu_cycles);
+ x_do_cycles (cpu_cycles);
- r->opcode = regs.irc;
- count_instr (r->opcode);
+ r->opcode = regs.irc;
+ count_instr (r->opcode);
- cpu_cycles = (*cpufunctbl[r->opcode])(r->opcode);
- cpu_cycles = adjust_cycles (cpu_cycles);
- if (r->spcflags) {
- if (do_specialties (cpu_cycles)) {
- ipl_fetch ();
- return;
+ cpu_cycles = (*cpufunctbl[r->opcode])(r->opcode);
+ cpu_cycles = adjust_cycles (cpu_cycles);
+ if (r->spcflags) {
+ if (do_specialties (cpu_cycles)) {
+ ipl_fetch ();
+ return;
+ }
}
+ ipl_fetch ();
}
- ipl_fetch ();
- }
- } CATCH(prb) {
- bus_error();
- goto retry;
- } ENDTRY
+ } CATCH(prb) {
+ bus_error();
+ } ENDTRY
+ }
}
#endif
// static int done;
struct regstruct *r = ®s;
-retry:
- TRY(prb) {
- for (;;) {
- r->instruction_pc = m68k_getpc ();
+ for(;;) {
+ TRY(prb) {
+ for (;;) {
+ r->instruction_pc = m68k_getpc ();
- r->opcode = x_get_iword(0);
- count_instr (r->opcode);
+ r->opcode = x_get_iword(0);
+ count_instr (r->opcode);
- do_cycles (cpu_cycles);
+ do_cycles (cpu_cycles);
- cpu_cycles = (*cpufunctbl[r->opcode])(r->opcode);
- cpu_cycles = adjust_cycles (cpu_cycles);
+ cpu_cycles = (*cpufunctbl[r->opcode])(r->opcode);
+ cpu_cycles = adjust_cycles (cpu_cycles);
- if (r->spcflags) {
- if (do_specialties (cpu_cycles)) {
- break;
+ if (r->spcflags) {
+ if (do_specialties (cpu_cycles)) {
+ return;
+ }
}
}
- }
- } CATCH(prb) {
- bus_error();
- goto retry;
- } ENDTRY
+ } CATCH(prb) {
+ bus_error();
+ } ENDTRY
+ }
}
/* fake MMU 68k */
#endif /* SAVESTATE */
-static void exception3f (uae_u32 opcode, uaecptr addr, int writeaccess, int instructionaccess, uaecptr pc)
+static void exception3f (uae_u32 opcode, uaecptr addr, int writeaccess, int instructionaccess, uaecptr pc, bool plus2)
{
if (currprefs.cpu_model >= 68040)
addr &= ~1;
else
last_addr_for_exception_3 = pc;
} else if (pc == 0xffffffff) {
- last_addr_for_exception_3 = m68k_getpc () + 2;
+ last_addr_for_exception_3 = m68k_getpc ();
+ if (plus2)
+ last_addr_for_exception_3 += 2;
} else {
last_addr_for_exception_3 = pc;
}
#endif
}
-void exception3 (uae_u32 opcode, uaecptr addr)
+void exception3_read(uae_u32 opcode, uaecptr addr)
+{
+ exception3f (opcode, addr, false, 0, 0xffffffff, false);
+}
+void exception3_write(uae_u32 opcode, uaecptr addr)
{
- exception3f (opcode, addr, 0, 0, 0xffffffff);
+ exception3f (opcode, addr, true, 0, 0xffffffff, false);
}
void exception3i (uae_u32 opcode, uaecptr addr)
{
- exception3f (opcode, addr, 0, 1, 0xffffffff);
+ exception3f (opcode, addr, 0, 1, 0xffffffff, true);
}
void exception3b (uae_u32 opcode, uaecptr addr, bool w, bool i, uaecptr pc)
{
- exception3f (opcode, addr, w, i, pc);
+ exception3f (opcode, addr, w, i, pc, true);
}
void exception2 (uaecptr addr, bool read, int size, uae_u32 fc)
mmu_bus_error (addr, fc, read == false, size, false, 0);
}
} else {
+ last_addr_for_exception_3 = m68k_getpc() + bus_error_offset;
last_fault_for_exception_3 = addr;
last_writeaccess_for_exception_3 = read == 0;
last_instructionaccess_for_exception_3 = (fc & 1) == 0;
if (1 && natmem_size > 0x40000000 && natmem_size - 0x40000000 >= (totalsize - 0x10000000 - ((changed_prefs.z3chipmem_size + align) & ~align)) && changed_prefs.z3chipmem_size <= 512 * 1024 * 1024) {
changed_prefs.z3autoconfig_start = currprefs.z3autoconfig_start = Z3BASE_REAL;
z3offset += Z3BASE_REAL - Z3BASE_UAE - ((changed_prefs.z3chipmem_size + align) & ~align);
- if (currprefs.cpuboard_type == BOARD_WARPENGINE_A4000)
- z3offset += 0x01000000;
+ z3offset += cpuboards[currprefs.cpuboard_type].subtypes[currprefs.cpuboard_subtype].z3extra;
set_expamem_z3_hack_override(true);
startbarrier = 0;
write_log(_T("Z3 REAL mapping. JIT direct compatible.\n"));
} else {
// calculate Z3 alignment (argh, I thought only Z2 needed this..)
uae_u32 addr = Z3BASE_REAL;
- if (currprefs.cpuboard_type == BOARD_WARPENGINE_A4000) {
- addr = expansion_startaddress(addr, 0x01000000);
- addr += 0x01000000;
+ int z3off = cpuboards[currprefs.cpuboard_type].subtypes[currprefs.cpuboard_subtype].z3extra;
+ if (z3off) {
+ addr = expansion_startaddress(addr, z3off);
+ addr += z3off;
}
addr = expansion_startaddress(addr, changed_prefs.z3fastmem_size);
addr += changed_prefs.z3fastmem_size;
#define IDC_SCSIROMSELECT 1391
#define IDC_KICKCHOOSER 1392
#define IDC_KEYCHOOSER 1393
+#define IDC_SCSIROMSUBSELECT 1393
#define IDC_ROMFILE2 1394
#define IDC_ROMCHOOSER2 1395
#define IDC_FLASHCHOOSER 1396
#define IDC_CARTFILE 1398
#define IDC_CARTCHOOSER 1399
#define IDC_SAVE 1400
+#define IDC_CPUBOARDROMSUBSELECT 1400
#define IDC_LOAD 1401
#define IDC_RTCCHOOSER 1401
#define IDC_SCSIROMCHOOSER 1402
#define IDC_EDITPATH 1410
#define IDC_RTCFILE 1411
#define IDC_SCSIROMFILE 1412
+#define IDC_SCSIROMFILE2 1413
#define IDC_CPUBOARDROMFILE 1414
#define IDC_HDF_RDB 1500
#define IDC_HFSIZE 1501
#define IDC_CD_SELECT 1807
#define IDC_FASTMEMAUTOCONFIG 1808
#define IDC_RTG_DISPLAYSELECT 1809
+#define IDC_CPUBOARD_SETTING1 1809
#define IDC_MISCLIST 1810
+#define IDC_CPUBOARD_SETTING2 1810
#define IDC_STATENAME 1811
#define IDC_SAMPLER_STEREO 1812
#define IDC_LISTDIALOG_LIST 1813
#define IDC_TAPE_SELECT_FILE 1833
#define IDC_TAPE_RW 1834
#define IDC_ERRORLOGMESSAGE 1835
+#define IDC_TAPE_SELECT_FILE2 1835
+#define IDC_TAPE_EJECT 1835
#define IDC_ERRORLOGCLEAR 1836
#define IDC_DISKINFOBOX 1837
#define IDC_SAVEBOOTBLOCK 1838
#define IDC_CPUBOARD_TYPE 1842
#define IDC_CPUBOARDMEM 1843
#define IDC_Z3MAPPING 1844
+#define IDC_CPUBOARD_SUBTYPE 1845
#define ID__FLOPPYDRIVES 40004
#define ID_FLOPPYDRIVES_DF0 40005
#define ID_ST_CONFIGURATION 40010
// Dialog
//
-IDD_KICKSTART DIALOGEX 0, 0, 396, 279
+IDD_KICKSTART DIALOGEX 0, 0, 396, 289
STYLE DS_LOCALEDIT | DS_SETFONT | DS_3DLOOK | DS_CONTROL | WS_CHILD
EXSTYLE WS_EX_CONTEXTHELP
FONT 8, "MS Sans Serif", 0, 0, 0x1
"Button",BS_AUTOCHECKBOX | WS_TABSTOP,87,77,104,12
CONTROL "ShapeShifter support [] Patches the system ROM for ShapeShifter compatibility.",IDC_KICKSHIFTER,
"Button",BS_AUTOCHECKBOX | WS_TABSTOP,195,77,106,13
- GROUPBOX "Miscellaneous",IDC_STATIC,1,98,394,177
+ GROUPBOX "Miscellaneous",IDC_STATIC,1,100,394,188
LTEXT "Cartridge ROM file:",IDC_FLASHTEXT2,12,112,265,10
COMBOBOX IDC_CARTFILE,12,125,361,75,CBS_DROPDOWN | CBS_AUTOHSCROLL | CBS_SORT | WS_VSCROLL | WS_TABSTOP
PUSHBUTTON "...",IDC_CARTCHOOSER,376,124,10,15
LTEXT "Real Time Clock file",IDC_STATIC,12,174,313,15,SS_CENTERIMAGE
EDITTEXT IDC_RTCFILE,12,191,361,12,ES_AUTOHSCROLL
PUSHBUTTON "...",IDC_RTCCHOOSER,376,189,10,15
- COMBOBOX IDC_SCSIROMSELECT,12,223,171,75,CBS_DROPDOWNLIST | CBS_AUTOHSCROLL | WS_VSCROLL | WS_TABSTOP
- LTEXT "SCSI/Boot ROM file:",IDC_STATIC,12,207,170,15,SS_CENTERIMAGE
- COMBOBOX IDC_SCSIROMFILE,202,223,171,75,CBS_DROPDOWN | CBS_AUTOHSCROLL | WS_VSCROLL | WS_TABSTOP
- PUSHBUTTON "...",IDC_SCSIROMCHOOSER,376,221,10,15
- LTEXT "Accelerator board ROM file:",IDC_STATIC,12,240,170,15,SS_CENTERIMAGE
- COMBOBOX IDC_CPUBOARDROMFILE,12,256,171,75,CBS_DROPDOWN | CBS_AUTOHSCROLL | WS_VSCROLL | WS_TABSTOP
- PUSHBUTTON "...",IDC_CPUBOARDROMCHOOSER,187,255,10,15
- CONTROL "Autoboot disabled",IDC_SCSIROMFILEAUTOBOOT,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,202,239,104,12
+ COMBOBOX IDC_SCSIROMSELECT,12,228,171,75,CBS_DROPDOWNLIST | CBS_AUTOHSCROLL | WS_VSCROLL | WS_TABSTOP
+ LTEXT "SCSI/Boot ROM file:",IDC_STATIC,12,212,170,15,SS_CENTERIMAGE
+ COMBOBOX IDC_SCSIROMFILE,202,228,171,75,CBS_DROPDOWN | CBS_AUTOHSCROLL | WS_VSCROLL | WS_TABSTOP
+ PUSHBUTTON "...",IDC_SCSIROMCHOOSER,376,226,10,15
+ LTEXT "Accelerator board ROM file:",IDC_STATIC,12,250,170,15,SS_CENTERIMAGE
+ COMBOBOX IDC_CPUBOARDROMFILE,12,266,171,75,CBS_DROPDOWN | CBS_AUTOHSCROLL | WS_VSCROLL | WS_TABSTOP
+ PUSHBUTTON "...",IDC_CPUBOARDROMCHOOSER,187,265,10,15
+ CONTROL "Autoboot disabled",IDC_SCSIROMFILEAUTOBOOT,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,202,213,84,12
+ COMBOBOX IDC_SCSIROMSUBSELECT,202,246,171,75,CBS_DROPDOWNLIST | CBS_AUTOHSCROLL | WS_VSCROLL | WS_TABSTOP
END
IDD_DISPLAY DIALOGEX 0, 0, 396, 298
"Button",BS_AUTOCHECKBOX | WS_TABSTOP,155,154,124,10
END
-IDD_MEMORY DIALOGEX 0, 0, 396, 290
+IDD_MEMORY DIALOGEX 0, 0, 396, 304
STYLE DS_LOCALEDIT | DS_SETFONT | DS_3DLOOK | DS_CONTROL | WS_CHILD
EXSTYLE WS_EX_CONTEXTHELP
FONT 8, "MS Sans Serif", 0, 0, 0x1
RTEXT "Z2 Fast:",IDC_STATIC,8,49,60,15,SS_CENTERIMAGE
CONTROL "Slider1",IDC_FASTMEM,"msctls_trackbar32",TBS_AUTOTICKS | TBS_TOP | WS_TABSTOP,68,47,60,20
EDITTEXT IDC_FASTRAM,135,53,40,12,ES_CENTER | ES_READONLY
- CONTROL "Autoconfig Z2 Fast RAM",IDC_FASTMEMAUTOCONFIG,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,45,220,120,10
+ CONTROL "Autoconfig Z2 Fast RAM",IDC_FASTMEMAUTOCONFIG,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,11,194,120,10
RTEXT "Slow:",IDC_STATIC,179,25,66,15,SS_CENTERIMAGE
CONTROL "Slider1",IDC_SLOWMEM,"msctls_trackbar32",TBS_AUTOTICKS | TBS_TOP | WS_TABSTOP,248,22,60,20
EDITTEXT IDC_SLOWRAM,311,25,40,12,ES_CENTER | ES_READONLY
CONTROL "",IDC_Z3CHIPMEM,"msctls_trackbar32",TBS_AUTOTICKS | TBS_TOP | WS_TABSTOP,248,71,60,20
EDITTEXT IDC_Z3CHIPRAM,311,76,40,12,ES_CENTER | ES_READONLY
EDITTEXT IDC_MAX32RAM,14,99,366,12,ES_CENTER | ES_READONLY
- GROUPBOX "Advanced Memory Settings",IDC_STATIC,0,133,393,147
+ GROUPBOX "Advanced Memory Settings",IDC_STATIC,0,133,393,164
RTEXT "Motherboard Fast:",IDC_STATIC,116,149,129,10,SS_CENTERIMAGE
CONTROL "",IDC_MBMEM1,"msctls_trackbar32",TBS_AUTOTICKS | TBS_TOP | WS_TABSTOP,251,145,68,20
EDITTEXT IDC_MBRAM1,326,148,40,12,ES_CENTER | ES_READONLY
EDITTEXT IDC_MBRAM2,326,171,40,12,ES_CENTER | ES_READONLY
CONTROL "",IDC_FASTMEM2,"msctls_trackbar32",TBS_AUTOTICKS | TBS_TOP | WS_TABSTOP,251,193,68,20
EDITTEXT IDC_FASTRAM2,326,196,40,12,ES_CENTER | ES_READONLY
- COMBOBOX IDC_CPUBOARD_TYPE,8,257,117,75,CBS_DROPDOWNLIST | WS_VSCROLL | WS_TABSTOP
+ COMBOBOX IDC_CPUBOARD_TYPE,9,255,117,75,CBS_DROPDOWNLIST | WS_VSCROLL | WS_TABSTOP
RTEXT "Second Z2 Fast RAM board:",IDC_STATIC,129,194,116,15,SS_CENTERIMAGE
- RTEXT "Accelerator board memory:",IDC_STATIC,138,257,104,15,SS_CENTERIMAGE
- CONTROL "",IDC_CPUBOARDMEM,"msctls_trackbar32",TBS_AUTOTICKS | TBS_TOP | WS_TABSTOP,251,253,68,20
- EDITTEXT IDC_CPUBOARDRAM,326,256,40,12,ES_CENTER | ES_READONLY
+ RTEXT "Accelerator board memory:",IDC_STATIC,138,250,104,15,SS_CENTERIMAGE
+ CONTROL "",IDC_CPUBOARDMEM,"msctls_trackbar32",TBS_AUTOTICKS | TBS_TOP | WS_TABSTOP,251,246,68,20
+ EDITTEXT IDC_CPUBOARDRAM,326,249,40,12,ES_CENTER | ES_READONLY
COMBOBOX IDC_Z3MAPPING,249,220,117,75,CBS_DROPDOWNLIST | WS_VSCROLL | WS_TABSTOP
RTEXT "Z3 mapping mode:",IDC_STATIC,149,220,93,15,SS_CENTERIMAGE
+ COMBOBOX IDC_CPUBOARD_SUBTYPE,9,274,117,75,CBS_DROPDOWNLIST | WS_VSCROLL | WS_TABSTOP
+ CONTROL "-",IDC_CPUBOARD_SETTING1,"Button",BS_AUTOCHECKBOX | NOT WS_VISIBLE | WS_TABSTOP,155,277,100,10
+ CONTROL "-",IDC_CPUBOARD_SETTING2,"Button",BS_AUTOCHECKBOX | NOT WS_VISIBLE | WS_TABSTOP,261,277,100,10
END
IDD_CPU DIALOGEX 0, 0, 396, 292
COMBOBOX IDC_NETDEVICE,202,256,178,65,CBS_DROPDOWNLIST | WS_VSCROLL | WS_TABSTOP
CONTROL "CD32 Full Motion Video cartridge",IDC_CS_CD32FMV,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,13,242,151,11
CONTROL "Toccata Z2 sound card emulation",IDC_CS_TOCCATA,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,13,255,151,11
- CONTROL "Toccata Paula audio mix",IDC_CS_TOCCATAMIXER,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,13,268,151,11
+ CONTROL "Toccata Paula/CD audio mix",IDC_CS_TOCCATAMIXER,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,13,267,151,11
END
IDD_INPUTMAP DIALOGEX 0, 0, 421, 341
COMBOBOX IDC_HDF_CONTROLLER_UNIT,189,89,25,150,CBS_DROPDOWNLIST | CBS_HASSTRINGS | WS_VSCROLL | WS_TABSTOP
END
-IDD_TAPEDRIVE DIALOGEX 0, 0, 395, 80
+IDD_TAPEDRIVE DIALOGEX 0, 0, 395, 97
STYLE DS_LOCALEDIT | DS_SETFONT | DS_MODALFRAME | DS_SETFOREGROUND | DS_3DLOOK | DS_CENTER | DS_CENTERMOUSE | WS_POPUP | WS_VISIBLE | WS_CAPTION | WS_SYSMENU
CAPTION "Tape Drive Settings"
FONT 8, "MS Sans Serif", 0, 0, 0x0
BEGIN
RTEXT "Path:",IDC_STATIC,4,18,43,10,SS_CENTERIMAGE
- PUSHBUTTON "Select Directory",IDC_TAPE_SELECT_DIR,19,36,123,15
- PUSHBUTTON "Select Archive or Plain File",IDC_TAPE_SELECT_FILE,160,36,123,15
- CONTROL "Read/write",IDC_TAPE_RW,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,313,39,67,10
- RTEXT "HD Controller:",IDC_STATIC,7,61,65,10,SS_CENTERIMAGE
- COMBOBOX IDC_HDF_CONTROLLER,79,59,100,150,CBS_DROPDOWNLIST | CBS_HASSTRINGS | WS_VSCROLL | WS_TABSTOP
- DEFPUSHBUTTON "Add Tape Drive",IDOK,223,58,88,14
- PUSHBUTTON "Cancel",IDCANCEL,318,58,67,14
- COMBOBOX IDC_HDF_CONTROLLER_UNIT,186,59,25,150,CBS_DROPDOWNLIST | CBS_HASSTRINGS | WS_VSCROLL | WS_TABSTOP
+ PUSHBUTTON "Select Directory",IDC_TAPE_SELECT_DIR,13,36,123,15
+ PUSHBUTTON "Select Archive or Plain File",IDC_TAPE_SELECT_FILE,146,36,123,15
+ CONTROL "Read/write",IDC_TAPE_RW,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,277,58,67,10
+ RTEXT "HD Controller:",IDC_STATIC,7,60,65,10,SS_CENTERIMAGE
+ COMBOBOX IDC_HDF_CONTROLLER,79,58,148,150,CBS_DROPDOWNLIST | CBS_HASSTRINGS | WS_VSCROLL | WS_TABSTOP
+ DEFPUSHBUTTON "Add Tape Drive",IDOK,106,75,88,14
+ PUSHBUTTON "Cancel",IDCANCEL,200,76,88,14
+ COMBOBOX IDC_HDF_CONTROLLER_UNIT,235,58,31,150,CBS_DROPDOWNLIST | CBS_HASSTRINGS | WS_VSCROLL | WS_TABSTOP
COMBOBOX IDC_PATH_NAME,52,15,332,75,CBS_DROPDOWN | CBS_AUTOHSCROLL | WS_VSCROLL | WS_TABSTOP
+ PUSHBUTTON "Eject",IDC_TAPE_EJECT,278,36,105,15
END
IDD_DISKINFO DIALOGEX 0, 0, 491, 323
BEGIN
IDD_KICKSTART, DIALOG
BEGIN
- BOTTOMMARGIN, 275
END
IDD_DISPLAY, DIALOG
IDD_MEMORY, DIALOG
BEGIN
- BOTTOMMARGIN, 287
+ BOTTOMMARGIN, 301
END
IDD_CPU, DIALOG
IDD_TAPEDRIVE, DIALOG
BEGIN
+ BOTTOMMARGIN, 80
END
IDD_DISKINFO, DIALOG
IDS_FILTER_PAL_EXTRA "Brightness\nContrast\nSaturation\nGamma\nScanlines\nBlurriness\nNoise\n"
IDS_FILTER_3D_EXTRA "Point/Bilinear\nScanline opacity\nScanline level\n"
IDS_ALWAYS_ON "Always on"
- IDS_DISPLAY_ATTRIBUTES "Brightness\nContrast\nGamma"
+ IDS_DISPLAY_ATTRIBUTES "Brightness\nContrast\nGamma\nGamma [R]\nGamma [G]\nGamma [B]"
IDS_NUMSG_NO_PPC "PPC CPU was started but PPC CPU emulation core plugin was not found. Download available from http://www.winuae.net/"
IDS_NUMSG_UAEBOOTROM_PCC
"PPC native OS booted with UAE boot ROM active. UAE expansions are not hardware emulated and are not PPC compatible. (UAE HD controller, uaescsi.device, uaeserial, bsdsocket and so on..)"
uae_u16 serper, serdat, serdatr;
-static int allowed_baudrates[] =
+static const int allowed_baudrates[] =
{ 0, 110, 300, 600, 1200, 2400, 4800, 9600, 14400,
19200, 31400, 38400, 57600, 115200, 128000, 256000, -1 };
return '.';
}
-static void checkreceive_enet (int mode)
+static void checkreceive_enet (void)
{
#ifdef SERIAL_ENET
uae_u16 recdata;
#endif
}
-static void checkreceive_serial (int mode)
+static void checkreceive_serial (void)
{
#ifdef SERIAL_PORT
static int ninebitdata;
serdatshift = serdat;
data_in_sershift = 1;
data_in_serdat = 0;
- INTREQ(0x8000 | 0x0001); // Transmit buffer empty
+ INTREQ(0x8000 | 0x0001);
+ serial_check_irq();
checksend();
if (seriallog)
return;
serial_period_hsync_counter++;
if (serial_period_hsyncs == 1 || (serial_period_hsync_counter % (serial_period_hsyncs - 1)) == 0) {
- checkreceive_serial (0);
- checkreceive_enet (0);
+ checkreceive_serial();
+ checkreceive_enet();
}
if ((serial_period_hsync_counter % serial_period_hsyncs) == 0 && !currprefs.cpu_cycle_exact) {
checksend();
void serial_check_irq (void)
{
+ // Data in receive buffer
if (data_in_serdatr)
- INTREQ_0 (0x8000 | 0x0800);
+ INTREQ(0x8000 | 0x0800);
}
void serial_dtr_on (void)
#define LANG_DLL_FULL_VERSION_MATCH 1
#if WINUAEPUBLICBETA
-#define WINUAEBETA _T("9")
+#define WINUAEBETA _T("10")
#else
#define WINUAEBETA _T("")
#endif
-#define WINUAEDATE MAKEBD(2015, 2, 9)
+#define WINUAEDATE MAKEBD(2015, 2, 21)
//#define WINUAEEXTRA _T("AmiKit Preview")
//#define WINUAEEXTRA _T("Amiga Forever Edition")
case 2:
p = &workprefs.gfx_gamma;
break;
+ case 3:
+ p = &workprefs.gfx_gamma_ch[0];
+ break;
+ case 4:
+ p = &workprefs.gfx_gamma_ch[1];
+ break;
+ case 5:
+ p = &workprefs.gfx_gamma_ch[2];
+ break;
}
return p;
}
static void update_da (HWND hDlg)
{
currprefs.gfx_gamma = workprefs.gfx_gamma;
+ currprefs.gfx_gamma_ch[0] = workprefs.gfx_gamma_ch[0];
+ currprefs.gfx_gamma_ch[1] = workprefs.gfx_gamma_ch[1];
+ currprefs.gfx_gamma_ch[2] = workprefs.gfx_gamma_ch[2];
currprefs.gfx_luminance = workprefs.gfx_luminance;
currprefs.gfx_contrast = workprefs.gfx_contrast;
set_da (hDlg);
return FALSE;
}
+static const int cpuboard_settings_id[] = { IDC_CPUBOARD_SETTING1, IDC_CPUBOARD_SETTING2, -1 };
+
static void enable_for_memorydlg (HWND hDlg)
{
int fast = true;
ew(hDlg, IDC_CPUBOARDMEM, workprefs.cpuboard_type > 0);
ew(hDlg, IDC_CPUBOARDRAM, workprefs.cpuboard_type > 0);
ew(hDlg, IDC_CPUBOARD_TYPE, workprefs.address_space_24 == false);
+ ew(hDlg, IDC_CPUBOARD_SUBTYPE, workprefs.address_space_24 == false && workprefs.cpuboard_type);
+ const struct cpuboardsettings *cbs = cpuboards[workprefs.cpuboard_type].subtypes[workprefs.cpuboard_subtype].settings;
+ for (int i = 0; cpuboard_settings_id[i] >= 0; i++) {
+ hide(hDlg, cpuboard_settings_id[i], !(workprefs.address_space_24 == false && cbs && cbs[i].name));
+ }
}
extern uae_u32 natmem_size;
SendDlgItemMessage (hDlg, IDC_CPUBOARDMEM, TBM_SETPOS, TRUE, mem_size);
SetDlgItemText (hDlg, IDC_CPUBOARDRAM, memsize_names[msi_cpuboard[mem_size]]);
SendDlgItemMessage (hDlg, IDC_CPUBOARD_TYPE, CB_SETCURSEL, workprefs.cpuboard_type, 0);
+ SendDlgItemMessage (hDlg, IDC_CPUBOARD_SUBTYPE, CB_SETCURSEL, workprefs.cpuboard_subtype, 0);
+ for (int i = 0; cpuboard_settings_id[i] >= 0; i++) {
+ setchecked(hDlg, cpuboard_settings_id[i], (workprefs.cpuboard_settings & (1 << i)) != 0);
+ }
}
static int manybits (int v, int mask)
return FALSE;
}
+static void updatecpuboardsubtypes(HWND hDlg)
+{
+ SendDlgItemMessage (hDlg, IDC_CPUBOARD_SUBTYPE, CB_RESETCONTENT, 0, 0);
+ for (int i = 0; cpuboards[workprefs.cpuboard_type].subtypes[i].name; i++) {
+ SendDlgItemMessage(hDlg, IDC_CPUBOARD_SUBTYPE, CB_ADDSTRING, 0, (LPARAM)cpuboards[workprefs.cpuboard_type].subtypes[i].name);
+ }
+ const struct cpuboardsettings *cbs = cpuboards[workprefs.cpuboard_type].subtypes[workprefs.cpuboard_subtype].settings;
+ int i = 0;
+ if (cbs) {
+ for (i = 0; cbs[i].name; i++) {
+ int id = cpuboard_settings_id[i];
+ if (id < 0)
+ break;
+ SetWindowText (GetDlgItem(hDlg, id), cbs[i].name);
+ }
+ }
+ while (cpuboard_settings_id[i] >= 0) {
+ int id = cpuboard_settings_id[i];
+ SetWindowText (GetDlgItem(hDlg, id), _T("-"));
+ i++;
+ }
+}
+
static INT_PTR CALLBACK MemoryDlgProc (HWND hDlg, UINT msg, WPARAM wParam, LPARAM lParam)
{
static int recursive = 0;
switch (msg)
{
case WM_INITDIALOG:
+ recursive++;
pages[MEMORY_ID] = hDlg;
currentpage = MEMORY_ID;
SendDlgItemMessage (hDlg, IDC_CHIPMEM, TBM_SETRANGE, TRUE, MAKELONG (MIN_CHIP_MEM, MAX_CHIP_MEM));
SendDlgItemMessage(hDlg, IDC_Z3MAPPING, CB_ADDSTRING, 0, (LPARAM)_T("Real"));
SendDlgItemMessage (hDlg, IDC_Z3MAPPING, CB_SETCURSEL, workprefs.z3_mapping_mode, 0);
SendDlgItemMessage (hDlg, IDC_CPUBOARD_TYPE, CB_RESETCONTENT, 0, 0);
- SendDlgItemMessage (hDlg, IDC_CPUBOARD_TYPE, CB_ADDSTRING, 0, (LPARAM)_T("-"));
- SendDlgItemMessage(hDlg, IDC_CPUBOARD_TYPE, CB_ADDSTRING, 0, (LPARAM)_T("Blizzard 1230 IV"));
- SendDlgItemMessage(hDlg, IDC_CPUBOARD_TYPE, CB_ADDSTRING, 0, (LPARAM)_T("Blizzard 1260"));
- SendDlgItemMessage(hDlg, IDC_CPUBOARD_TYPE, CB_ADDSTRING, 0, (LPARAM)_T("Blizzard 2060"));
- SendDlgItemMessage(hDlg, IDC_CPUBOARD_TYPE, CB_ADDSTRING, 0, (LPARAM)_T("CyberStorm MK I"));
- SendDlgItemMessage(hDlg, IDC_CPUBOARD_TYPE, CB_ADDSTRING, 0, (LPARAM)_T("CyberStorm MK II"));
- SendDlgItemMessage(hDlg, IDC_CPUBOARD_TYPE, CB_ADDSTRING, 0, (LPARAM)_T("CyberStorm MK III"));
- SendDlgItemMessage(hDlg, IDC_CPUBOARD_TYPE, CB_ADDSTRING, 0, (LPARAM)_T("CyberStorm PPC"));
- SendDlgItemMessage(hDlg, IDC_CPUBOARD_TYPE, CB_ADDSTRING, 0, (LPARAM)_T("Blizzard PPC"));
- SendDlgItemMessage(hDlg, IDC_CPUBOARD_TYPE, CB_ADDSTRING, 0, (LPARAM)_T("Warp Engine"));
- SendDlgItemMessage(hDlg, IDC_CPUBOARD_TYPE, CB_ADDSTRING, 0, (LPARAM)_T("Tek Magic"));
- SendDlgItemMessage(hDlg, IDC_CPUBOARD_TYPE, CB_ADDSTRING, 0, (LPARAM)_T("A2620/A2630"));
- SendDlgItemMessage(hDlg, IDC_CPUBOARD_TYPE, CB_ADDSTRING, 0, (LPARAM)_T("DKB 1230/1240"));
- SendDlgItemMessage(hDlg, IDC_CPUBOARD_TYPE, CB_ADDSTRING, 0, (LPARAM)_T("Fusion Forty"));
- SendDlgItemMessage(hDlg, IDC_CPUBOARD_TYPE, CB_ADDSTRING, 0, (LPARAM)_T("GVP A3001 Series I"));
- SendDlgItemMessage(hDlg, IDC_CPUBOARD_TYPE, CB_ADDSTRING, 0, (LPARAM)_T("GVP A3001 Series II"));
- SendDlgItemMessage(hDlg, IDC_CPUBOARD_TYPE, CB_ADDSTRING, 0, (LPARAM)_T("Apollo 1240/1260"));
- SendDlgItemMessage(hDlg, IDC_CPUBOARD_TYPE, CB_ADDSTRING, 0, (LPARAM)_T("GVP A530"));
- SendDlgItemMessage(hDlg, IDC_CPUBOARD_TYPE, CB_ADDSTRING, 0, (LPARAM)_T("GVP G-Force 030"));
+ for (int i = 0; cpuboards[i].name; i++) {
+ SendDlgItemMessage(hDlg, IDC_CPUBOARD_TYPE, CB_ADDSTRING, 0, (LPARAM)cpuboards[i].name);
+ }
+ updatecpuboardsubtypes(hDlg);
setcpuboardmemsize(hDlg);
+ recursive--;
case WM_USER:
- workprefs.fastmem_autoconfig = ischecked (hDlg, IDC_FASTMEMAUTOCONFIG);
+ recursive++;
fix_values_memorydlg ();
values_to_memorydlg (hDlg);
enable_for_memorydlg (hDlg);
break;
case WM_COMMAND:
- recursive++;
- if (HIWORD (wParam) == CBN_SELCHANGE || HIWORD (wParam) == CBN_KILLFOCUS) {
- switch (LOWORD (wParam))
- {
- case IDC_Z3MAPPING:
- v = SendDlgItemMessage (hDlg, IDC_Z3MAPPING, CB_GETCURSEL, 0, 0L);
- if (v != CB_ERR) {
- workprefs.z3_mapping_mode = v;
- }
- break;
- case IDC_CPUBOARD_TYPE:
- v = SendDlgItemMessage (hDlg, IDC_CPUBOARD_TYPE, CB_GETCURSEL, 0, 0L);
- if (v != CB_ERR) {
- workprefs.cpuboard_type = v;
- if (is_ppc_cpu(&workprefs)) {
- workprefs.ppc_mode = 2;
- } else if (workprefs.ppc_mode == 2) {
- workprefs.ppc_mode = 0;
+ if (!recursive) {
+ recursive++;
+ if (HIWORD (wParam) == CBN_SELCHANGE || HIWORD (wParam) == CBN_KILLFOCUS) {
+ switch (LOWORD (wParam))
+ {
+ case IDC_Z3MAPPING:
+ v = SendDlgItemMessage (hDlg, IDC_Z3MAPPING, CB_GETCURSEL, 0, 0L);
+ if (v != CB_ERR) {
+ workprefs.z3_mapping_mode = v;
+ }
+ break;
+ case IDC_CPUBOARD_TYPE:
+ v = SendDlgItemMessage (hDlg, IDC_CPUBOARD_TYPE, CB_GETCURSEL, 0, 0L);
+ if (v != CB_ERR && v != workprefs.cpuboard_type) {
+ workprefs.cpuboard_type = v;
+ workprefs.cpuboard_subtype = 0;
+ workprefs.cpuboard_settings = 0;
+ updatecpuboardsubtypes(hDlg);
+ if (is_ppc_cpu(&workprefs)) {
+ workprefs.ppc_mode = 2;
+ } else if (workprefs.ppc_mode == 2) {
+ workprefs.ppc_mode = 0;
+ }
+ built_in_cpuboard_prefs(&workprefs);
+ setcpuboardmemsize(hDlg);
+ enable_for_memorydlg(hDlg);
+ }
+ break;
+ case IDC_CPUBOARD_SUBTYPE:
+ v = SendDlgItemMessage (hDlg, IDC_CPUBOARD_SUBTYPE, CB_GETCURSEL, 0, 0L);
+ if (v != CB_ERR && v != workprefs.cpuboard_subtype) {
+ workprefs.cpuboard_subtype = v;
+ workprefs.cpuboard_settings = 0;
+ if (is_ppc_cpu(&workprefs)) {
+ workprefs.ppc_mode = 2;
+ } else if (workprefs.ppc_mode == 2) {
+ workprefs.ppc_mode = 0;
+ }
+ built_in_cpuboard_prefs(&workprefs);
+ setcpuboardmemsize(hDlg);
+ enable_for_memorydlg(hDlg);
}
- built_in_cpuboard_prefs(&workprefs);
- setcpuboardmemsize(hDlg);
- enable_for_memorydlg(hDlg);
+ break;
}
- break;
}
+ workprefs.fastmem_autoconfig = ischecked (hDlg, IDC_FASTMEMAUTOCONFIG);
+ for (int i = 0; cpuboard_settings_id[i] >= 0; i++) {
+ workprefs.cpuboard_settings &= ~(1 << i);
+ if (ischecked(hDlg, cpuboard_settings_id[i]))
+ workprefs.cpuboard_settings |= 1 << i;
+ }
+ recursive--;
}
- workprefs.fastmem_autoconfig = ischecked (hDlg, IDC_FASTMEMAUTOCONFIG);
- recursive--;
break;
case WM_HSCROLL:
}
}
+static void values_to_kickstartdlg_sub(HWND hDlg)
+{
+ SendDlgItemMessage(hDlg, IDC_CPUBOARDROMSUBSELECT, CB_RESETCONTENT, 0, 0);
+ ew(hDlg, IDC_CPUBOARDROMSUBSELECT, false);
+
+ SendDlgItemMessage(hDlg, IDC_SCSIROMSUBSELECT, CB_RESETCONTENT, 0, 0);
+ const struct expansionromtype *er = &expansionroms[scsiromselected];
+ const struct expansionsubromtype *srt = er->subtypes;
+ ew(hDlg, IDC_SCSIROMSUBSELECT, srt != NULL);
+ while (srt && srt->name) {
+ SendDlgItemMessage(hDlg, IDC_SCSIROMSUBSELECT, CB_ADDSTRING, 0, (LPARAM)srt->name);
+ srt++;
+ }
+ int index;
+ struct boardromconfig *brc = get_device_rom(&workprefs, expansionroms[scsiromselected].romtype, &index);
+ if (brc) {
+ SendDlgItemMessage (hDlg, IDC_SCSIROMSUBSELECT, CB_SETCURSEL, brc->roms[index].subtype, 0);
+ } else if (srt) {
+ SendDlgItemMessage (hDlg, IDC_SCSIROMSUBSELECT, CB_SETCURSEL, 0, 0);
+ }
+}
+
static void values_from_kickstartdlg (HWND hDlg)
{
int index;
getromfile(hDlg, IDC_SCSIROMFILE, tmp, MAX_DPATH / sizeof (TCHAR));
if (tmp[0]) {
brc = get_device_rom_new(&workprefs, expansionroms[scsiromselected].romtype, &index);
+ bool changed = _tcscmp(tmp, brc->roms[index].romfile) != 0;
getromfile(hDlg, IDC_SCSIROMFILE, brc->roms[index].romfile, MAX_DPATH / sizeof (TCHAR));
- if (ischecked(hDlg, IDC_SCSIROMFILEAUTOBOOT))
- brc->roms[index].autoboot_disabled = true;
+ brc->roms[index].autoboot_disabled = ischecked(hDlg, IDC_SCSIROMFILEAUTOBOOT);
+ int v = SendDlgItemMessage (hDlg, IDC_SCSIROMSUBSELECT, CB_GETCURSEL, 0, 0L);
+ if (v != CB_ERR)
+ brc->roms[index].subtype = v;
+ if (changed)
+ values_to_kickstartdlg_sub(hDlg);
} else {
+ brc = get_device_rom(&workprefs, expansionroms[scsiromselected].romtype, &index);
clear_device_rom(&workprefs, expansionroms[scsiromselected].romtype);
+ if (brc && brc->roms[index].romfile[0])
+ values_to_kickstartdlg_sub(hDlg);
}
getromfile(hDlg, IDC_CPUBOARDROMFILE, tmp, sizeof(brc->roms[index].romfile) / sizeof(TCHAR));
if (tmp[0]) {
brc = get_device_rom(&workprefs, expansionroms[scsiromselected].romtype, &index);
addromfiles (fkey, hDlg, IDC_SCSIROMFILE, brc ? brc->roms[index].romfile : NULL,
- expansionroms[scsiromselected].romtype, 0);
+ expansionroms[scsiromselected].romtype, expansionroms[scsiromselected].romtype_extra);
CheckDlgButton(hDlg, IDC_SCSIROMFILEAUTOBOOT, brc && brc->roms[index].autoboot_disabled);
ew(hDlg, IDC_SCSIROMFILEAUTOBOOT, expansionroms[scsiromselected].autoboot_jumper);
- brc = get_device_rom(&workprefs, ROMTYPE_CPUBOARD, &index);
- addromfiles(fkey, hDlg, IDC_CPUBOARDROMFILE, brc ? brc->roms[index].romfile : NULL,
- ROMTYPE_CPUBOARD, ROMTYPE_GVPS2);
+ if (workprefs.cpuboard_type) {
+ const struct cpuboardsubtype *cst = &cpuboards[workprefs.cpuboard_type].subtypes[workprefs.cpuboard_subtype];
+ brc = get_device_rom(&workprefs, ROMTYPE_CPUBOARD, &index);
+ addromfiles(fkey, hDlg, IDC_CPUBOARDROMFILE, brc ? brc->roms[index].romfile : NULL,
+ cst->romtype, cst->romtype_extra);
+ } else {
+ SendDlgItemMessage(hDlg, IDC_CPUBOARDROMFILE, CB_RESETCONTENT, 0, 0);
+ }
regclosetree(fkey);
CheckDlgButton(hDlg, IDC_KICKSHIFTER, workprefs.kickshifter);
CheckDlgButton(hDlg, IDC_MAPROM, workprefs.maprom);
gui_set_string_cursor(scsiromselect_table, hDlg, IDC_SCSIROMSELECT, scsiromselected);
+ values_to_kickstartdlg_sub(hDlg);
}
static void init_kickstart (HWND hDlg)
case IDC_ROMFILE2:
case IDC_CARTFILE:
case IDC_SCSIROMFILE:
+ case IDC_SCSIROMSUBSELECT:
case IDC_CPUBOARDROMFILE:
+ case IDC_CPUBOARDROMSUBSELECT:
values_from_kickstartdlg (hDlg);
break;
case IDC_SCSIROMSELECT:
expansionroms[scsiromselected].romtype, 0);
ew(hDlg, IDC_SCSIROMFILEAUTOBOOT, expansionroms[scsiromselected].autoboot_jumper);
regclosetree(fkey);
+ values_to_kickstartdlg_sub(hDlg);
}
break;
}
for (int i = 0; expansionroms[i].name; i++) {
const struct expansionromtype *erc = &expansionroms[i];
- if (erc->deviceflags & EXPANSIONTYPE_IDE)
- gui_add_string(hdmenutable, hDlg, IDC_HDF_CONTROLLER, HD_CONTROLLER_TYPE_IDE_EXPANSION_FIRST + i, erc->friendlyname);
+ if (erc->deviceflags & EXPANSIONTYPE_IDE) {
+// if (get_boardromconfig(&workprefs, erc->romtype, NULL) || get_boardromconfig(&workprefs, erc->romtype_extra, NULL)) {
+ gui_add_string(hdmenutable, hDlg, IDC_HDF_CONTROLLER, HD_CONTROLLER_TYPE_IDE_EXPANSION_FIRST + i, erc->friendlyname);
+// }
+ }
}
gui_add_string(hdmenutable, hDlg, IDC_HDF_CONTROLLER, 0, _T(""));
for (int i = 0; expansionroms[i].name; i++) {
const struct expansionromtype *erc = &expansionroms[i];
- if (erc->deviceflags & EXPANSIONTYPE_SCSI)
- gui_add_string(hdmenutable, hDlg, IDC_HDF_CONTROLLER, HD_CONTROLLER_TYPE_SCSI_EXPANSION_FIRST + i, erc->friendlyname);
+ if (erc->deviceflags & EXPANSIONTYPE_SCSI) {
+// if (get_boardromconfig(&workprefs, erc->romtype, NULL) || get_boardromconfig(&workprefs, erc->romtype_extra, NULL)) {
+ gui_add_string(hdmenutable, hDlg, IDC_HDF_CONTROLLER, HD_CONTROLLER_TYPE_SCSI_EXPANSION_FIRST + i, erc->friendlyname);
+// }
+ }
}
gui_add_string(hdmenutable, hDlg, IDC_HDF_CONTROLLER, 0, _T(""));
{
static int recursive = 0;
int posn, readonly;
+ TCHAR tmp[MAX_DPATH];
switch (msg) {
if (recursive)
break;
recursive++;
+ if (HIWORD (wParam) == CBN_SELCHANGE || HIWORD (wParam) == CBN_KILLFOCUS) {
+ switch (LOWORD (wParam))
+ {
+ case IDC_PATH_NAME:
+ GetDlgItemText (hDlg, IDC_PATH_NAME, tmp, sizeof tmp / sizeof (TCHAR));
+ if (_tcscmp (tmp, current_tapedlg.ci.rootdir)) {
+ _tcscpy (current_tapedlg.ci.rootdir, tmp);
+ readonly = my_existsfile (current_tapedlg.ci.rootdir);
+ ew (hDlg, IDC_TAPE_RW, !readonly);
+ if (readonly)
+ CheckDlgButton (hDlg, IDC_TAPE_RW, FALSE);
+ }
+ break;
+ case IDC_HDF_CONTROLLER:
+ posn = gui_get_string_cursor(hdmenutable, hDlg, IDC_HDF_CONTROLLER);
+ if (posn != CB_ERR) {
+ current_tapedlg.ci.controller_type = posn;
+ inithdcontroller(hDlg, current_tapedlg.ci.controller_type, UAEDEV_TAPE);
+ SendDlgItemMessage (hDlg, IDC_HDF_CONTROLLER_UNIT, CB_SETCURSEL, current_tapedlg.ci.controller_unit, 0);
+ }
+ break;
+ case IDC_HDF_CONTROLLER_UNIT:
+ posn = SendDlgItemMessage (hDlg, IDC_HDF_CONTROLLER_UNIT, CB_GETCURSEL, 0, 0);
+ if (posn != CB_ERR)
+ current_tapedlg.ci.controller_unit = posn;
+ break;
+ }
+ }
switch (LOWORD (wParam))
{
+ case IDC_TAPE_EJECT:
+ current_tapedlg.ci.rootdir[0] = 0;
+ SetDlgItemText(hDlg, IDC_PATH_NAME, current_tapedlg.ci.rootdir);
+ break;
case IDC_TAPE_SELECT_FILE:
DiskSelection (hDlg, IDC_PATH_NAME, 18, &workprefs, NULL);
GetDlgItemText (hDlg, IDC_PATH_NAME, current_tapedlg.ci.rootdir, sizeof current_tapedlg.ci.rootdir / sizeof (TCHAR));
case IDCANCEL:
EndDialog (hDlg, 0);
break;
- case IDC_HDF_CONTROLLER:
- posn = gui_get_string_cursor(hdmenutable, hDlg, IDC_HDF_CONTROLLER);
- if (posn != CB_ERR) {
- current_tapedlg.ci.controller_type = posn;
- inithdcontroller(hDlg, current_tapedlg.ci.controller_type, UAEDEV_TAPE);
- SendDlgItemMessage (hDlg, IDC_HDF_CONTROLLER_UNIT, CB_SETCURSEL, current_tapedlg.ci.controller_unit, 0);
- }
- break;
- case IDC_HDF_CONTROLLER_UNIT:
- posn = SendDlgItemMessage (hDlg, IDC_HDF_CONTROLLER_UNIT, CB_GETCURSEL, 0, 0);
- if (posn != CB_ERR)
- current_tapedlg.ci.controller_unit = posn;
- break;
}
current_tapedlg.ci.readonly = !ischecked (hDlg, IDC_TAPE_RW);
recursive--;
+Beta 10:
+
+- Added hd controller subtype selection.
+- A590/A2091: DMAC-01/02 revision selection.
+- GVP Series I: all revisions.
+- Remaining non-DMA SupraDrives added.
+- Masoboshi MC-302 (IDE-only) and MC-702 (IDE+SCSI). Note that only MC-302 is currently working, DMA also not
+ yet supported. (Driver by default uses only PIO)
+- Added A2090/A2090a emulation.
+ (Currently shared with A590/A2091, it is not possible to use A2090 and A590/A2091 at the same time)
+- Previous supradrive config entry name changed, config reset needed.
+- A590/A2091 interrupt handling updates.
+- 68000 address error stacked PC accuracy improved (MOVEM and NOT, CLR and other single operand instructions)
+- Apparently GVP Series I Z2 RAM autoconfig id is 1761/8.
+- Accelerator board without IDE and SCSI and SCSI (auto) or IDE (auto) selected: drive was incorrectly reserved
+ for selected accelerator board.
+- Reorganized accelerator board handling, built-in HD controller configuration source code special cases removed.
+ ROM selection shows only ROM images compatible with selected accelerator board.
+- Added accelerator rom config/jumper options. Currently only map rom for Blizzards (ROM panel MapROM emulation
+ still also selects it) and OSMODE (J304) jumper for A26x0.
+- WD33C93 emulation fix, A2630+A2090 Amix installation works.
+- "24-bit address space is not supported with selected accelerator board configuration" error even when 24-bit
+ was not enabled.
+- Bogus 0x20 68882 stack frame version id removed, both 68881 and 68882 use 0x1f.
+- Set/reset accelerator ROM correctly in Quickstart mode.
+- Debugger fl was already reserved for listing active break points. Scanline fl renamed to fs.
+- Debugger library and device list commands (Td, Tl) shows version, revision, opencount and id string.
+- Debugger task list command (Tt) shows signals that task is waiting for and PC where task continues executing
+ when Wait() returns. Also previously it showed extra bogus entry and usually also didn't show all tasks..
+- Added extra prefetch hack for A26x0 ROM off switch code if 68030 MMU is enabled.
+- On the fly switching from AGA to non-AGA mode didn't reset FMODE value.
+
+A2090(a):
+
+- Commodore's first Amiga harddrive controller and it shows..
+- Custom partition table (No RDB), autoboot is supported.
+- Very confusing and illogical partitioning system. (No, double clicking "Prep HD" icon won't do what
+ you would expect it to do. At least with SCSI-only configuration.)
+- 34.4 boot ROM added.
+- At least 34.4 has broken format routine (few absolute addresses are not relocated correctly in rom code)
+ for SCSI drives. Disable boot ROM and use binddrivers mounting when running prep-program as a workaround.
+- ST-506 parts not emulated.
+
+GVP Series I:
+- Impact A2000-1/X (Autoconfig Product number 1)
+- Impact A2000-HC (Product 2)
+- Impact A2000-HC+2 (Product 3)
+- Nearly identical hardware. Different SRAM buffer size and SRAM address offset.
+- Early partition software created incompatible RDB blocks. (For example checksum fields are zeroed)
+- v1.0 (1.16 driver version) ROM added.
+
+SupraDrives:
+- A500 ByteSync/XP (was already supported since b8)
+- 2000 WordSync
+- A500 Autoboot
+- 4x4 (Non autoboot). Clock chip not yet emulated.
+- Supra AMABx ROMs support all above models.
+- All Supradrives except very rare 2000 DMA (which apparently had bad DMA implementation and uses
+ very different driver) are now emulated.
+
Beta 9:
- Fixed harddrive config parse crash. (b8)
*model = currprefs.ppc_model;
} else {
/* Set default CPU model based on accelerator board */
- if (currprefs.cpuboard_type == BOARD_BLIZZARDPPC) {
+ if (ISCPUBOARD(BOARD_BLIZZARD, BOARD_BLIZZARD_SUB_PPC)) {
*model = _T("603ev");
} else {
*model = _T("604e");
}
}
- if (currprefs.cpuboard_type == BOARD_BLIZZARDPPC) {
+ if (ISCPUBOARD(BOARD_BLIZZARD, BOARD_BLIZZARD_SUB_PPC)) {
*hid1 = 0xc0000000; // 4x
} else {
*hid1 = 0xa0000000; // 4x
return NULL;
}
-#define NEXT_ROM_ID 122
+#define NEXT_ROM_ID 124
static struct romheader romheaders[] = {
{ _T("Freezer Cartridges"), 1 },
{ _T("Freezer: HRTMon v2.33 (built-in)"), 0, 0, 0, 0, _T("HRTMON\0"), 0, 63, 0, 0, ROMTYPE_HRTMON, 0, 1, NULL,
0xffffffff, 0, 0, 0, 0, 0, _T("HRTMon") },
+ { _T("A2090a ROM"), 0, 0, 0, 0, _T("A2090A\0"), 16384, 122, 0, 0, ROMTYPE_A2090, 0, 0, NULL,
+ 0x73fe45a7, 0x77ce9091,0x4be5a3bf,0x6f26b343,0x062b5bd8,0xc63c3754 },
+ ALTROMPN(122, 1, 1, 8192, ROMTYPE_ODD | ROMTYPE_8BIT, _T("315097-01"), 0x150b116c,0x8011d873,0x3be53db0,0x79dfe319,0x7ffb8634,0x1baa6dbd)
+ ALTROMPN(122, 1, 2, 8192, ROMTYPE_EVEN | ROMTYPE_8BIT, _T("315098-01"), 0xbe422e3b,0x64ad1646,0x030db10f,0x54f13f64,0x7d449e4d,0x17f9ab5c)
{ _T("A590/A2091 ROM 6.0"), 6, 0, 6, 0, _T("A590\0A2091\0"), 16384, 53, 0, 0, ROMTYPE_A2091, 0, 0, NULL,
0x8396cf4e, 0x5E03BC61,0x8C862ABE,0x7BF79723,0xB4EEF4D2,0x1859A0F2 },
ALTROMPN(53, 1, 1, 8192, ROMTYPE_ODD | ROMTYPE_8BIT, _T("390389-03"), 0xb0b8cf24,0xfcf40175,0x05f4d441,0x814b45d5,0x59c19eab,0x43816b30)
{ _T("SupraDrive AMAB6"), 3, 8, 3, 8, _T("SUPRA\0"), 16384, 121, 0, 0, ROMTYPE_SUPRA, 0, 0, _T("AMAB6"),
0xf40bd349, 0x82168556,0x07525067,0xe9263431,0x1fb9c347,0xe737f247 },
- { _T("Blizzard 1230-IV ROM"), 0, 0, 0, 0, _T("B1230\0"), 32768, 89, 0, 0, ROMTYPE_CPUBOARD, 0, 0, NULL,
+ { _T("Blizzard 1230-IV ROM"), 0, 0, 0, 0, _T("B1230\0"), 32768, 89, 0, 0, ROMTYPE_CB_BLIZ1230, 0, 0, NULL,
0x3078dbdc, 0x4d3e7fd0,0xa1a4c3ae,0xe17c5de3,0xcbe1af03,0x447aff92 },
- { _T("Blizzard 1240/1260 ROM"), 0, 0, 0, 0, _T("B1240\0B1260\0"), 32768, 90, 0, 0, ROMTYPE_CPUBOARD, 0, 0, NULL,
+ { _T("Blizzard 1240/1260 ROM"), 0, 0, 0, 0, _T("B1240\0B1260\0"), 32768, 90, 0, 0, ROMTYPE_CB_BLIZ1260, 0, 0, NULL,
0xf88ae0f1, 0xf69aca4b,0xb13e3389,0x04676f0c,0x8616f8db,0x074c313d },
- { _T("Blizzard 2060 ROM"), 8, 5, 8, 5, _T("B2060\0"), 65536, 92, 0, 0, ROMTYPE_CPUBOARD, 0, 0, NULL,
+ { _T("Blizzard 2060 ROM"), 8, 5, 8, 5, _T("B2060\0"), 65536, 92, 0, 0, ROMTYPE_CB_BLIZ2060, 0, 0, NULL,
0xce270bc0, 0xe043c1aa,0x3bb06e06,0xd4dabff3,0x0a8c6317,0xabfef2bb },
ALTROMPN(92, 1, 1, 32768, ROMTYPE_ODD | ROMTYPE_8BIT, NULL, 0xa6023f20, 0xdfb048d6, 0xbdc03587, 0x241e8121, 0x26aba603, 0xd69b0238)
ALTROMPN(92, 1, 2, 32768, ROMTYPE_EVEN | ROMTYPE_8BIT, NULL, 0x9635a9cd, 0x47578b27, 0xc4ba6e54, 0x891930dd, 0xcb4b6a45, 0x5d6b31b2)
0xe4f485a5, 0x20bf7de5,0x05e45d0a,0xc411cfd2,0x806d0fd8,0xe46276de, NULL, _T("fastlanez3.rom") },
{ _T("Oktagon 2008 ROM"), 6, 12, 6, 12, _T("OKTAGON\0"), 32768, 103, 0, 0, ROMTYPE_OKTAGON, 0, 0, NULL,
0xbb0d2f6a, 0x56c441fa,0x37d19339,0x3081b2e8,0xceae823b,0xc7e97e49, NULL, _T("oktagon2008.rom") },
- { _T("Warp Engine A4000 ROM"), 0, 0, 0, 0, _T("WARPENGINE\0WARPENGINEA4000\0"), 32768, 93, 0, 0, ROMTYPE_CPUBOARD, 0, 0, NULL,
+ { _T("Warp Engine A4000 ROM"), 0, 0, 0, 0, _T("WARPENGINE\0WARPENGINEA4000\0"), 32768, 93, 0, 0, ROMTYPE_CB_WENGINE, 0, 0, NULL,
0x4deb574a, 0x6e6c95ff,0xe8448391,0xd36c5b68,0xc9065cb0,0x702a7d27 },
- { _T("TekMagic 2040/2060 ROM"), 1, 0, 1, 0, _T("TEKMAGIC\0TEKMAGIC2040\0TEKMAGIC2060\0"), 65536, 104, 0, 0, ROMTYPE_CPUBOARD, 0, 0, NULL,
+ { _T("TekMagic 2040/2060 ROM"), 1, 0, 1, 0, _T("TEKMAGIC\0TEKMAGIC2040\0TEKMAGIC2060\0"), 65536, 104, 0, 0, ROMTYPE_CB_TEKMAGIC, 0, 0, NULL,
0x9e9781d5, 0xf65b60d1,0x4300c50f,0x2ed17cf4,0x4dcfdef9,0x16697bc9, NULL, _T("tekmagic2060.rom") },
ALTROMPN(104, 1, 1, 32768, ROMTYPE_ODD | ROMTYPE_8BIT, NULL, 0x888da4cf, 0x6ae85f3a, 0x65331ba4, 0xaaba67ae, 0x34763d70, 0x2bde0495)
ALTROMPN(104, 1, 2, 32768, ROMTYPE_EVEN | ROMTYPE_8BIT, NULL, 0xaf1f47db, 0x28d5bed0, 0xbc517d46, 0x500e8159, 0x723e0b64, 0x4733c26a)
- { _T("A2620/A2630 -07 ROM"), 0, 0, 0, 0, _T("A2620\0A2630\0"), 65536, 105, 0, 0, ROMTYPE_CPUBOARD, 0, 0, _T("390282-07/390283-07"),
+ { _T("A2620/A2630 -07 ROM"), 0, 0, 0, 0, _T("A2620\0A2630\0"), 65536, 105, 0, 0, ROMTYPE_CB_A26x0, 0, 0, _T("390282-07/390283-07"),
0x169d80e9, 0x41f518cb,0x41c1dc1f,0xcc636383,0x20676af5,0x4969010c, NULL, NULL },
ALTROMPN(105, 1, 1, 32768, ROMTYPE_ODD | ROMTYPE_8BIT, _T("390282-07"), 0xf2904058, 0x33695119, 0x5fdf5d56, 0x095a696b, 0x0ba2641d, 0x334845df)
ALTROMPN(105, 1, 2, 32768, ROMTYPE_EVEN | ROMTYPE_8BIT, _T("390283-07"), 0xf697d458, 0x09fe260b, 0x03784e87, 0x3351dbec, 0x5146a455, 0x814383d1)
- { _T("A2620/A2630 -06 ROM"), 0, 0, 0, 0, _T("A2620\0A2630\0"), 65536, 106, 0, 0, ROMTYPE_CPUBOARD, 0, 0, _T("390282-06/390283-06"),
+ { _T("A2620/A2630 -06 ROM"), 0, 0, 0, 0, _T("A2620\0A2630\0"), 65536, 106, 0, 0, ROMTYPE_CB_A26x0, 0, 0, _T("390282-06/390283-06"),
0xeb31fd9e, 0x2d6a5c68,0x1040f98d,0x7e63ad08,0x90da9e83,0x2b5c704d, NULL, NULL },
ALTROMPN(106, 1, 1, 32768, ROMTYPE_ODD | ROMTYPE_8BIT, _T("390282-06"), 0xd6ae582c, 0x47b3dea3, 0x31db76e6, 0x1380a3d6, 0x9f191657, 0xdd1cd4b3)
ALTROMPN(106, 1, 2, 32768, ROMTYPE_EVEN | ROMTYPE_8BIT, _T("390283-06"), 0xcd379634, 0x65e251e2, 0xf6961c8e, 0x33a86c3d, 0x01248f70, 0xa159823b)
- { _T("DKB 12x0 ROM"), 1, 23, 1, 23, _T("DKB\0"), 32768, 112, 0, 0, ROMTYPE_CPUBOARD, 0, 0, NULL,
+ { _T("DKB 12x0 ROM"), 1, 23, 1, 23, _T("DKB\0"), 32768, 112, 0, 0, ROMTYPE_CB_DKB12x0, 0, 0, NULL,
0xf3b2b0b3, 0x1d539593,0xb1d7514e,0xeb214ab3,0x433a97fc,0x8a010366, NULL, NULL },
- { _T("Fusion Forty ROM"), 0, 0, 0, 0, _T("FUSIONFORTY\0"), 131072, 113, 0, 0, ROMTYPE_CPUBOARD, 0, 0, NULL,
+ { _T("Fusion Forty ROM"), 0, 0, 0, 0, _T("FUSIONFORTY\0"), 131072, 113, 0, 0, ROMTYPE_CB_FUSION, 0, 0, NULL,
0x48fcb5fd, 0x15674dac,0x90b6d8db,0xdda3a175,0x997184c2,0xa423d733, NULL, NULL },
ALTROMPN(113, 1, 1, 32768, ROMTYPE_QUAD | ROMTYPE_EVEN | ROMTYPE_8BIT, _T("U28"), 0x434a21a8, 0x472c1623, 0x02babd00, 0x7c1a77ff, 0x40dd12ab, 0x39c97f82)
ALTROMPN(113, 1, 2, 32768, ROMTYPE_QUAD | ROMTYPE_ODD | ROMTYPE_8BIT, _T("U27"), 0x38373cf6, 0xfe8aa931, 0xada6b6f3, 0x6b48ca3c, 0x9b86677d, 0xbee4da59)
ALTROMPN(113, 1, 3, 32768, ROMTYPE_QUAD | ROMTYPE_EVEN | ROMTYPE_8BIT, _T("U25"), 0xc9e990d3, 0xb251ef73, 0x1374e796, 0xa87cbc7e, 0x9263320a, 0x28a71d2b)
ALTROMPN(113, 1, 4, 32768, ROMTYPE_QUAD | ROMTYPE_ODD | ROMTYPE_8BIT, _T("U26"), 0x2e117fe0, 0xbb2de2da, 0x6db4e92c, 0x636fefe6, 0x13a32699, 0xcea31011)
- { _T("Apollo 1240/1260 ROM"), 5, 60, 5, 60, _T("APOLLO12XX\0"), 131072, 119, 0, 0, ROMTYPE_CPUBOARD, 0, 0, NULL,
+ { _T("Apollo 1240/1260 ROM"), 5, 60, 5, 60, _T("APOLLO12XX\0"), 131072, 119, 0, 0, ROMTYPE_CB_APOLLO, 0, 0, NULL,
0xcd009ad9, 0x1c3b4851,0xc5a221e3,0xa7ca24fc,0xc1df4a5b,0x9f2343ad },
- { _T("GVP A3001 Series I ROM"), 3, 3, 3, 3, _T("A3001SI\0"), 8192, 114, 0, 0, ROMTYPE_CPUBOARD, 0, 0, NULL,
+ { _T("GVP A3001 Series I ROM"), 3, 3, 3, 3, _T("A3001SI\0"), 8192, 114, 0, 0, ROMTYPE_CB_A3001S1, 0, 0, NULL,
0xaaff7c65, 0x424cf3da,0xcc9da794,0x0ba74446,0x69dd1691,0x44ae87ee, NULL, NULL },
- { _T("GVP Series II v3.15 ROM"), 3, 15, 3, 15, _T("GVPII\0"), 16384, 111, 0, 0, ROMTYPE_GVPS2, 0, 0, NULL,
+ { _T("GVP Series I v1.0 ROM"), 1, 0, 1, 16, _T("GVPI\0"), 16384, 123, 0, 0, ROMTYPE_GVPS1, 0, 0, NULL,
+ 0x1a4c20aa, 0xb9a3377e,0x2d9b5163,0x28693c63,0x19ffb65b,0x40ae3618, NULL, NULL },
+ ALTROMPN(123, 1, 1, 8192, ROMTYPE_ODD | ROMTYPE_8BIT, NULL, 0xa723193e, 0x05b4a072, 0x785c7824, 0x54e003c3, 0x6d88bd9b, 0xf5f561b9)
+ ALTROMPN(123, 1, 2, 8192, ROMTYPE_EVEN | ROMTYPE_8BIT, NULL, 0x27f15785, 0x1a71a78d, 0xdd4e9559, 0x0f133bba, 0x4a71122f, 0x44caef78)
+ { _T("GVP Series I/II v3.15 ROM"), 3, 15, 3, 15, _T("GVPII\0GVPI\0"), 16384, 111, 0, 0, ROMTYPE_GVPS12, 0, 0, NULL,
0xf99c6f11, 0x77098a9e,0x35acaef2,0x11a546f0,0xc564cdac,0xf52836c4, NULL, NULL },
{ _T("GVP Series II v4.15 ROM"), 4, 15, 4, 15, _T("GVPII\0"), 16384, 109, 0, 0, ROMTYPE_GVPS2, 0, 0, NULL,
0xf89f44d6, 0xbf10c12c,0xc72dd040,0x549ea17c,0x24947633,0xe3773297, NULL, NULL },
{ _T("Masoboshi MC-702 ROM"), 2, 201, 2, 201, _T("MASOBOSHI\0"), 32768, 120, 0, 0, ROMTYPE_MASOBOSHI, 0, 0, NULL,
0xcd99b98a, 0x3897e46a,0x66d5833f,0x849b8e81,0x30acb3cb,0x319a2fa0, NULL, NULL },
- { _T("CyberStorm MK I 68040"), 0, 0, 0, 0, _T("CSMKI\0"), 32768, 95, 0, 0, ROMTYPE_CPUBOARD, 0, 0, NULL,
+ { _T("CyberStorm MK I 68040"), 0, 0, 0, 0, _T("CSMKI\0"), 32768, 95, 0, 0, ROMTYPE_CB_CSMK1, 0, 0, NULL,
0, 0, 0, 0, 0, 0, NULL, _T("cyberstormmk1_040.rom") },
- { _T("CyberStorm MK I 68060"), 0, 0, 0, 0, _T("CSMKI\0"), 65536, 101, 0, 0, ROMTYPE_CPUBOARD, 0, 0, NULL,
+ { _T("CyberStorm MK I 68060"), 0, 0, 0, 0, _T("CSMKI\0"), 65536, 101, 0, 0, ROMTYPE_CB_CSMK1, 0, 0, NULL,
0, 0, 0, 0, 0, 0, NULL, _T("cyberstormmk1_060.rom") },
- { _T("CyberStorm MK II"), 0, 0, 0, 0, _T("CSMKII\0"), 131072, 96, 0, 0, ROMTYPE_CPUBOARD, 0, 0, NULL,
+ { _T("CyberStorm MK II"), 0, 0, 0, 0, _T("CSMKII\0"), 131072, 96, 0, 0, ROMTYPE_CB_CSMK2, 0, 0, NULL,
0, 0, 0, 0, 0, 0, NULL, _T("cyberstormmk2.rom") },
- { _T("CyberStorm MK III"), 0, 0, 0, 0, _T("CSMKIII\0"), 131072, 97, 0, 0, ROMTYPE_CPUBOARD, 0, 0, NULL,
+ { _T("CyberStorm MK III"), 0, 0, 0, 0, _T("CSMKIII\0"), 131072, 97, 0, 0, ROMTYPE_CB_CSMK3, 0, 0, NULL,
0, 0, 0, 0, 0, 0, NULL, _T("cyberstormmk3.rom") },
- { _T("CyberStorm PPC"), 0, 0, 0, 0, _T("CSPPC\0"), 131072, 98, 0, 0, ROMTYPE_CPUBOARD, 0, 0, NULL,
+ { _T("CyberStorm PPC"), 0, 0, 0, 0, _T("CSPPC\0"), 131072, 98, 0, 0, ROMTYPE_CB_CSPPC, 0, 0, NULL,
0, 0, 0, 0, 0, 0, NULL, _T("cyberstormppc.rom") },
- { _T("Blizzard PPC 68040"), 0, 0, 0, 0, _T("BPPC\0"), 524288, 99, 0, 0, ROMTYPE_CPUBOARD, 0, 0, NULL,
+ { _T("Blizzard PPC 68040"), 0, 0, 0, 0, _T("BPPC\0"), 524288, 99, 0, 0, ROMTYPE_CB_BLIZPPC, 0, 0, NULL,
0, 0, 0, 0, 0, 0, NULL, _T("blizzardppc_040.rom") },
- { _T("Blizzard PPC 68060"), 0, 0, 0, 0, _T("BPPC\0"), 524288, 100, 0, 0, ROMTYPE_CPUBOARD, 0, 0, NULL,
+ { _T("Blizzard PPC 68060"), 0, 0, 0, 0, _T("BPPC\0"), 524288, 100, 0, 0, ROMTYPE_CB_BLIZPPC, 0, 0, NULL,
0, 0, 0, 0, 0, 0, NULL, _T("blizzardppc_060.rom") },
{ _T("Picasso IV ROM"), 7, 4, 7, 4, _T("PIV\0"), 131072, 91, 0, 0, ROMTYPE_PIV, 0, 0, NULL,
struct boardromconfig *brc = get_device_rom(p, romtype, &idx);
if (brc) {
const TCHAR *romname = brc->roms[idx].romfile;
+ if (!_tcsicmp(romname, _T(":NOROM")))
+ return NULL;
struct zfile *z = read_rom_name (romname);
if (!z) {
struct romlist *rl = getromlistbyids(roms, romname);
}
return -1;
}
+
+struct boardromconfig *get_boardromconfig(struct uae_prefs *p, int romtype, int *index)
+{
+ for (int i = 0; i < MAX_EXPANSION_BOARDS; i++) {
+ struct boardromconfig *brc = &p->expansionboard[i];
+ if ((brc->device_type & ROMTYPE_MASK) == (romtype & ROMTYPE_MASK)) {
+ for (int j = 0; j < MAX_BOARD_ROMS; j++) {
+ if (brc->roms[j].romfile[0]) {
+ if (index)
+ *index = j;
+ return brc;
+ }
+ }
+ }
+ }
+ return NULL;
+}
\ No newline at end of file
extern int log_scsiemu;
-static const int outcmd[] = { 0x0a, 0x2a, 0xaa, 0x15, 0x55, -1 };
+static const int outcmd[] = { 0x04, 0x0a, 0x2a, 0xaa, 0x15, 0x55, -1 };
static const int incmd[] = { 0x01, 0x03, 0x05, 0x08, 0x12, 0x1a, 0x5a, 0x25, 0x28, 0x34, 0x37, 0x42, 0x43, 0xa8, 0x51, 0x52, 0xbd, -1 };
static const int nonecmd[] = { 0x00, 0x0b, 0x11, 0x16, 0x17, 0x19, 0x1b, 0x1e, 0x2b, 0x35, -1 };
static const int scsicmdsizes[] = { 6, 10, 10, 12, 16, 12, 10, 10 };
+static void scsi_illegal_command(struct scsi_data *sd)
+{
+ uae_u8 *s = sd->sense;
+
+ memset (s, 0, sizeof (sd->sense));
+ sd->status = SCSI_STATUS_CHECK_CONDITION;
+ s[0] = 0x70;
+ s[2] = 5; /* ILLEGAL REQUEST */
+ s[12] = 0x24; /* ILLEGAL FIELD IN CDB */
+ sd->sense_len = 0x12;
+}
+
static void scsi_grow_buffer(struct scsi_data *sd, int newsize)
{
if (sd->buffer_size >= newsize)
return 0;
}
-void scsi_emulate_analyze (struct scsi_data *sd)
+bool scsi_emulate_analyze (struct scsi_data *sd)
{
int cmd_len, data_len, data_len2, tmp_len;
data_len = sd->data_len;
data_len2 = 0;
cmd_len = scsicmdsizes[sd->cmd[0] >> 5];
+ if (sd->hfd && sd->hfd->ansi_version < 2 && cmd_len > 10)
+ goto nocmd;
sd->cmd_len = cmd_len;
switch (sd->cmd[0])
{
+ case 0x04: // FORMAT UNIT
+ if (sd->device_type == UAEDEV_CD)
+ goto nocmd;
+ // FmtData set?
+ if (sd->cmd[1] & 0x10) {
+ int cl = (sd->cmd[1] & 8) != 0;
+ int dlf = sd->cmd[1] & 7;
+ data_len2 = 4;
+ }
+ break;
case 0x08: // READ(6)
data_len2 = sd->cmd[4] * sd->blocksize;
scsi_grow_buffer(sd, data_len2);
scsi_grow_buffer(sd, data_len2);
break;
case 0x0a: // WRITE(6)
+ if (sd->device_type == UAEDEV_CD)
+ goto nocmd;
data_len = sd->cmd[4] * sd->blocksize;
scsi_grow_buffer(sd, data_len);
break;
case 0x2a: // WRITE(10)
+ if (sd->device_type == UAEDEV_CD)
+ goto nocmd;
data_len = ((sd->cmd[7] << 8) | (sd->cmd[8] << 0)) * (uae_s64)sd->blocksize;
scsi_grow_buffer(sd, data_len);
break;
case 0xaa: // WRITE(12)
+ if (sd->device_type == UAEDEV_CD)
+ goto nocmd;
data_len = ((sd->cmd[6] << 24) | (sd->cmd[7] << 16) | (sd->cmd[8] << 8) | (sd->cmd[9] << 0)) * (uae_s64)sd->blocksize;
scsi_grow_buffer(sd, data_len);
break;
case 0xbe: // READ CD
case 0xb9: // READ CD MSF
+ if (sd->device_type != UAEDEV_CD)
+ goto nocmd;
tmp_len = (sd->cmd[6] << 16) | (sd->cmd[7] << 8) | sd->cmd[8];
// max block transfer size, it is usually smaller.
tmp_len *= 2352 + 96;
sd->data_len = 0;
sd->direction = 0;
}
- return;
+ return true;
}
sd->data_len = data_len;
sd->direction = scsi_data_dir (sd);
+ return true;
+nocmd:
+ sd->status = SCSI_STATUS_CHECK_CONDITION;
+ sd->direction = 0;
+ scsi_illegal_command(sd);
+ return false;
}
void scsi_illegal_lun(struct scsi_data *sd)
int board_size;
addrbank *bank;
int type;
+ int subtype;
int dma_direction;
};
if (sd->offset >= len) {
#if RAW_SCSI_DEBUG
write_log(_T("raw_scsi: got command %02x (%d bytes)\n"), sd->cmd[0], len);
+ for (int i = 0; i < len; i++) {
+ write_log(_T("%02x."), sd->cmd[i]);
+ }
+ write_log(_T("\n"));
#endif
scsi_emulate_analyze(rs->target);
if (sd->direction > 0) {
return;
if (scsi->regs[2] & 0x40)
return;
+ if (scsi->regs[5] & 0x80)
+ return;
if (scsi->rscsi.bus_phase != (scsi->regs[3] & 7)) {
scsi->regs[5] |= 0x80; // end of dma
scsi->regs[3] |= 0x80;
static int suprareg(struct ncr5380_scsi *ncr, uaecptr addr, bool write)
{
- int reg = (addr & 0x1f) >> 1;
- if (addr & 0x20) {
+ int reg = (addr & 0x0f) >> 1;
+ if ((addr & 0x20) && ncr->subtype == 0) {
if (!write)
reg = 6;
else
{
int reg = -1;
uae_u32 v = 0;
+ int addresstype = -1;
addr &= ncr->board_mask;
if (ncr->type == NCR5380_SUPRA) {
- if (addr & 1) {
- v = 0xff;
- } else if (addr & 0x8000) {
- v = ncr->rom[addr & 0x7fff];
+ if (ncr->subtype == 3) {
+ if ((addr & 0x8000) && !(addr & 1))
+ addresstype = 0;
} else {
+ if (ncr->subtype != 1 && (addr & 1)) {
+ v = 0xff;
+ } else if (addr & 0x8000) {
+ addresstype = 1;
+ } else {
+ addresstype = 0;
+ }
+ }
+
+ if (addresstype == 1) {
+ v = ncr->rom[addr & 0x7fff];
+ } else if (addresstype == 0) {
reg = suprareg(ncr, addr, false);
if (reg >= 0)
v = ncr5380_bget(ncr, reg);
}
+
}
#if NCR5380_DEBUG > 1
static void ncr80_bput2(struct ncr5380_scsi *ncr, uaecptr addr, uae_u32 val)
{
int reg = -1;
+ int addresstype = -1;
+
addr &= ncr->board_mask;
- if (!(addr & 0x8001)) {
+ if (ncr->subtype == 3) {
+ if ((addr & 0x8000) && !(addr & 1))
+ addresstype = 0;
+ } else {
+ if (ncr->subtype != 1 && (addr & 1))
+ return;
+ if (!(addr & 0x8000))
+ addresstype = 0;
+ }
+ if (addresstype == 0) {
reg = suprareg(ncr, addr, true);
if (reg >= 0)
ncr5380_bput(ncr, reg, val);
#define SUPRA_ROM_OFFSET 0x8000
-static const uae_u8 supra_autoconfig[16] = { 0xd1, 13, 0x00, 0x00, 0x04, 0x20, 0x00, 0x00, 0x00, 0x00, SUPRA_ROM_OFFSET >> 8, SUPRA_ROM_OFFSET & 0xff };
+static const uae_u8 supra_autoconfig_byte[16] = { 0xd1, 13, 0x00, 0x00, 0x04, 0x20, 0x00, 0x00, 0x00, 0x00, SUPRA_ROM_OFFSET >> 8, SUPRA_ROM_OFFSET & 0xff };
+static const uae_u8 supra_autoconfig_word[16] = { 0xd1, 12, 0x00, 0x00, 0x04, 0x20, 0x00, 0x00, 0x00, 0x00, SUPRA_ROM_OFFSET >> 8, SUPRA_ROM_OFFSET & 0xff };
+static const uae_u8 supra_autoconfig_500[16] = { 0xd1, 8, 0x00, 0x00, 0x04, 0x20, 0x00, 0x00, 0x00, 0x00, SUPRA_ROM_OFFSET >> 8, SUPRA_ROM_OFFSET & 0xff };
+static const uae_u8 supra_autoconfig_4x4[16] = { 0xc1, 1, 0x00, 0x00, 0x04, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
addrbank *supra_init(int devnum)
{
scsi->bank = &ncr_bank_supra;
scsi->rom = xcalloc(uae_u8, 2 * 16384);
scsi->type = NCR5380_SUPRA;
+ scsi->subtype = 0;
memset(scsi->rom, 0xff, 2 * 16384);
rc = get_device_romconfig(&currprefs, devnum, ROMTYPE_SUPRA);
- if (rc && !rc->autoboot_disabled) {
- struct zfile *z = read_device_rom(&currprefs, devnum, ROMTYPE_SUPRA, roms);
+ if (rc) {
+ struct zfile *z = NULL;
+ scsi->subtype = rc->subtype;
+ if (!rc->autoboot_disabled && scsi->subtype != 3) {
+ z = read_device_rom(&currprefs, devnum, ROMTYPE_SUPRA, roms);
+ if (!z && is_device_rom(&currprefs, devnum, ROMTYPE_SUPRA))
+ romwarning(roms);
+ }
for (int i = 0; i < 16; i++) {
- uae_u8 b = supra_autoconfig[i];
+ uae_u8 b = scsi->subtype == 3 ? supra_autoconfig_4x4[i] :
+ (scsi->subtype == 2 ? supra_autoconfig_500[i] : (scsi->subtype == 1 ? supra_autoconfig_word[i] : supra_autoconfig_byte[i]));
ew(scsi, i * 4, b);
}
if (z) {
scsi->rom[i * 2 + 0] = b;
}
zfile_fclose(z);
- } else {
- romwarning(roms);
}
}
return scsi->bank;
memcpy (nzf->data, zf->data, zf->size);
nzf->size = zf->size;
nzf->datasize = zf->datasize;
- } else {
+ } else if (zf->useparent) {
+ nzf = zfile_fopen_parent(zf, zf->name, 0, zf->size);
+ return nzf;
+ } else {
if (zf->zipname) {
nzf = openzip (zf->name);
if (nzf)
return nzf;
}
+ if (!zf->name || !zf->mode)
+ return NULL;
FILE *ff = _tfopen (zf->name, zf->mode);
if (!ff)
return NULL;
projects / francis / winuae.git / commitdiff