#ifdef NCR
-#define NCR_DEBUG 2
+#define NCR_DEBUG 1
#include "options.h"
#include "uae.h"
#include "devices.h"
#define BOARD_SIZE 16777216
-#define IO_MASK 0xff
+#define IO_MASK 0x7f
#define A4091_ROM_VECTOR 0x0200
#define A4091_ROM_OFFSET 0x0000
int io_start, io_end;
addrbank *bank;
bool irq;
+ bool irqlevel;
+ bool z2;
void (*irq_func)(int, int);
struct romconfig *rc;
struct ncr_state **self_ptr;
static struct ncr_state *ncr_a4000t;
static struct ncr_state *ncra4091[MAX_DUPLICATE_EXPANSION_BOARDS];
static struct ncr_state *ncr_wildfire;
+static struct ncr_state *ncr_zeus040;
static void set_irq2(int id, int level)
{
if (level)
safe_interrupt_set(IRQ_SOURCE_NCR, 0, false);
}
+static void set_irq6(int id, int level)
+{
+ if (level)
+ safe_interrupt_set(IRQ_SOURCE_NCR, 0, true);
+}
void ncr_rethink(void)
{
for (int i = 0; ncr_units[i]; i++) {
if (ncr_units[i] != ncr_cs && ncr_units[i]->irq)
- safe_interrupt_set(IRQ_SOURCE_NCR, i + 1, false);
+ safe_interrupt_set(IRQ_SOURCE_NCR, i + 1, ncr_units[i]->irqlevel);
}
if (ncr_cs && ncr_cs->irq)
cyberstorm_mk3_ppc_irq_setonly(0, 1);
{
uae_u32 v = val;
addr &= ncr->board_mask;
- if (ncr->io_end && (addr < ncr->io_start || addr >= ncr->io_end))
+ if (ncr->io_end && (addr < ncr->io_start || addr >= ncr->io_end)) {
+#if NCR_DEBUG > 1
+ write_log(_T("ncr_bput none %08x %02x %08x\n"), addr, v & 0xff, M68K_GETPC);
+#endif
return;
+ }
+#if NCR_DEBUG > 1
+ write_log(_T("ncr_bput %08x %02x %08x\n"), addr, v & 0xff, M68K_GETPC);
+#endif
if (ncr->newncr)
ncr_io_bput(ncr, addr, val);
else
v ^= 0xff & ~7;
return v;
}
- if (ncr->io_end && (addr < ncr->io_start || addr >= ncr->io_end))
+ if (ncr->io_end && (addr < ncr->io_start || addr >= ncr->io_end)) {
+#if NCR_DEBUG > 1
+ write_log(_T("ncr_bget none %08x %02x %08x\n"), addr, v, M68K_GETPC);
+#endif
return v;
+ }
if (ncr->newncr)
- return ncr_io_bget(ncr, addr);
+ v = ncr_io_bget(ncr, addr);
else
- return ncr710_io_bget(ncr, addr);
+ v = ncr710_io_bget(ncr, addr);
+#if NCR_DEBUG > 1
+ write_log(_T("ncr_bget %08x %02x %08x\n"), addr, v, M68K_GETPC);
+#endif
+ return v;
}
static uae_u32 REGPARAM2 ncr_lget (struct ncr_state *ncr, uaecptr addr)
uae_u32 v = 0;
if (ncr) {
addr &= ncr->board_mask;
- if (ncr == ncr_we) {
- addr &= ~0x80;
- v = (ncr_bget2(ncr, addr + 3) << 0) | (ncr_bget2(ncr, addr + 2) << 8) |
- (ncr_bget2(ncr, addr + 1) << 16) | (ncr_bget2(ncr, addr + 0) << 24);
+ if (addr >= A4091_IO_ALT) {
+ v = (ncr_bget2 (ncr, addr + 3) << 0) | (ncr_bget2 (ncr, addr + 2) << 8) |
+ (ncr_bget2 (ncr, addr + 1) << 16) | (ncr_bget2 (ncr, addr + 0) << 24);
} else {
- if (addr >= A4091_IO_ALT) {
- v = (ncr_bget2 (ncr, addr + 3) << 0) | (ncr_bget2 (ncr, addr + 2) << 8) |
- (ncr_bget2 (ncr, addr + 1) << 16) | (ncr_bget2 (ncr, addr + 0) << 24);
- } else {
- v = (ncr_bget2 (ncr, addr + 3) << 0) | (ncr_bget2 (ncr, addr + 2) << 8) |
- (ncr_bget2 (ncr, addr + 1) << 16) | (ncr_bget2 (ncr, addr + 0) << 24);
- }
+ v = (ncr_bget2 (ncr, addr + 3) << 0) | (ncr_bget2 (ncr, addr + 2) << 8) |
+ (ncr_bget2 (ncr, addr + 1) << 16) | (ncr_bget2 (ncr, addr + 0) << 24);
}
}
return v;
if (!ncr)
return;
addr &= ncr->board_mask;
- if (ncr == ncr_we) {
- addr &= ~0x80;
- ncr_bput2(ncr, addr + 3, l >> 0);
- ncr_bput2(ncr, addr + 2, l >> 8);
- ncr_bput2(ncr, addr + 1, l >> 16);
- ncr_bput2(ncr, addr + 0, l >> 24);
+ if (addr >= A4091_IO_ALT) {
+ ncr_bput2 (ncr, addr + 3, l >> 0);
+ ncr_bput2 (ncr, addr + 2, l >> 8);
+ ncr_bput2 (ncr, addr + 1, l >> 16);
+ ncr_bput2 (ncr, addr + 0, l >> 24);
} else {
- if (addr >= A4091_IO_ALT) {
- ncr_bput2 (ncr, addr + 3, l >> 0);
- ncr_bput2 (ncr, addr + 2, l >> 8);
- ncr_bput2 (ncr, addr + 1, l >> 16);
- ncr_bput2 (ncr, addr + 0, l >> 24);
- } else {
- ncr_bput2 (ncr, addr + 3, l >> 0);
- ncr_bput2 (ncr, addr + 2, l >> 8);
- ncr_bput2 (ncr, addr + 1, l >> 16);
- ncr_bput2 (ncr, addr + 0, l >> 24);
- }
+ ncr_bput2 (ncr, addr + 3, l >> 0);
+ ncr_bput2 (ncr, addr + 2, l >> 8);
+ ncr_bput2 (ncr, addr + 1, l >> 16);
+ ncr_bput2 (ncr, addr + 0, l >> 24);
}
}
addr &= ncr->board_mask;
if (!ncr->configured) {
addr &= 65535;
- switch (addr)
- {
- case 0x4c:
- ncr->configured = 1;
- expamem_shutup(ncr->bank);
- break;
- case 0x48:
- ncr->expamem_lo = b & 0xff;
- break;
+ if (ncr->z2) {
+ switch (addr)
+ {
+ case 0x48:
+ ncr->expamem_hi = b & 0xff;
+ map_banks_z2(ncr->bank, expamem_board_pointer >> 16, expamem_board_size >> 16);
+ ncr->baseaddress = expamem_board_pointer;
+ ncr->configured = 1;
+ expamem_next(ncr->bank, NULL);
+ break;
+ case 0x4c:
+ ncr->configured = 1;
+ expamem_shutup(ncr->bank);
+ break;
+ case 0x4a:
+ ncr->expamem_lo = b & 0xff;
+ break;
+ }
+ } else {
+ switch (addr)
+ {
+ case 0x4c:
+ ncr->configured = 1;
+ expamem_shutup(ncr->bank);
+ break;
+ case 0x48:
+ ncr->expamem_lo = b & 0xff;
+ break;
+ }
}
return;
}
ncr_generic_lput, ncr_generic_wput, ncr_generic_bput,
default_xlate, default_check, NULL, NULL, _T("NCR53C700/800"),
dummy_lgeti, dummy_wgeti,
- ABFLAG_IO | ABFLAG_THREADSAFE, S_READ, S_WRITE
+ ABFLAG_IO | ABFLAG_THREADSAFE | ABFLAG_SAFE, S_READ, S_WRITE
};
static void ew (struct ncr_state *ncr, int addr, uae_u8 value)
if (!ncr)
return false;
- ncr_we = ncr;
xfree(ncr->rom);
ncr->rom = NULL;
return true;
}
+static const uae_u8 zeus040_autoconfig[16] = {
+ 0xd1, 0x96, 0x40, 0x00, 0x07, 0xea, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+bool ncr710_zeus040_autoconfig_init(struct autoconfig_info *aci)
+{
+ aci->autoconfigp = zeus040_autoconfig;
+ if (!aci->doinit)
+ return true;
+
+ struct ncr_state *ncr = getscsi(aci->rc);
+ if (!ncr)
+ return false;
+
+ xfree(ncr->rom);
+ ncr->rom = NULL;
+
+ ncr->enabled = true;
+ memset(ncr->acmemory, 0xff, sizeof ncr->acmemory);
+ ncr->rom_start = 0x8000;
+ ncr->rom_offset = 0x8000;
+ ncr->rom_end = 0x10000;
+ ncr->io_start = 0x4000;
+ ncr->io_end = 0x8000;
+
+ for (int i = 0; i < 16; i++) {
+ uae_u8 b = zeus040_autoconfig[i];
+ if (i == 0 && (currprefs.cpuboard_settings & 1))
+ b &= ~0x10;
+ ew(ncr, i * 4, b);
+ }
+ ncr->rom = xcalloc(uae_u8, 32768);
+ load_rom_rc(aci->rc, ROMTYPE_CB_ZEUS040, 16384, 0, ncr->rom, 32768, 0);
+
+ ncr_reset_board(ncr);
+
+ aci->addrbank = &ncr_bank_generic;
+ return true;
+}
+
+
void ncr_free(void)
{
for (int i = 0; i < MAX_NCR_UNITS; i++) {
ncr_wildfire->bank = &ncr_bank_generic;
}
+void zeus040_add_scsi_unit(int ch, struct uaedev_config_info *ci, struct romconfig *rc)
+{
+ ncr_add_scsi_unit(&ncr_zeus040, ch, ci, rc, false);
+ ncr_zeus040->irq_func = set_irq6;
+ ncr_zeus040->irqlevel = true;
+ ncr_zeus040->z2 = true;
+}
+
#endif
return NULL;
}
-#define NEXT_ROM_ID 225
+#define NEXT_ROM_ID 226
#define ALTROM(id,grp,num,size,flags,crc32,a,b,c,d,e) \
{ _T("X"), 0, 0, 0, 0, 0, size, id, 0, 0, flags, (grp << 16) | num, 0, NULL, crc32, a, b, c, d, e },
0x9e9781d5, 0xf65b60d1,0x4300c50f,0x2ed17cf4,0x4dcfdef9,0x16697bc9, NULL, _T("tekmagic2060.rom") },
ALTROMPN(104, 1, 1, 32768, ROMTYPE_ODD | ROMTYPE_8BIT, NULL, 0x888da4cf, 0x6ae85f3a, 0x65331ba4, 0xaaba67ae, 0x34763d70, 0x2bde0495)
ALTROMPN(104, 1, 2, 32768, ROMTYPE_EVEN | ROMTYPE_8BIT, NULL, 0xaf1f47db, 0x28d5bed0, 0xbc517d46, 0x500e8159, 0x723e0b64, 0x4733c26a)
+ { _T("Zeus 040"), 2, 98, 2, 98, _T("ZEUS040\0"), 16384, 225, 0, 0, ROMTYPE_CB_ZEUS040, 0, 0, NULL,
+ 0x2c609194, 0x9a91cf45,0x6816067a,0x943c18f1,0xbd30effe,0x482d4aaf, NULL, NULL },
+ ALTROMPN(225, 1, 1, 8192, ROMTYPE_ODD | ROMTYPE_8BIT, NULL, 0xc0bea5dd, 0x1540a755, 0x36066da4, 0x8bcb3dd4, 0xf13f179b, 0x9439f379)
+ ALTROMPN(225, 1, 2, 8192, ROMTYPE_EVEN | ROMTYPE_8BIT, NULL, 0x7989684f, 0x9dc4d885, 0x242bf7eb, 0xe75a01b2, 0x483c9e3c, 0x8013896b)
{ _T("A2620/A2630 -07"), 0, 0, 0, 0, _T("A2620\0A2630\0"), 65536, 105, 0, 0, ROMTYPE_CB_A26x0, 0, 0, _T("390282-07/390283-07"),
0x169d80e9, 0x41f518cb,0x41c1dc1f,0xcc636383,0x20676af5,0x4969010c, NULL, NULL },