void devices_hsync(void)
{
- #ifdef A2065
+#ifdef GFXBOARD
+ gfxboard_hsync_handler();
+#endif
+#ifdef A2065
a2065_hsync_handler ();
#endif
#ifdef CD32
uae_ppc_hsync_handler();
cpuboard_hsync();
#endif
+#ifdef WITH_PCI
+ pci_hsync();
+#endif
#ifdef WITH_TOCCATA
sndboard_hsync();
#endif
_T("Picasso IV Zorro III"),
BOARD_MANUFACTURER_PICASSO, BOARD_MODEL_MEMORY_PICASSOIV, 0,
0x00000000, 0x00400000, 0x00400000, 0x04000000, CIRRUS_ID_CLGD5446, true, 2, false
+ },
+ {
+ _T("A2410"),
+ 1030, 0, 0,
+ 0x00000000, 0x00200000, 0x00200000, 0x00000000, 0,false, 2, false
}
};
bool gfxboard_toggle (int mode)
{
+ if (currprefs.rtgmem_type == GFXBOARD_A2410) {
+ return tms_toggle(mode);
+ }
+
if (vram == NULL)
return false;
if (monswitch_current) {
fullrefresh = 2;
}
+void gfxboard_hsync_handler(void)
+{
+ if (currprefs.rtgmem_type == GFXBOARD_A2410) {
+ tms_hsync_handler();
+ }
+}
+
void gfxboard_vsync_handler (void)
{
+ if (currprefs.rtgmem_type == GFXBOARD_A2410) {
+ tms_vsync_handler();
+ return;
+ }
+
if (!configured_mem || !configured_regs)
return;
#define EXPANSIONTYPE_24BIT 4
#define EXPANSIONTYPE_IDE_PORT_DOUBLED 8
#define EXPANSIONTYPE_SASI 16
-#define EXPANSIONTYPE_PCI_BRIDGE 32
-#define EXPANSIONTYPE_PARALLEL_ADAPTER 64
+#define EXPANSIONTYPE_CUSTOM 32
+#define EXPANSIONTYPE_PCI_BRIDGE 64
+#define EXPANSIONTYPE_PARALLEL_ADAPTER 128
struct expansionboardsettings
{
const TCHAR *name;
extern void gfxboard_free (void);
extern void gfxboard_reset (void);
extern void gfxboard_vsync_handler (void);
+extern void gfxboard_hsync_handler(void);
extern bool gfxboard_is_z3 (int);
extern bool gfxboard_is_registers (int);
extern int gfxboard_get_vram_min (int);
extern bool gfxboard_toggle (int mode);
extern int gfxboard_num_boards (int type);
+extern addrbank *tms_init(int devnum);
+extern void tms_hsync_handler(void);
+extern void tms_vsync_handler(void);
+extern bool tms_toggle(int);
+
#define GFXBOARD_UAE_Z2 0
#define GFXBOARD_UAE_Z3 1
#define GFXBOARD_HARDWARE 2
+
+#define GFXBOARD_PICASSO2 2
+#define GFXBOARD_PICASSO2PLUS 3
+#define GFXBOARD_PICCOLO_Z2 4
+#define GFXBOARD_PICCOLO_Z3 5
+#define GFXBOARD_SD64_Z2 6
+#define GFXBOARD_SD64_Z3 7
+#define GFXBOARD_SPECTRUM_Z2 8
+#define GFXBOARD_SPECTRUM_Z3 9
+#define GFXBOARD_PICASSO4_Z2 10
+#define GFXBOARD_PICASSO4_Z3 11
+#define GFXBOARD_A2410 12
shmaddr=natmem_offset + 0x00d00000;
size += BARRIER;
got = TRUE;
- } else if(!_tcscmp (shmids[shmid].name, _T("superiv_e0"))) {
- shmaddr=natmem_offset + 0x00e00000;
+ } else if (!_tcscmp(shmids[shmid].name, _T("superiv_e0"))) {
+ shmaddr = natmem_offset + 0x00e00000;
+ size += BARRIER;
+ got = TRUE;
+ } else if (!_tcscmp(shmids[shmid].name, _T("x_a0"))) {
+ shmaddr = natmem_offset + 0x00a00000;
size += BARRIER;
got = TRUE;
}