#define BLIZZARDMK3_MAPROM_BASE 0x1ef80000
#define BLIZZARD_MAPROM_ENABLE 0x80ffff00
#define BLIZZARD_BOARD_DISABLE 0x80fa0000
+#define BLIZZARD_BOARD_DISABLE2 0x80f00000
-#define CSMK2_BOARD_DISABLE 0x83000000
+#define CSMK2_2060_BOARD_DISABLE 0x83000000
static int cpuboard_size = -1, cpuboard2_size = -1;
static int configured;
{
return ISCPUBOARDP(p, BOARD_DCE, 0);
}
+static bool is_ivsvector(struct uae_prefs *p)
+{
+ return ISCPUBOARDP(p, BOARD_IVS, BOARD_IVS_VECTOR);
+}
static bool is_aca500(struct uae_prefs *p)
{
return ISCPUBOARDP(p, BOARD_IC, BOARD_IC_ACA500);
}
+extern addrbank cpuboardmem1_bank;
+MEMORY_FUNCTIONS(cpuboardmem1);
+static addrbank cpuboardmem1_bank = {
+ cpuboardmem1_lget, cpuboardmem1_wget, cpuboardmem1_bget,
+ cpuboardmem1_lput, cpuboardmem1_wput, cpuboardmem1_bput,
+ cpuboardmem1_xlate, cpuboardmem1_check, NULL, _T("*B"), _T("cpuboard ram"),
+ cpuboardmem1_lget, cpuboardmem1_wget,
+ ABFLAG_RAM | ABFLAG_THREADSAFE, 0, 0
+};
+extern addrbank cpuboardmem2_bank;
+MEMORY_FUNCTIONS(cpuboardmem2);
+static addrbank cpuboardmem2_bank = {
+ cpuboardmem2_lget, cpuboardmem2_wget, cpuboardmem2_bget,
+ cpuboardmem2_lput, cpuboardmem2_wput, cpuboardmem2_bput,
+ cpuboardmem2_xlate, cpuboardmem2_check, NULL, _T("*B"), _T("cpuboard ram #2"),
+ cpuboardmem2_lget, cpuboardmem2_wget,
+ ABFLAG_RAM | ABFLAG_THREADSAFE, 0, 0
+};
+
+
DECLARE_MEMORY_FUNCTIONS(blizzardio);
static addrbank blizzardio_bank = {
blizzardio_lget, blizzardio_wget, blizzardio_bget,
{
uae_u32 v = 0;
if (cpuboard_non_byte_ea) {
- v = blizzardea_bget(addr + 3) << 0;
- v |= blizzardea_bget(addr + 2) << 8;
+ v = blizzardea_bget(addr + 0) << 24;
v |= blizzardea_bget(addr + 1) << 16;
- v |= blizzardea_bget(addr + 0) << 24;
+ v |= blizzardea_bget(addr + 2) << 8;
+ v |= blizzardea_bget(addr + 3) << 0;
}
return v;
}
{
uae_u32 v = 0;
if (cpuboard_non_byte_ea) {
- v = blizzardea_bget(addr + 1) << 0;
- v |= blizzardea_bget(addr + 0) << 8;
+ v = blizzardea_bget(addr + 0) << 8;
+ v |= blizzardea_bget(addr + 1) << 0;
}
return v;
}
static void REGPARAM2 blizzardea_lput(uaecptr addr, uae_u32 l)
{
if (cpuboard_non_byte_ea) {
- blizzardea_bput(addr + 3, l >> 0);
- blizzardea_bput(addr + 2, l >> 8);
- blizzardea_bput(addr + 1, l >> 16);
blizzardea_bput(addr + 0, l >> 24);
+ blizzardea_bput(addr + 1, l >> 16);
+ blizzardea_bput(addr + 2, l >> 8);
+ blizzardea_bput(addr + 3, l >> 0);
}
}
static void REGPARAM2 blizzardea_wput(uaecptr addr, uae_u32 w)
{
if (cpuboard_non_byte_ea) {
- blizzardea_bput(addr + 1, w >> 0);
blizzardea_bput(addr + 0, w >> 8);
+ blizzardea_bput(addr + 1, w >> 0);
}
}
static void REGPARAM2 blizzardea_bput(uaecptr addr, uae_u32 b)
if((addr & 65535) == (BLIZZARD_BOARD_DISABLE & 65535)) {
if (v != 0xcafe)
return;
- write_log(_T("Blizzard: board disable!\n"));
- cpu_halt(CPU_HALT_ACCELERATOR_CPU_FALLBACK); // not much choice..
+ write_log(_T("Blizzard: fallback CPU!\n"));
+ cpu_fallback(0);
}
} else if (is_csmk3(&currprefs) || is_blizzardppc(&currprefs)) {
write_log(_T("CS IO WPUT %08x %04x\n"), addr, v);
- } else if (is_csmk2(&currprefs)) {
+ } else if (is_csmk2(&currprefs) || is_blizzard2060(&currprefs)) {
write_log(_T("CS IO WPUT %08x %04x\n"), addr, v);
- if (addr == CSMK2_BOARD_DISABLE) {
+ if (addr == CSMK2_2060_BOARD_DISABLE) {
if (v != 0xcafe)
return;
- write_log(_T("CSMK2: board disable!\n"));
- cpu_halt(CPU_HALT_ACCELERATOR_CPU_FALLBACK); // not much choice..
+ write_log(_T("CSMK2/2060: fallback CPU!\n"));
+ cpu_fallback(0);
}
}
}
{
if (!currprefs.cpuboard_type)
return;
+
+ bool fallback_cpu = currprefs.cpu_model < 68020;
+
if (is_blizzard1230mk2(&currprefs) || is_blizzard1230mk3(&currprefs)) {
map_banks(&blizzardram_bank, blizzardram_bank.start >> 16, cpuboard_size >> 16, 0);
map_banks(&blizzardio_bank, BLIZZARD_MAPROM_ENABLE >> 16, 65536 >> 16, 0);
}
}
if (is_blizzard(&currprefs) || is_blizzardppc(&currprefs)) {
- map_banks(&blizzardram_bank, blizzardram_bank.start >> 16, cpuboard_size >> 16, 0);
- if (!is_blizzardppc(&currprefs)) {
- if (cpuboard_size < 256 * 1024 * 1024)
- map_banks(&blizzardmaprom_bank, BLIZZARDMK4_MAPROM_BASE >> 16, 524288 >> 16, 0);
- map_banks(&blizzardf0_bank, 0xf00000 >> 16, 65536 >> 16, 0);
- map_banks(&blizzardio_bank, BLIZZARD_MAPROM_ENABLE >> 16, 65536 >> 16, 0);
- map_banks(&blizzardio_bank, BLIZZARD_BOARD_DISABLE >> 16, 65536 >> 16, 0);
+ if (!fallback_cpu) {
+ map_banks(&blizzardram_bank, blizzardram_bank.start >> 16, cpuboard_size >> 16, 0);
+ if (!is_blizzardppc(&currprefs)) {
+ if (cpuboard_size < 256 * 1024 * 1024)
+ map_banks(&blizzardmaprom_bank, BLIZZARDMK4_MAPROM_BASE >> 16, 524288 >> 16, 0);
+ map_banks(&blizzardf0_bank, 0xf00000 >> 16, 65536 >> 16, 0);
+ map_banks(&blizzardio_bank, BLIZZARD_MAPROM_ENABLE >> 16, 65536 >> 16, 0);
+ map_banks(&blizzardio_bank, BLIZZARD_BOARD_DISABLE >> 16, 65536 >> 16, 0);
+ map_banks(&blizzardio_bank, BLIZZARD_BOARD_DISABLE2 >> 16, 65536 >> 16, 0);
+ } else {
+ map_banks(&blizzardf0_bank, 0xf00000 >> 16, 0x60000 >> 16, 0);
+ map_banks(&blizzardio_bank, 0xf60000 >> 16, (2 * 65536) >> 16, 0);
+ blizzardppc_maprom();
+ }
} else {
- map_banks(&blizzardf0_bank, 0xf00000 >> 16, 0x60000 >> 16, 0);
- map_banks(&blizzardio_bank, 0xf60000 >> 16, (2 * 65536) >> 16, 0);
- blizzardppc_maprom();
+ map_banks(&dummy_bank, 0xf00000 >> 16, 0x80000 >> 16, 0);
}
}
if (is_csmk3(&currprefs)) {
cyberstorm_maprom();
}
if (is_csmk2(&currprefs)) {
- map_banks(&blizzardio_bank, 0x88000000 >> 16, 65536 >> 16, 0);
- map_banks(&blizzardio_bank, 0x83000000 >> 16, 65536 >> 16, 0);
- map_banks(&blizzardf0_bank, 0xf00000 >> 16, 65536 >> 16, 0);
- cyberstormmk2_maprom();
+ if (!fallback_cpu) {
+ map_banks(&blizzardio_bank, 0x88000000 >> 16, 65536 >> 16, 0);
+ map_banks(&blizzardio_bank, 0x83000000 >> 16, 65536 >> 16, 0);
+ map_banks(&blizzardf0_bank, 0xf00000 >> 16, 65536 >> 16, 0);
+ cyberstormmk2_maprom();
+ } else {
+ map_banks(&dummy_bank, 0xf00000 >> 16, 0x80000 >> 16, 0);
+ }
}
if (is_csmk1(&currprefs)) {
map_banks(&blizzardio_bank, 0x80f80000 >> 16, 65536 >> 16, 0);
map_banks(&blizzardmaprom_bank, 0x07f80000 >> 16, 524288 >> 16, 0);
}
if (is_blizzard2060(&currprefs)) {
- map_banks(&blizzardf0_bank, 0xf00000 >> 16, 65536 >> 16, 0);
- map_banks(&blizzardio_bank, 0x80000000 >> 16, 0x10000000 >> 16, 0);
- if (mapromconfigured())
- map_banks_nojitdirect(&blizzardmaprom_bank, (a3000hmem_bank.start + a3000hmem_bank.allocated - 524288) >> 16, 524288 >> 16, 0);
+ if (!fallback_cpu) {
+ map_banks(&blizzardf0_bank, 0xf00000 >> 16, 65536 >> 16, 0);
+ map_banks(&blizzardio_bank, 0x80000000 >> 16, 0x10000000 >> 16, 0);
+ if (mapromconfigured())
+ map_banks_nojitdirect(&blizzardmaprom_bank, (a3000hmem_bank.start + a3000hmem_bank.allocated - 524288) >> 16, 524288 >> 16, 0);
+ } else {
+ map_banks(&dummy_bank, 0xf00000 >> 16, 0x80000 >> 16, 0);
+ }
}
if (is_tekmagic(&currprefs)) {
map_banks(&blizzardf0_bank, 0xf00000 >> 16, 131072 >> 16, 0);
map_banks(&blizzardf0_bank, 0xa00000 >> 16, 524288 >> 16, 0);
map_banks(&blizzardio_bank, 0xb00000 >> 16, 262144 >> 16, 0);
}
+ if (is_ivsvector(&currprefs)) {
+ if (!currprefs.address_space_24) {
+ map_banks(&cpuboardmem1_bank, cpuboardmem1_bank.start >> 16, (0x04000000 - cpuboardmem1_bank.start) >> 16, cpuboardmem1_bank.allocated);
+ if (cpuboardmem2_bank.allocated)
+ map_banks(&cpuboardmem2_bank, cpuboardmem2_bank.start >> 16, (0x10000000 - cpuboardmem2_bank.start) >> 16, cpuboardmem2_bank.allocated);
+ }
+ }
+ if (is_mtec_ematrix530(&currprefs) || is_sx32pro(&currprefs)) {
+ if (cpuboardmem1_bank.allocated) {
+ map_banks(&cpuboardmem1_bank, cpuboardmem1_bank.start >> 16, cpuboardmem1_bank.allocated >> 16, 0);
+ }
+ }
}
void cpuboard_reset(void)
blizzardmaprom_bank.flags &= ~(ABFLAG_INDIRECT | ABFLAG_NOALLOC);
blizzardmaprom2_bank.flags &= ~(ABFLAG_INDIRECT | ABFLAG_NOALLOC);
+
+ mapped_free(&cpuboardmem1_bank);
+ mapped_free(&cpuboardmem2_bank);
}
static void cpuboard_init_2(void)
return;
cpuboard_size = currprefs.cpuboardmem1_size;
+ cpuboardmem1_bank.allocated = 0;
+ cpuboardmem2_bank.allocated = 0;
if (is_kupke(&currprefs) || is_mtec_ematrix530(&currprefs) || is_sx32pro(&currprefs)) {
// plain 64k autoconfig, nothing else.
blizzardea_bank.mask = blizzardea_bank.allocated - 1;
mapped_malloc(&blizzardea_bank);
+ if (is_mtec_ematrix530(&currprefs) || is_sx32pro(&currprefs)) {
+ cpuboardmem1_bank.start = 0x18000000 - cpuboard_size;
+ cpuboardmem1_bank.allocated = cpuboard_size;
+ cpuboardmem1_bank.mask = cpuboardmem1_bank.allocated - 1;
+ mapped_malloc(&cpuboardmem1_bank);
+ }
+
} else if (is_aca500(&currprefs)) {
blizzardf0_bank.start = 0x00f00000;
blizzardf0_bank.mask = blizzardf0_bank.allocated - 1;
mapped_malloc(&blizzardf0_bank);
+ } else if (is_ivsvector(&currprefs)) {
+
+ cpuboardmem1_bank.start = 0x02000000;
+ cpuboardmem1_bank.allocated = 32 * 1024 * 1024;
+ cpuboardmem1_bank.mask = cpuboardmem1_bank.allocated - 1;
+ mapped_malloc(&cpuboardmem1_bank);
+
+ cpuboardmem2_bank.start = 0x0c000000;
+ cpuboardmem2_bank.allocated = cpuboard_size;
+ cpuboardmem2_bank.mask = cpuboard_size - 1;
+ mapped_malloc(&cpuboardmem2_bank);
+
}
+
+ if (!cpuboardmem1_bank.baseaddr)
+ cpuboardmem1_bank.allocated = 0;
+ if (!cpuboardmem2_bank.baseaddr)
+ cpuboardmem2_bank.allocated = 0;
}
void cpuboard_init(void)
{
int b = cpuboard_memorytype(p);
if (p->cpuboard_type) {
+ if (cpuboards[p->cpuboard_type].subtypes[p->cpuboard_subtype].deviceflags & EXPANSIONTYPE_HAS_FALLBACK)
+ return false;
if (!(cpuboards[p->cpuboard_type].subtypes[p->cpuboard_subtype].deviceflags & EXPANSIONTYPE_24BIT))
return true;
}
b == BOARD_MEMORY_BLIZZARD_PPC ||
b == BOARD_MEMORY_Z3 ||
b == BOARD_MEMORY_25BITMEM ||
- b == BOARD_MEMORY_EMATRIX;
+ b == BOARD_MEMORY_CUSTOM_32;
}
int cpuboard_memorytype(struct uae_prefs *p)
// bit 3: unknown
// bit 4: 68000 mode
if (w & 0x10) {
- write_log(_T("A2630 68000 mode!\n"));
- cpu_halt(CPU_HALT_ACCELERATOR_CPU_FALLBACK);
+ write_log(_T("A2630 fallback CPU mode!\n"));
+ cpu_fallback(0);
}
return true;
}
case BOARD_IC:
break;
+ case BOARD_IVS:
+ switch (p->cpuboard_subtype)
+ {
+ case BOARD_IVS_VECTOR:
+ aci->addrbank = &expamem_null;
+ return true;
+ }
+ break;
+
case BOARD_COMMODORE:
switch(p->cpuboard_subtype)
{
}
cpuboard_non_byte_ea = true;
+
if (is_sx32pro(p)) {
earom_size = 65536;
for (int i = 0; i < 32768; i++) {
void do_leave_program (void)
{
+#ifdef WITH_PPC
+ // must be first
+ uae_ppc_free();
+#endif
free_traps();
sampler_free ();
graphics_leave ();
#ifdef WITH_LUA
uae_lua_free ();
#endif
-#ifdef WITH_PPC
- uae_ppc_free();
-#endif
#ifdef WITH_TOCCATA
sndboard_free();
uaesndboard_free();
return expamem_read(0) & 0xc0;
}
+void expansion_cpu_fallback(void)
+{
+ if (ecard < cardno) {
+ card_data *cd = cards[ecard];
+ if (cd->cst && (cd->cst->deviceflags & EXPANSIONTYPE_FALLBACK_DISABLE)) {
+ expamem_next(NULL, NULL);
+ }
+ }
+}
+
static void call_card_init(int index)
{
addrbank *ab, *abe;
struct autoconfig_info *aci = &cd->aci;
bool ok = false;
+ if (currprefs.address_space_24 && cd->cst && (cd->cst->deviceflags & EXPANSIONTYPE_FALLBACK_DISABLE)) {
+ expamem_next(NULL, NULL);
+ return;
+ }
+
expamem_bank.name = cd->name ? cd->name : _T("None");
aci->prefs = &currprefs;
aci->doinit = true;
expamem_bank_current = NULL;
return;
}
- if (ab == &expamem_null || ab == &expamem_nonautoconfig) {
+ if (ab == &expamem_null || ab == &expamem_nonautoconfig || cd->zorro < 1 || cd->zorro > 3) {
expamem_next(NULL, NULL);
return;
}
if (ecard >= cardno)
break;
struct card_data *ec = cards[ecard];
+ if (ec->zorro == 3 && ec->base == 0xffffffff) {
+ write_log(_T("Autoconfig chain enumeration aborted, 32-bit address space overflow.\n"));
+ ecard = cardno;
+ break;
+ }
if (ec->initrc && isnonautoconfig(ec->zorro)) {
struct autoconfig_info aci = { 0 };
aci.doinit = true;
return ab;
uae_u32 size = ab->allocated;
ab->start = start;
- if (ab->start) {
+ if (ab->start && size) {
map_banks_z2(ab, ab->start >> 16, size >> 16);
}
return ab;
* Zorro III expansion memory
*/
-static addrbank * expamem_map_z3fastmem (struct autoconfig_info *aci)
+static addrbank *expamem_map_z3fastmem (struct autoconfig_info *aci)
{
int devnum = aci->devnum;
addrbank *ab = &z3fastmem_bank[devnum];
uaecptr z3fs = expamem_board_pointer;
uae_u32 size = currprefs.z3fastmem[devnum].size;
- map_banks_z3(ab, z3fs >> 16, size >> 16);
+ if (ab->allocated)
+ map_banks_z3(ab, z3fs >> 16, size >> 16);
return ab;
}
uae_u32 start = bank->start;
bool alwaysmapz3 = aci->prefs->z3_mapping_mode != Z3MAPPING_REAL;
- if (alwaysmapz3 || expamem_z3hack(aci->prefs)) {
+ if ((alwaysmapz3 || expamem_z3hack(aci->prefs)) && bank->allocated) {
map_banks_z3(bank, start >> 16, size >> 16);
}
return true;
else
expamem_z3_size = 16 * 1024 * 1024;
- expamem_z3_pointer_real = (expamem_z3_pointer_real + expamem_z3_size - 1) & ~(expamem_z3_size - 1);
+ uaecptr newp = (expamem_z3_pointer_real + expamem_z3_size - 1) & ~(expamem_z3_size - 1);
+ if (newp < expamem_z3_pointer_real)
+ newp = 0xffffffff;
+ expamem_z3_pointer_real = newp;
expamem_board_pointer = expamem_z3hack(cd->aci.prefs) ? expamem_z3_pointer_uae : expamem_z3_pointer_real;
expamem_board_size = expamem_z3_size;
}
aci->zorro = cd->zorro;
if (cd->zorro == 3) {
- expamem_z3_pointer_real += expamem_board_size;
- expamem_z3_pointer_uae += expamem_board_size;
- expamem_board_pointer += expamem_board_size;
+ if (expamem_z3_pointer_real + expamem_board_size < expamem_z3_pointer_real) {
+ expamem_z3_pointer_real = 0xffffffff;
+ } else {
+ expamem_z3_pointer_real += expamem_board_size;
+ }
+ if (expamem_z3_pointer_uae + expamem_board_size < expamem_z3_pointer_uae) {
+ expamem_z3_pointer_uae = 0xffffffff;
+ } else {
+ expamem_z3_pointer_uae += expamem_board_size;
+ }
+ if (expamem_board_pointer + expamem_board_size < expamem_board_pointer) {
+ expamem_board_pointer = 0xffffffff;
+ } else {
+ expamem_board_pointer += expamem_board_size;
+ }
if ((type & add_memory) || aci->direct_vram) {
- if (expamem_z3_pointer_uae > expamem_z3_highram_uae)
+ if (expamem_z3_pointer_uae != 0xffffffff && expamem_z3_pointer_uae > expamem_z3_highram_uae)
expamem_z3_highram_uae = expamem_z3_pointer_uae;
- if (expamem_z3_pointer_real > expamem_z3_highram_real)
+ if (expamem_z3_pointer_real != 0xffffffff && expamem_z3_pointer_real > expamem_z3_highram_real)
expamem_z3_highram_real = expamem_z3_pointer_real;
}
false, false, 1
},
{ // 23 - 25
- _T("CPU Arch\0") _T("auto") _T("386\0") _T("386_prefetch\0") _T("386_slow\0") _T("486_slow\0") _T("486_prefetch\0") _T("pentium_slow\0"),
- _T("cpuarch\0") _T("auto") _T("386\0") _T("386_prefetch\0") _T("386_slow\0") _T("486_slow\0") _T("486_prefetch\0") _T("pentium_slow\0"),
+ _T("CPU Arch\0") _T("auto\0") _T("386\0") _T("386_prefetch\0") _T("386_slow\0") _T("486_slow\0") _T("486_prefetch\0") _T("pentium_slow\0"),
+ _T("cpuarch\0") _T("auto\0") _T("386\0") _T("386_prefetch\0") _T("386_slow\0") _T("486_slow\0") _T("486_prefetch\0") _T("pentium_slow\0"),
true, false, 0
},
{
_T("Blizzard 1230 IV"),
_T("Blizzard1230IV"),
ROMTYPE_CB_BLIZ1230, 0,
- NULL, 0,
+ NULL, EXPANSIONTYPE_FALLBACK_DISABLE | EXPANSIONTYPE_HAS_FALLBACK,
BOARD_MEMORY_BLIZZARD_12xx,
256 * 1024 * 1024,
0,
_T("Blizzard 1260"),
_T("Blizzard1260"),
ROMTYPE_CB_BLIZ1260, 0,
- NULL, 0,
+ NULL, EXPANSIONTYPE_FALLBACK_DISABLE | EXPANSIONTYPE_HAS_FALLBACK,
BOARD_MEMORY_BLIZZARD_12xx,
256 * 1024 * 1024,
0,
_T("Blizzard 2060"),
_T("Blizzard2060"),
ROMTYPE_CB_BLIZ2060, 0,
- cpuboard_ncr9x_add_scsi_unit, EXPANSIONTYPE_SCSI,
+ cpuboard_ncr9x_add_scsi_unit, EXPANSIONTYPE_SCSI | EXPANSIONTYPE_FALLBACK_DISABLE | EXPANSIONTYPE_HAS_FALLBACK,
BOARD_MEMORY_HIGHMEM,
128 * 1024 * 1024,
0,
_T("CyberStorm MK II"),
_T("CyberStormMK2"),
ROMTYPE_CB_CSMK2, 0,
- cpuboard_ncr9x_add_scsi_unit, EXPANSIONTYPE_SCSI,
+ cpuboard_ncr9x_add_scsi_unit, EXPANSIONTYPE_SCSI | EXPANSIONTYPE_FALLBACK_DISABLE | EXPANSIONTYPE_HAS_FALLBACK,
BOARD_MEMORY_HIGHMEM,
128 * 1024 * 1024
},
_T("e-matrix530"),
ROMTYPE_CB_EMATRIX, 0,
ematrix_add_scsi_unit, EXPANSIONTYPE_SCSI,
- BOARD_MEMORY_EMATRIX,
+ BOARD_MEMORY_CUSTOM_32,
128 * 1024 * 1024,
0,
ncr_ematrix_autoconfig_init, NULL, BOARD_AUTOCONFIG_Z2, 1,
NULL
}
};
+static const struct expansionboardsettings ivsvector_settings[] = {
+ {
+ // 0/1
+ _T("Memory (JP12)\0") _T("4M\0") _T("8M\0") _T("16M\0") _T("32M\0"),
+ _T("memory\0") _T("4m\0") _T("8m\0") _T("16m\0") _T("32m\0"),
+ true, false, 0
+ },
+ {
+ // 3
+ _T("Disable FastROM (JP17)"),
+ _T("disfastrom"),
+ false, false, 1
+ },
+ {
+ // 4
+ _T("Autoboot (JP20)"),
+ _T("autoboot"),
+ false, false, 0
+ },
+ {
+ // 5
+ _T("Dis68kRAM (JP14)"),
+ _T("dis68kram"),
+ false, false, 1
+ },
+ {
+ // 6
+ _T("Burst (JP13)"),
+ _T("burst"),
+ false, false, 1
+ },
+ {
+ NULL
+ }
+};
+
+
static const struct expansionboardsettings a26x0board_settings[] = {
{
_T("OSMODE (J304)"),
_T("Wildfire"),
_T("wildfire"),
ROMTYPE_CB_DBK_WF, 0,
- wildfire_add_scsi_unit, EXPANSIONTYPE_SCSI,
+ wildfire_add_scsi_unit, EXPANSIONTYPE_SCSI | EXPANSIONTYPE_HAS_FALLBACK,
BOARD_MEMORY_HIGHMEM,
128 * 1024 * 1024,
0,
NULL
}
};
+static const struct cpuboardsubtype ivs_sub[] = {
+ {
+ _T("Vector"),
+ _T("Vector"),
+ ROMTYPE_CB_VECTOR, 0,
+ ivsvector_add_scsi_unit, EXPANSIONTYPE_SCSI,
+ BOARD_MEMORY_HIGHMEM,
+ 32 * 1024 * 1024,
+ 0,
+ ivsvector_init, NULL, BOARD_AUTOCONFIG_Z2, 1,
+ ivsvector_settings, NULL,
+ 2112, 240, 0, false
+ },
+ {
+ NULL
+ }
+};
+
static const struct cpuboardsubtype apollo_sub[] = {
{
_T("Apollo 1240/1260"),
_T("sx32pro"),
ROMTYPE_CB_SX32PRO, 0,
NULL, 0,
- BOARD_MEMORY_EMATRIX,
+ BOARD_MEMORY_CUSTOM_32,
64 * 1024 * 1024
},
{
_T("RCS Management"),
fusionforty_sub, 0
},
+ {
+ BOARD_IVS,
+ _T("Interactive Video Systems"),
+ ivs_sub, 0
+ },
#if 0
{
BOARD_IC,
NULL
}
};
+
+const struct memoryboardtype memoryboards[]
+{
+ // z2
+ {
+ _T("GVP"), _T("Impact A2000-RAM8"),
+ 2, 2077, 9
+ },
+ {
+ _T("Kupke"), _T("Golem RAM-Card"),
+ 2, 2073, 3
+ },
+ {
+ _T("Supra"), _T("SupraRAM 500RX"),
+ 2, 1056, 10
+ },
+ {
+ _T("Supra"), _T("SupraRAM 2000"),
+ 2, 1056, 9
+ },
+ // z3
+ {
+ _T("E3B"), _T("ZorRAM"),
+ 3, 3643, 32
+ },
+
+ {
+ NULL
+ }
+};
\ No newline at end of file
#define EXPANSIONTYPE_FLOPPY 4096
#define EXPANSIONTYPE_NET 8192
#define EXPANSIONTYPE_INTERNAL 16384
+#define EXPANSIONTYPE_FALLBACK_DISABLE 32768
+#define EXPANSIONTYPE_HAS_FALLBACK 65536
+
struct expansionboardsettings
{
const TCHAR *name;
int defaultsubtype;
};
extern const struct cpuboardtype cpuboards[];
+struct memoryboardtype
+{
+ const TCHAR *man;
+ const TCHAR *name;
+ uae_u8 z;
+ uae_u16 manufacturer;
+ uae_u8 product;
+ uae_u8 autoconfig[16];
+};
+extern const struct memoryboardtype memoryboards[];
+
#endif /* UAE_AUTOCONF_H */
#define BOARD_MEMORY_BLIZZARD_12xx 4
#define BOARD_MEMORY_BLIZZARD_PPC 5
#define BOARD_MEMORY_25BITMEM 6
-#define BOARD_MEMORY_EMATRIX 7
+#define BOARD_MEMORY_CUSTOM_32 7
#define ISCPUBOARDP(p, type,subtype) (cpuboards[p->cpuboard_type].id == type && (type < 0 || p->cpuboard_subtype == subtype))
#define ISCPUBOARD(type,subtype) (cpuboards[currprefs.cpuboard_type].id == type && (type < 0 || currprefs.cpuboard_subtype == subtype))
#define BOARD_RCS 11
#define BOARD_RCS_SUB_FUSIONFORTY 0
-#define BOARD_IC 12
+#define BOARD_IVS 12
+#define BOARD_IVS_VECTOR 0
+
+#define BOARD_IC 13
#define BOARD_IC_ACA500 0
#endif /* UAE_CPUBOARD_H */
#ifndef UAE_MEMORY_H
#define UAE_MEMORY_H
-extern void memory_reset (void);
-extern void a1000_reset (void);
+extern void memory_reset(void);
+extern void memory_restore(void);
+extern void a1000_reset(void);
#ifdef JIT
extern int special_mem;
extern void rtarea_free(void);
extern void rtarea_init_mem(void);
extern void rtarea_setup(void);
-extern void expamem_init (void);
extern void expamem_reset (void);
extern void expamem_next (addrbank *mapped, addrbank *next);
extern void expamem_shutup (addrbank *mapped);
extern bool expamem_z3hack(struct uae_prefs*);
+extern void expansion_cpu_fallback(void);
extern void set_expamem_z3_hack_mode(int);
extern uaecptr expamem_board_pointer, expamem_highmem_pointer;
extern uaecptr expamem_z3_pointer_real, expamem_z3_pointer_uae;
#endif
extern void memory_init (void);
-extern void memory_cleanup (void);
+extern void memory_cleanup(void);
+extern void restore_banks(void);
extern void map_banks (addrbank *bank, int first, int count, int realsize);
extern void map_banks_z2(addrbank *bank, int first, int count);
extern void map_banks_z3(addrbank *bank, int first, int count);
extern void cpureset (void);
extern void cpu_halt (int id);
extern int cpu_sleep_millis(int ms);
+extern void cpu_change(int newmodel);
+extern void cpu_fallback(int mode);
extern void fill_prefetch (void);
extern void fill_prefetch_020 (void);
#endif
bool check_prefs_changed_comp (bool);
extern void flush_dcache (uaecptr, int);
-extern void flush_mmu (uaecptr, int);
extern int movec_illg (int regno);
extern uae_u32 val_move2c (int regno);
bool address_space_24;
bool picasso96_nocustom;
int picasso96_modeflags;
+ int cpu_model_fallback;
uae_u32 z3autoconfig_start;
struct ramboard z3fastmem[MAX_RAM_BOARDS];
uae_u8 apollo_scsi_bget(uaecptr addr);
void apollo_add_scsi_unit(int ch, struct uaedev_config_info *ci, struct romconfig *rc);
+void ivsvector_scsi_bput(uaecptr addr, uae_u8 v);
+uae_u8 ivsvector_scsi_bget(uaecptr addr);
+void ivsvector_add_scsi_unit(int ch, struct uaedev_config_info *ci, struct romconfig *rc);
+bool ivsvector_init(struct autoconfig_info *aci);
+
void soft_scsi_free(void);
void soft_scsi_reset(void);
p->fastmem[0].size = p->cpuboardmem1_size;
} else if (cpuboard_memorytype(p) == BOARD_MEMORY_25BITMEM) {
p->mem25bit_size = p->cpuboardmem1_size;
- } else if (cpuboard_memorytype(p) == BOARD_MEMORY_EMATRIX) {
- int size = p->cpuboardmem1_size / (1024 * 1024);
- if (size == 32 || size == 8 || size == 2) {
- p->custom_memory_sizes[0] = p->cpuboardmem1_size / 2;
- p->custom_memory_sizes[1] = p->cpuboardmem1_size / 2;
- p->custom_memory_addrs[0] = 0x18000000 - p->custom_memory_sizes[0];
- p->custom_memory_addrs[1] = 0x18000000;
- p->custom_memory_mask[0] = 0x10000000;
- p->custom_memory_mask[1] = 0x18000000;
- } else {
- p->custom_memory_sizes[0] = p->cpuboardmem1_size;
- p->custom_memory_sizes[1] = 0;
- p->custom_memory_addrs[0] = 0x18000000 - p->custom_memory_sizes[0];
- p->custom_memory_addrs[1] = 0;
- p->custom_memory_mask[0] = 0x10000000;
- p->custom_memory_mask[1] = 0;
- }
}
if (((p->chipmem_size & (p->chipmem_size - 1)) != 0 && p->chipmem_size != 0x180000)
bool rtgmem = (ab->flags & ABFLAG_RTG) != 0;
static int recurse;
- if (!_tcscmp(ab->label, _T("*"))) {
+ if (ab->label && ab->label[0] == '*') {
if (ab->start == 0 || ab->start == 0xffffffff) {
write_log(_T("mapped_malloc(*) without start address!\n"));
return false;
restore_roms();
}
+void memory_restore(void)
+{
+ last_address_space_24 = currprefs.address_space_24;
+ cpuboard_map();
+ map_banks_set(&kickmem_bank, 0xF8, 8, 0);
+}
+
void memory_reset (void)
{
int bnk, bnk_end;
}
#endif
+static addrbank *highram_temp_bank[65536 - 0x100];
+
+void restore_banks(void)
+{
+ for (int bnr = 0x100; bnr < 65536; bnr++) {
+ if (highram_temp_bank[bnr - 0x100]) {
+ map_banks(highram_temp_bank[bnr - 0x100], bnr, 1, 0);
+ } else {
+ map_banks(&dummy_bank, bnr, 1, 0);
+ }
+ }
+}
+
void map_banks (addrbank *bank, int start, int size, int realsize)
{
if (start == 0xffffffff)
return;
+ if (start >= 0x100) {
+ int real_left = 0;
+ for (int bnr = start; bnr < start + size; bnr++) {
+ highram_temp_bank[bnr - 0x100] = bank;
+ }
+ if (currprefs.address_space_24)
+ return;
+ }
map_banks2 (bank, start, size, realsize, 0);
#ifdef WITH_PPC
ppc_generate_map_banks(bank, start, size);
static struct cache040 icaches040[CACHESETS040];
static struct cache040 dcaches040[CACHESETS040];
+static int fallback_cpu_model, fallback_mmu_model, fallback_fpu_model;
+static int fallback_cpu_compatible, fallback_cpu_address_space_24;
+static struct regstruct fallback_regs;
+static int fallback_new_cpu_model;
+
int cpu_last_stop_vpos, cpu_stopped_lines;
#if COUNT_INSTRS
v = get_long (4);
m68k_areg (regs, 7) = get_long (0);
}
+
m68k_setpc_normal(v);
regs.m = 0;
regs.stopped = 0;
regs.ce020memcycles = 0;
fill_prefetch ();
}
+
void m68k_reset(void)
{
m68k_reset2(false);
}
+void cpu_change(int newmodel)
+{
+ if (newmodel == currprefs.cpu_model)
+ return;
+ fallback_new_cpu_model = newmodel;
+ cpu_halt(CPU_HALT_ACCELERATOR_CPU_FALLBACK);
+}
+
+void cpu_fallback(int mode)
+{
+ int fallbackmodel;
+ if (currprefs.chipset_mask & CSMASK_AGA) {
+ fallbackmodel = 68020;
+ } else {
+ fallbackmodel = 68000;
+ }
+ if (mode < 0) {
+ if (currprefs.cpu_model > fallbackmodel) {
+ cpu_change(fallbackmodel);
+ } else if (fallback_new_cpu_model) {
+ cpu_change(fallback_new_cpu_model);
+ }
+ } else if (mode == 0) {
+ cpu_change(fallbackmodel);
+ } else if (mode) {
+ if (fallback_cpu_model) {
+ cpu_change(fallback_cpu_model);
+ }
+ }
+}
+
+static void cpu_do_fallback(void)
+{
+ bool fallbackmode = false;
+ if ((fallback_new_cpu_model < 68020 && !(currprefs.chipset_mask & CSMASK_AGA)) || (fallback_new_cpu_model == 68020 && (currprefs.chipset_mask & CSMASK_AGA))) {
+ // -> 68000/68010 or 68EC020
+ fallback_cpu_model = currprefs.cpu_model;
+ fallback_fpu_model = currprefs.fpu_model;
+ fallback_mmu_model = currprefs.mmu_model;
+ fallback_cpu_compatible = currprefs.cpu_compatible;
+ fallback_cpu_address_space_24 = currprefs.address_space_24;
+ changed_prefs.cpu_model = currprefs.cpu_model_fallback && fallback_new_cpu_model <= 68020 ? currprefs.cpu_model_fallback : fallback_new_cpu_model;
+ changed_prefs.fpu_model = 0;
+ changed_prefs.mmu_model = 0;
+ changed_prefs.cpu_compatible = true;
+ changed_prefs.address_space_24 = true;
+ memcpy(&fallback_regs, ®s, sizeof(struct regstruct));
+ fallback_regs.pc = M68K_GETPC;
+ fallbackmode = true;
+ } else {
+ // -> 68020+
+ changed_prefs.cpu_model = fallback_cpu_model;
+ changed_prefs.fpu_model = fallback_fpu_model;
+ changed_prefs.mmu_model = fallback_mmu_model;
+ changed_prefs.cpu_compatible = fallback_cpu_compatible;
+ changed_prefs.address_space_24 = fallback_cpu_address_space_24;
+ fallback_cpu_model = 0;
+ }
+ init_m68k();
+ m68k_reset2(false);
+ if (!fallbackmode) {
+ // restore original 68020+
+ memcpy(®s, &fallback_regs, sizeof(regs));
+ restore_banks();
+ memory_restore();
+ memory_map_dump();
+ m68k_setpc(fallback_regs.pc);
+ } else {
+ memory_restore();
+ expansion_cpu_fallback();
+ memory_map_dump();
+ }
+}
+
+static void m68k_reset_restore(void)
+{
+ // hardreset and 68000/68020 fallback mode? Restore original mode.
+ if (fallback_cpu_model) {
+ fallback_new_cpu_model = fallback_cpu_model;
+ fallback_regs.pc = 0;
+ cpu_do_fallback();
+ }
+}
void REGPARAM2 op_unimpl (uae_u16 opcode)
{
if (regs.spcflags & SPCFLAG_CHECK) {
if (regs.halted) {
+ if (regs.halted == CPU_HALT_ACCELERATOR_CPU_FALLBACK) {
+ return 1;
+ }
unset_special(SPCFLAG_CHECK);
if (haltloop())
return 1;
cputrace.state = -1;
+ if (regs.halted == CPU_HALT_ACCELERATOR_CPU_FALLBACK) {
+ regs.halted = 0;
+ cpu_do_fallback();
+ }
+
if (currprefs.inprecfile[0] && input_play) {
inprec_open (currprefs.inprecfile, NULL);
changed_prefs.inprecfile[0] = currprefs.inprecfile[0] = 0;
else if (savestate_state == STATE_REWIND)
savestate_rewind ();
#endif
+ if (cpu_hardreset)
+ m68k_reset_restore();
prefs_changed_cpu();
set_cycles (start_cycles);
custom_reset (cpu_hardreset != 0, cpu_keyboardreset);
natmem_size = 0x80000000;
}
- write_log (_T("NATMEM: Total physical RAM %llu MB, all RAM %llu MB\n"),
+ write_log (_T("MMAN: Total physical RAM %llu MB, all RAM %llu MB\n"),
totalphys64 >> 20, total64 >> 20);
- write_log(_T("NATMEM: Attempting to reserve: %u MB\n"), natmem_size >> 20);
+ write_log(_T("MMAN: Attempting to reserve: %u MB\n"), natmem_size >> 20);
#if 1
natmem_reserved = (uae_u8 *) uae_vm_reserve(natmem_size, UAE_VM_32BIT | UAE_VM_WRITE_WATCH);
break;
natmem_size -= 64 * 1024 * 1024;
if (!natmem_size) {
- write_log (_T("Can't allocate 257M of virtual address space!?\n"));
+ write_log (_T("MMAN: Can't allocate 257M of virtual address space!?\n"));
natmem_size = 17 * 1024 * 1024;
natmem_reserved = (uae_u8*)VirtualAlloc (NULL, natmem_size, vaflags, PAGE_READWRITE);
if (!natmem_size) {
- write_log (_T("Can't allocate 17M of virtual address space!? Something is seriously wrong\n"));
+ write_log (_T("MMAN: Can't allocate 17M of virtual address space!? Something is seriously wrong\n"));
notify_user(NUMSG_NOMEMORY);
return false;
}
} else {
max_z3fastmem = natmem_size;
}
- write_log (_T("NATMEM: Reserved %p-%p (0x%08x %dM)\n"),
+ write_log (_T("MMAN: Reserved %p-%p (0x%08x %dM)\n"),
natmem_reserved, (uae_u8 *) natmem_reserved + natmem_reserved_size,
natmem_reserved_size, natmem_reserved_size / (1024 * 1024));
} else {
result = virtualallocwithlock (shmaddr, size, decommit ? MEM_DECOMMIT : MEM_COMMIT, PAGE_READWRITE);
if (result != shmaddr)
- write_log (_T("NATMEM: realloc(%p-%p,%d,%d,%s) failed, err=%d\n"), shmaddr, shmaddr + size, size, s->mode, s->name, GetLastError ());
+ write_log (_T("MMAN: realloc(%p-%p,%d,%d,%s) failed, err=%d\n"), shmaddr, shmaddr + size, size, s->mode, s->name, GetLastError ());
else
- write_log (_T("NATMEM: rellocated(%p-%p,%d,%s)\n"), shmaddr, shmaddr + size, size, s->name);
+ write_log (_T("MMAN: rellocated(%p-%p,%d,%s)\n"), shmaddr, shmaddr + size, size, s->name);
}
}
}
start_rtg = 0;
end_rtg = 0;
- int idx = 0;
- for (;;) {
- struct autoconfig_info *aci = expansion_get_autoconfig_data(&currprefs, idx++);
- if (!aci)
- break;
- if (!aci->addrbank)
- continue;
- if (aci->direct_vram) {
- if (!start_rtg)
- start_rtg = aci->start;
- end_rtg = aci->start + aci->size;
- }
- }
-
jit_direct_compatible_memory = currprefs.cachesize && (!currprefs.comptrustbyte || !currprefs.comptrustword || !currprefs.comptrustlong);
+ if (jit_direct_compatible_memory && expamem_z3_highram_uae > 0x80000000) {
+ write_log(_T("MMAN: RAM outside of 31-bit address space. Switching off JIT Direct.\n"));
+ jit_direct_compatible_memory = false;
+ }
// choose UAE if requested, blizzard or if jit direct and only UAE mode fits in natmem space.
- if (changed_prefs.z3_mapping_mode == Z3MAPPING_UAE || cpuboard_memorytype(&changed_prefs) == BOARD_MEMORY_BLIZZARD_12xx ||
+ if ((Z3BASE_UAE + changed_prefs.z3chipmem_size > Z3BASE_REAL && changed_prefs.z3_mapping_mode == Z3MAPPING_AUTO) ||
+ (jit_direct_compatible_memory && expamem_z3_highram_real > 0x80000000 && changed_prefs.z3_mapping_mode == Z3MAPPING_AUTO) ||
+ changed_prefs.z3_mapping_mode == Z3MAPPING_UAE || cpuboard_memorytype(&changed_prefs) == BOARD_MEMORY_BLIZZARD_12xx ||
(expamem_z3_highram_real + extra >= natmem_reserved_size && expamem_z3_highram_real < totalsize && changed_prefs.z3_mapping_mode == Z3MAPPING_AUTO && jit_direct_compatible_memory)) {
changed_prefs.z3autoconfig_start = currprefs.z3autoconfig_start = Z3BASE_UAE;
if (changed_prefs.z3_mapping_mode == Z3MAPPING_AUTO)
totalsize = expamem_z3_highram_real;
if (totalsize + extra >= natmem_reserved_size) {
jit_direct_compatible_memory = false;
- write_log(_T("NATMEM: Not enough direct memory for Z3REAL. Switching off JIT Direct.\n"));
+ write_log(_T("MMAN: Not enough direct memory for Z3REAL. Switching off JIT Direct.\n"));
}
}
+ if (jit_direct_compatible_memory && expamem_z3_highram_real > 0x80000000) {
+ write_log(_T("MMAN: RAM outside of 31-bit address space. Switching off JIT Direct.\n"));
+ jit_direct_compatible_memory = false;
+ }
}
write_log(_T("Total %uM, HM %uM\n"), totalsize >> 20, expamem_highmem_pointer >> 20);
if (jit_direct_compatible_memory && (totalsize > size64 || totalsize + extra >= natmem_reserved_size)) {
jit_direct_compatible_memory = false;
- write_log(_T("NATMEM: Not enough direct memory. Switching off JIT Direct.\n"));
+ write_log(_T("MMAN: Not enough direct memory. Switching off JIT Direct.\n"));
+ }
+
+ expansion_scan_autoconfig(&currprefs, true);
+
+ int idx = 0;
+ for (;;) {
+ struct autoconfig_info *aci = expansion_get_autoconfig_data(&currprefs, idx++);
+ if (!aci)
+ break;
+ if (!aci->addrbank)
+ continue;
+ if (aci->direct_vram) {
+ if (!start_rtg)
+ start_rtg = aci->start;
+ end_rtg = aci->start + aci->size;
+ }
}
// rtg outside of natmem?
if (end_rtg > natmem_reserved_size) {
if (jit_direct_compatible_memory) {
- write_log(_T("NATMEM: VRAM outside of natmem (%08x > %08x), switching off JIT Direct.\n"), end_rtg, natmem_reserved_size);
+ write_log(_T("MMAN: VRAM outside of natmem (%08x > %08x), switching off JIT Direct.\n"), end_rtg, natmem_reserved_size);
jit_direct_compatible_memory = false;
}
if (end_rtg - start_rtg > natmem_reserved_size) {
- write_log(_T("NATMEM: VRAMs don't fit in natmem space! (%08x > %08x)\n"), end_rtg - start_rtg, natmem_reserved_size);
+ write_log(_T("MMAN: VRAMs don't fit in natmem space! (%08x > %08x)\n"), end_rtg - start_rtg, natmem_reserved_size);
notify_user(NUMSG_NOMEMORY);
return -1;
}
+#ifdef _WIN64
+ // 64-bit can't do natmem_offset..
+ notify_user(NUMSG_NOMEMORY);
+ return -1;
+#else
p96base_offset = start_rtg;
p96mem_size = end_rtg - start_rtg;
- write_log("NATMEM: rtgbase_offset = %08x, size %08x\n", p96base_offset, p96mem_size);
+ write_log("MMAN: rtgbase_offset = %08x, size %08x\n", p96base_offset, p96mem_size);
// adjust p96mem_offset to beginning of natmem
// by subtracting start of original p96mem_offset from natmem_offset
if (p96base_offset >= 0x10000000) {
natmem_offset = natmem_reserved - p96base_offset;
p96mem_offset = natmem_offset + p96base_offset;
}
+#endif
} else {
start_rtg = 0;
end_rtg = 0;
}
- expansion_scan_autoconfig(&currprefs, true);
#if 0
z3offset = 0;
if (changed_prefs.z3_mapping_mode != Z3MAPPING_UAE && cpuboard_memorytype(&changed_prefs) != BOARD_MEMORY_BLIZZARD_12xx) {
#endif
if (!natmem_offset) {
- write_log (_T("NATMEM: No special area could be allocated! err=%d\n"), GetLastError ());
+ write_log (_T("MMAN: No special area could be allocated! err=%d\n"), GetLastError ());
} else {
- write_log(_T("NATMEM: Our special area: %p-%p (0x%08x %dM)\n"),
+ write_log(_T("MMAN: Our special area: %p-%p (0x%08x %dM)\n"),
natmem_offset, (uae_u8*)natmem_offset + totalsize,
totalsize, totalsize / (1024 * 1024));
#if 0
uaecptr start;
uae_u32 size = ab->allocated;
uae_u32 readonlysize = size;
+ bool barrier = false;
if (!_tcscmp(ab->label, _T("*"))) {
start = ab->start;
got = true;
if (expansion_get_autoconfig_by_address(&currprefs, ab->start) && !expansion_get_autoconfig_by_address(&currprefs, ab->start + size))
- size += BARRIER;
+ barrier = true;
+ } else if (!_tcscmp(ab->label, _T("*B"))) {
+ start = ab->start;
+ got = true;
+ barrier = true;
} else if (!_tcscmp(ab->label, _T("chip"))) {
start = 0;
got = true;
if (!expansion_get_autoconfig_by_address(&currprefs, 0x00200000) || currprefs.chipmem_size < 2 * 1024 * 1024)
- size += BARRIER;
+ barrier = true;
} else if (!_tcscmp(ab->label, _T("kick"))) {
start = 0xf80000;
got = true;
- size += BARRIER;
+ barrier = true;
readonly = true;
maprom = true;
} else if (!_tcscmp(ab->label, _T("rom_a8"))) {
} else if (!_tcscmp(ab->label, _T("ramsey_low"))) {
start = a3000lmem_bank.start;
if (!a3000hmem_bank.start)
- size += BARRIER;
+ barrier = true;
got = true;
} else if (!_tcscmp(ab->label, _T("csmk1_maprom"))) {
start = 0x07f80000;
start = 0x00C00000;
got = true;
if (currprefs.bogomem_size <= 0x100000)
- size += BARRIER;
+ barrier = true;
} else if (!_tcscmp(ab->label, _T("custmem1"))) {
start = currprefs.custom_memory_addrs[0];
got = true;
got = true;
} else if (!_tcscmp(ab->label, _T("arhrtmon"))) {
start = 0x00800000;
- size += BARRIER;
+ barrier = true;
got = true;
} else if (!_tcscmp(ab->label, _T("xpower_e2"))) {
start = 0x00e20000;
- size += BARRIER;
+ barrier = true;
got = true;
} else if (!_tcscmp(ab->label, _T("xpower_f2"))) {
start = 0x00f20000;
- size += BARRIER;
+ barrier = true;
got = true;
} else if (!_tcscmp(ab->label, _T("nordic_f0"))) {
start = 0x00f00000;
- size += BARRIER;
+ barrier = true;
got = true;
} else if (!_tcscmp(ab->label, _T("nordic_f4"))) {
start = 0x00f40000;
- size += BARRIER;
+ barrier = true;
got = true;
} else if (!_tcscmp(ab->label, _T("nordic_f6"))) {
start = 0x00f60000;
- size += BARRIER;
+ barrier = true;
got = true;
} else if (!_tcscmp(ab->label, _T("superiv_b0"))) {
start = 0x00b00000;
- size += BARRIER;
+ barrier = true;
got = true;
} else if (!_tcscmp(ab->label, _T("superiv_d0"))) {
start = 0x00d00000;
- size += BARRIER;
+ barrier = true;
got = true;
} else if (!_tcscmp(ab->label, _T("superiv_e0"))) {
start = 0x00e00000;
- size += BARRIER;
+ barrier = true;
got = true;
} else if (!_tcscmp(ab->label, _T("ram_a8"))) {
start = 0x00a80000;
- size += BARRIER;
+ barrier = true;
got = true;
}
if (got) {
directsupport = false;
}
md->directsupport = directsupport;
+ if (barrier)
+ md->size += BARRIER;
}
return got;
}
#define IDC_CPUBOARDMEM 1843
#define IDC_Z3MAPPING 1844
#define IDC_CPUBOARD_SUBTYPE 1845
-#define IDC_Z3MAPPING2 1845
#define IDC_MEMORYSELECT 1845
#define IDC_CYCLEEXACTMEMORY 1846
+#define IDC_MEMORYBOARDSELECT 1846
#define IDC_UAEBOARD_TYPE 1848
#define IDC_AUTOCONFIG_MANUFACTURER 1849
#define IDC_AUTOCONFIG_PRODUCT 1850
GROUPBOX "Advanced Memory Settings",IDC_STATIC,1,128,393,115
CONTROL "",IDC_MEMORYMEM,"msctls_trackbar32",TBS_AUTOTICKS | TBS_TOP | WS_TABSTOP,253,145,68,20
EDITTEXT IDC_MEMORYRAM,328,148,40,12,ES_CENTER | ES_READONLY
- RTEXT "Z3 mapping mode:",IDC_STATIC,162,218,93,15,SS_CENTERIMAGE
- COMBOBOX IDC_Z3MAPPING,262,218,117,75,CBS_DROPDOWNLIST | WS_VSCROLL | WS_TABSTOP
+ LTEXT "Z3 mapping mode:",IDC_STATIC,263,194,115,15,SS_CENTERIMAGE
+ COMBOBOX IDC_Z3MAPPING,262,216,117,75,CBS_DROPDOWNLIST | WS_VSCROLL | WS_TABSTOP
COMBOBOX IDC_MEMORYSELECT,14,151,228,75,CBS_DROPDOWNLIST | WS_VSCROLL | WS_TABSTOP
EDITTEXT IDC_AUTOCONFIG_MANUFACTURER,78,175,45,13,ES_AUTOHSCROLL
EDITTEXT IDC_AUTOCONFIG_PRODUCT,196,175,45,13,ES_AUTOHSCROLL
RTEXT "Manufacturer",IDC_STATIC,12,175,57,15,SS_CENTERIMAGE
RTEXT "Product",IDC_STATIC,133,175,55,15,SS_CENTERIMAGE
RTEXT "Autoconfig data",IDC_STATIC,11,195,57,15,SS_CENTERIMAGE
- CONTROL "Edit Autoconfig data",IDC_FASTMEMAUTOCONFIGUSE,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,276,196,103,10
+ CONTROL "Edit Autoconfig data",IDC_FASTMEMAUTOCONFIGUSE,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,261,177,103,8
+ RTEXT "Memory board",IDC_STATIC,15,216,53,15,SS_CENTERIMAGE
+ COMBOBOX IDC_MEMORYBOARDSELECT,77,216,165,75,CBS_DROPDOWNLIST | WS_VSCROLL | WS_TABSTOP
END
IDD_CPU DIALOGEX 0, 0, 396, 317
COMBOBOX IDC_EXPANSIONBOARDSELECTOR,202,76,171,75,CBS_DROPDOWNLIST | CBS_AUTOHSCROLL | WS_VSCROLL | WS_TABSTOP
COMBOBOX IDC_ACCELERATORBOARDITEMSELECTOR,12,169,157,75,CBS_DROPDOWNLIST | CBS_AUTOHSCROLL | WS_VSCROLL | WS_TABSTOP
CONTROL "",IDC_ACCELERATORBOARDCHECKBOX,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,202,170,99,12
- COMBOBOX IDC_ACCELERATORBOARDSELECTOR,202,146,171,75,CBS_DROPDOWNLIST | CBS_AUTOHSCROLL | WS_VSCROLL | WS_TABSTOP
+ COMBOBOX IDC_ACCELERATORBOARDSELECTOR,202,169,171,75,CBS_DROPDOWNLIST | CBS_AUTOHSCROLL | WS_VSCROLL | WS_TABSTOP
CONTROL "NE2000 PCMCIA",IDC_NE2000PCMCIA,"Button",BS_AUTOCHECKBOX | WS_TABSTOP,6,232,187,11
END
"PPC native OS booted with incompatible UAE boot ROM enabled.\nSelect ROM panel ""New UAE (128k, ROM, Indirect)"" option\nor disable all UAE expansions.\n"
IDS_AUTOSCALE_OVERSCAN_BLANK "Overscan blanking"
IDS_SCREEN_ADAPTIVE_SYNC "Variable Sync"
- IDS_NUMSG_NOMEMORY "Out of memory or too much Z3 autoconfig space configured."
+ IDS_NUMSG_NOMEMORY "Out of memory or too much Z3 autoconfig space configured.\nIf 64-bit, make sure RTG board is first in board list."
END
#endif // English resources
#define LANG_DLL_FULL_VERSION_MATCH 1
#if WINUAEPUBLICBETA
-#define WINUAEBETA _T("3")
+#define WINUAEBETA _T("4")
#else
#define WINUAEBETA _T("")
#endif
-#define WINUAEDATE MAKEBD(2016, 8, 28)
+#define WINUAEDATE MAKEBD(2016, 8, 31)
//#define WINUAEEXTRA _T("AmiKit Preview")
//#define WINUAEEXTRA _T("Amiga Forever Edition")
ew (hDlg, IDC_Z3MAPPING, z3);
ew (hDlg, IDC_FASTTEXT, true);
- bool isfast = fastram_select < 2 * MAX_RAM_BOARDS;
+ bool isfast = fastram_select < 2 * MAX_RAM_BOARDS && fastram_select_ramboard && fastram_select_ramboard->size;
ew(hDlg, IDC_AUTOCONFIG_MANUFACTURER, isfast);
ew(hDlg, IDC_AUTOCONFIG_PRODUCT, isfast);
- ew(hDlg, IDC_AUTOCONFIG_DATA, fastram_select_ramboard && fastram_select_ramboard->autoconfig_inuse);
+ ew(hDlg, IDC_MEMORYBOARDSELECT, isfast);
+ ew(hDlg, IDC_AUTOCONFIG_DATA, fastram_select_ramboard && fastram_select_ramboard->autoconfig_inuse && fastram_select_ramboard->size);
ew(hDlg, IDC_FASTMEMAUTOCONFIGUSE, isfast);
ew(hDlg, IDC_MEMORYRAM, true);
ew(hDlg, IDC_MEMORYMEM, true);
}
+static void setfastram_ramboard(HWND hDlg, int zram)
+{
+ if (!fastram_select_ramboard)
+ return;
+ int idx = 0;
+ for (int i = 0; memoryboards[i].name; i++) {
+ const struct memoryboardtype *mbt = &memoryboards[i];
+ if (mbt->z == zram) {
+ if (mbt->manufacturer == fastram_select_ramboard->manufacturer && mbt->product == fastram_select_ramboard->product) {
+ SendDlgItemMessage(hDlg, IDC_MEMORYBOARDSELECT, CB_SETCURSEL, idx, 0);
+ break;
+ }
+ idx++;
+ }
+ }
+}
+
+
static void setfastram_selectmenu(HWND hDlg, int mode)
{
int min;
int max;
const int *msi;
TCHAR tmp[200];
+ int zram = 0;
+ struct ramboard *fastram_select_ramboard_old = fastram_select_ramboard;
fastram_select_ramboard = NULL;
if (fastram_select < MAX_RAM_BOARDS) {
max = MAX_FAST_MEM;
fastram_select_ramboard = &workprefs.fastmem[fastram_select];
fastram_select_pointer = &fastram_select_ramboard->size;
+ zram = 2;
} else if (fastram_select >= MAX_RAM_BOARDS && fastram_select < MAX_RAM_BOARDS * 2) {
msi = msi_z3fast;
min = MIN_Z3_MEM;
max = MAX_Z3_MEM;
fastram_select_ramboard = &workprefs.z3fastmem[fastram_select - MAX_RAM_BOARDS];
fastram_select_pointer = &fastram_select_ramboard->size;
+ zram = 3;
} else if (fastram_select == 2 * MAX_RAM_BOARDS) {
min = 0;
max = MAX_CB_MEM_128M;
expansion_generate_autoconfig_info(&workprefs);
struct ramboard *rb = fastram_select_ramboard;
if (rb) {
+ if (fastram_select_ramboard_old != fastram_select_ramboard || mode < 0) {
+ if (zram) {
+ ew(hDlg, IDC_MEMORYBOARDSELECT, TRUE);
+ SendDlgItemMessage(hDlg, IDC_MEMORYBOARDSELECT, CB_RESETCONTENT, 0, 0);
+ for (int i = 0; memoryboards[i].name; i++) {
+ const struct memoryboardtype *mbt = &memoryboards[i];
+ if (mbt->z == zram) {
+ _stprintf(tmp, _T("%s %s"), memoryboards[i].man, memoryboards[i].name);
+ SendDlgItemMessage(hDlg, IDC_MEMORYBOARDSELECT, CB_ADDSTRING, 0, (LPARAM)tmp);
+ }
+ }
+ } else {
+ SendDlgItemMessage(hDlg, IDC_MEMORYBOARDSELECT, CB_RESETCONTENT, 0, 0);
+ ew(hDlg, IDC_MEMORYBOARDSELECT, FALSE);
+ }
+ }
+
struct autoconfig_info *aci = expansion_get_autoconfig_info(&workprefs, fastram_select < MAX_RAM_BOARDS ? ROMTYPE_RAMZ2 : ROMTYPE_RAMZ3, fastram_select % MAX_RAM_BOARDS);
if (!rb->autoconfig_inuse) {
if (aci) {
SetDlgItemText(hDlg, IDC_AUTOCONFIG_PRODUCT, _T(""));
}
}
+ setfastram_ramboard(hDlg, zram);
+
} else {
SetDlgItemText(hDlg, IDC_AUTOCONFIG_MANUFACTURER, _T(""));
SetDlgItemText(hDlg, IDC_AUTOCONFIG_PRODUCT, _T(""));
SendDlgItemMessage(hDlg, IDC_Z3MAPPING, CB_ADDSTRING, 0, (LPARAM)_T("Real (0x40000000)"));
SendDlgItemMessage (hDlg, IDC_Z3MAPPING, CB_SETCURSEL, workprefs.z3_mapping_mode, 0);
- setfastram_selectmenu(hDlg, 0);
+ setfastram_selectmenu(hDlg, -1);
recursive--;
setfastram_selectmenu(hDlg, 0);
}
break;
+ case IDC_MEMORYBOARDSELECT:
+ if (fastram_select_ramboard) {
+ v = SendDlgItemMessage(hDlg, IDC_MEMORYBOARDSELECT, CB_GETCURSEL, 0, 0L);
+ if (v != CB_ERR) {
+ int idx = 0;
+ for (int i = 0; memoryboards[i].name; i++) {
+ const struct memoryboardtype *mbt = &memoryboards[i];
+ if ((fastram_select < MAX_RAM_BOARDS && mbt->z == 2) || (fastram_select >= MAX_RAM_BOARDS && mbt->z == 3)) {
+ if (idx == v) {
+ fastram_select_ramboard->manufacturer = mbt->manufacturer;
+ fastram_select_ramboard->product = mbt->product;
+ setfastram_selectmenu(hDlg, 0);
+ break;
+ }
+ idx++;
+ }
+ }
+ }
+ }
+ break;
}
} else if (HIWORD(wParam) == EN_CHANGE) {
switch (LOWORD(wParam))
<?xml version="1.0" encoding="utf-8"?>
<Project DefaultTargets="Build" ToolsVersion="14.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
- <Import Project="packages\VisualCppTools.14.0.24419-Pre\build\native\VisualCppTools.props" Condition="Exists('packages\VisualCppTools.14.0.24419-Pre\build\native\VisualCppTools.props')" />
<ItemGroup Label="ProjectConfigurations">
<ProjectConfiguration Include="Debug|Win32">
<Configuration>Debug</Configuration>
<LibraryPath Condition="'$(Configuration)|$(Platform)'=='Test|x64'">C:\Program Files %28x86%29\Microsoft DirectX SDK %28June 2010%29\Lib\x64;C:\dev\lib\x64;$(LibraryPath)</LibraryPath>
<IncludePath Condition="'$(Configuration)|$(Platform)'=='FullRelease|x64'">C:\Program Files %28x86%29\Microsoft DirectX SDK %28June 2010%29\Include;C:\dev\include;$(IncludePath)</IncludePath>
<LibraryPath Condition="'$(Configuration)|$(Platform)'=='FullRelease|x64'">C:\Program Files %28x86%29\Microsoft DirectX SDK %28June 2010%29\Lib\x64;C:\dev\lib\x64;$(LibraryPath)</LibraryPath>
- <NuGetPackageImportStamp>7b625af1</NuGetPackageImportStamp>
</PropertyGroup>
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Test|x64'">
<IgnoreImportLibrary>
</Midl>
<ClCompile>
<Optimization>Full</Optimization>
- <InlineFunctionExpansion>AnySuitable</InlineFunctionExpansion>
+ <InlineFunctionExpansion>OnlyExplicitInline</InlineFunctionExpansion>
<IntrinsicFunctions>true</IntrinsicFunctions>
<FavorSizeOrSpeed>Speed</FavorSizeOrSpeed>
<OmitFramePointers>true</OmitFramePointers>
</Midl>
<ClCompile>
<Optimization>Full</Optimization>
- <InlineFunctionExpansion>AnySuitable</InlineFunctionExpansion>
+ <InlineFunctionExpansion>OnlyExplicitInline</InlineFunctionExpansion>
<IntrinsicFunctions>true</IntrinsicFunctions>
<FavorSizeOrSpeed>Speed</FavorSizeOrSpeed>
<OmitFramePointers>true</OmitFramePointers>
<None Include="..\resources\move_up.ico" />
<None Include="..\resources\paths.ico" />
<None Include="..\resources\port.ico" />
- <None Include="packages.config" />
<None Include="port.ico" />
<None Include="..\resources\quickstart.ico" />
<None Include="..\resources\root.ico" />
</ItemGroup>
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
<ImportGroup Label="ExtensionTargets" />
- <Target Name="EnsureNuGetPackageBuildImports" BeforeTargets="PrepareForBuild">
- <PropertyGroup>
- <ErrorText>This project references NuGet package(s) that are missing on this computer. Use NuGet Package Restore to download them. For more information, see http://go.microsoft.com/fwlink/?LinkID=322105. The missing file is {0}.</ErrorText>
- </PropertyGroup>
- <Error Condition="!Exists('packages\VisualCppTools.14.0.24419-Pre\build\native\VisualCppTools.props')" Text="$([System.String]::Format('$(ErrorText)', 'packages\VisualCppTools.14.0.24419-Pre\build\native\VisualCppTools.props'))" />
- </Target>
</Project>
\ No newline at end of file
<None Include="..\resources\drive_spin.wav" />
<None Include="..\resources\drive_spinnd.wav" />
<None Include="..\resources\drive_startup.wav" />
- <None Include="packages.config" />
</ItemGroup>
<ItemGroup>
<ResourceCompile Include="..\resources\winuae.rc">
\r
+Beta 4:\r
+\r
+- Fixed uaegfx 8-bit mode palette updates.\r
+- Added A2630 v4 to ROM scanner. (v2, v3 and v5 to go)\r
+- Force UAE mapping mode if 1G Z3 Chip RAM size.\r
+- Do not map Z3 RAM (and crash) if RAM allocation fails.\r
+- Improved some "Too much RAM" edge cases when deciding UAE/REAL mode and if JIT direct supported.\r
+- cpuboard_settings config entry wasn't loaded correctly if it had any multiselect options.\r
+- Added IVS Vector accelerator board emulation.\r
+- Added support for accelerator 68000 mode fallback, IVS Vector has different boot menu logo in 68000 mode :)\r
+ (It is not possible to boot directly in 68000 mode, IVS Vector boot code needs to initialize first in 68030\r
+ before menu in 68000 mode will work)\r
+- Blizzard 1230/1260/2060 68EC020 fallback mode supported. Hard reset restores original CPU configuration.\r
+ Very pointless but IVS Vector support code already handles it.\r
+- Stop PPC emulation first, before freeing any emulation resources to prevent random crashes at exit.\r
+- Added some predefined autoconfig RAM board choices. Few popular options copypasted from amiga.resource.cx. More later..\r
+\r
+IVS Vector:\r
+\r
+- 4.14 ROM added. ("Vector Driver 4.14 - ROM IMAGE IVSSCSI 4.14 (02 SEP 1992)")\r
+- Same SCSI hardware as IVS Trumpcard Pro. (53C80, fake dma etc..)\r
+- Main RAM is jumper selected (4/8/16/32, Accelerator select menu option selects main RAM size)\r
+- Supports A2630 RAM expansion (Accelerator RAM slider selects A2630 RAM size)\r
+- Most jumpers emulated.\r
+- MapROM (FastROM) hardware is not emulated.\r
+- 68000 mode Z2 RAM options not emulated. (Just use normal UAE RAM sliders if you want matching config)\r
+- Right mouse button = boot menu.\r
+
Beta 3:\r
\r
- PCI ES1370 fixed.\r
} else if (addr == 8) {
pcib->config[2] = b;
if (b & 1) {
- write_log(_T("Wildfire 68000 mode!\n"));
- cpu_halt(CPU_HALT_ACCELERATOR_CPU_FALLBACK);
+ write_log(_T("Wildfire fallback CPU mode!\n"));
+ cpu_fallback(0);
}
}
}
projects / francis / winuae.git / commitdiff