return;
interrupt_cycle_cnt -= cycles;
if (interrupt_cycle_cnt <= 0) {
- regs.ipl_pin = 1;
- interrupt_level = 1;
+ regs.ipl_pin = IPL_TEST_IPL_LEVEL;
+ interrupt_level = regs.ipl_pin;
interrupt_cycle_cnt = 0;
}
}
*isconstant = -1;
} else {
put_word_test(pc, imm16_cnt);
- imm16_cnt += 0x100; // STOP hack
+ if (dp->mnemo == i_STOP && feature_interrupts > 0) {
+ // STOP hack to keep STOP test size smaller.
+ imm16_cnt += 0x0100;
+ }
if (imm16_cnt == 0)
*isconstant = 0;
else
int cnt = 2;
uaecptr first_pc = regs.pc;
uae_u32 loop_mode_reg = 0;
+
if (feature_loop_mode_68010) {
// 68010 loop mode
cnt = (feature_loop_mode_cnt + 1) * 2;
#define INTERRUPT_CYCLES 64
#define MAX_INTERRUPT_DELAY 64
#define IPL_TRIGGER_ADDR 0xdc0000
+#define IPL_TEST_IPL_LEVEL 4
; 1 = interrupt request is set before test.
; Tests all INTREQ bits one by one. Compatible with cycle count mode.
; 2 = test CPU IPL sampling timing.
+; 3 = 2 + Set T1 immediately before test instruction
; Uses serial port to generate timing interrupt. Requires serial port TX connected to RX.
; Generates multiple extra tests.
; Used delay instruction: ROL.L D0,D0 (D0 = number of CPU clocks * 2)
verbose=0
feature_undefined_ccr=1
feature_interrupts=2
+;feature_sr_mask=0x2100
mode=all
; interrupt exception