struct audio_channel_data
{
- unsigned int evtime;
+ uae_u32 evtime;
bool dmaenstore;
bool intreq2;
int irqcheck;
skip = 0;
}
#endif
+
+#if 0
+ if (vpos == 300 && get_cycles() < 312 * 227 * CYCLE_UNIT)
+ activate_debugger();
+#endif
}
static bool vsync_line;
{
int i;
- nextevent = 0;
+ nextevent = EVT_MAX;
for (i = 0; i < ev_max; i++) {
eventtab[i].active = 0;
eventtab[i].oldcycles = get_cycles();
write_log(_T("Reset at %08X. Chipset mask = %08X\n"), M68K_GETPC, currprefs.chipset_mask);
memory_map_dump();
+ bool ntsc = currprefs.ntscmode;
+
lightpen_active = 0;
lightpen_triggered = 0;
lightpen_cx[0] = lightpen_cy[0] = -1;
display_reset = 1;
if (hardreset || savestate_state) {
- bool ntsc = currprefs.ntscmode;
maxhpos = ntsc ? MAXHPOS_NTSC : MAXHPOS_PAL;
maxhpos_short = ntsc ? MAXHPOS_NTSC : MAXHPOS_PAL;
maxvpos = ntsc ? MAXVPOS_NTSC : MAXVPOS_PAL;
blt_info.blit_queued = 0;
init_sprites();
- maxhpos = MAXHPOS_PAL;
+ maxhpos = ntsc ? MAXHPOS_NTSC : MAXHPOS_PAL;
maxhpos_short = maxhpos;
updateextblk();
}
addr &= 0xfff;
switch (addr & 0x1fe) {
- case 0x002: v = DMACONR (hpos); break;
- case 0x004: v = VPOSR (); break;
- case 0x006: v = VHPOSR (); break;
-
- case 0x00A: v = JOY0DAT (); break;
- case 0x00C: v = JOY1DAT (); break;
- case 0x00E: v = CLXDAT (hpos); break;
- case 0x010: v = ADKCONR (); break;
-
- case 0x012: v = POT0DAT (); break;
- case 0x014: v = POT1DAT (); break;
- case 0x016: v = POTGOR (); break;
- case 0x018: v = SERDATR (); break;
- case 0x01A: v = DSKBYTR (hpos); break;
- case 0x01C: v = INTENAR (); break;
- case 0x01E: v = INTREQR (); break;
+ case 0x002: v = DMACONR(hpos); break;
+ case 0x004: v = VPOSR(); break;
+ case 0x006: v = VHPOSR(); break;
+
+ case 0x00A: v = JOY0DAT(); break;
+ case 0x00C: v = JOY1DAT(); break;
+ case 0x00E: v = CLXDAT(hpos); break;
+ case 0x010: v = ADKCONR(); break;
+
+ case 0x012: v = POT0DAT(); break;
+ case 0x014: v = POT1DAT(); break;
+ case 0x016: v = POTGOR(); break;
+ case 0x018: v = SERDATR(); break;
+ case 0x01A: v = DSKBYTR(hpos); break;
+ case 0x01C: v = INTENAR(); break;
+ case 0x01E: v = INTREQR(); break;
case 0x07C:
- v = DENISEID (&missing);
+ v = DENISEID(&missing);
if (missing)
goto writeonly;
break;
case 0x1BC: case 0x1BE:
if (!aga_mode)
goto writeonly;
- v = COLOR_READ ((addr & 0x3E) / 2);
+ v = COLOR_READ((addr & 0x3E) / 2);
break;
#endif
v |= custom_wget2(addr + 2, false) >> 8;
return v;
}
- return custom_wget2 (addr, false);
+ return custom_wget2(addr, false);
}
static uae_u32 REGPARAM2 custom_bget(uaecptr addr)
if ((addr & 0xffff) < 0x8000 && currprefs.cs_fatgaryrev >= 0)
return dummy_get(addr, 1, false, 0);
debug_invalid_reg(addr, 1, 0);
- v = custom_wget2 (addr & ~1, true);
+ v = custom_wget2(addr & ~1, true);
v >>= (addr & 1 ? 0 : 8);
return v;
}
#define UAEMAJOR 4
#define UAEMINOR 9
-#define UAESUBREV 1
+#define UAESUBREV 2
#define MAX_AMIGADISPLAYS 4
if (bogomem_aliasing)
size = 8;
cb = &chipmem_bank;
-#ifdef AGA
-#if 0
+ #ifdef AGA
+ #if 0
if (currprefs.cpu_cycle_exact && currprefs.cpu_model >= 68020)
- cb = &chipmem_bank_ce2;
-#endif
-#endif
+ cb = &chipmem_bank_ce2;
+ #endif
+ #endif
if (chip) {
- map_banks (&dummy_bank, 0, size, 0);
- if (!isdirectjit ()) {
+ map_banks(&dummy_bank, 0, size, 0);
+ if (!isdirectjit()) {
if ((currprefs.chipset_mask & CSMASK_ECS_AGNUS) && bogomem_bank.allocated_size == 0) {
map_banks(cb, 0, size, chipmem_bank.allocated_size);
int start = chipmem_bank.allocated_size >> 16;
if (chipmem_bank.allocated_size < 0x100000) {
if (currprefs.cs_1mchipjumper) {
int dummy = (0x100000 - chipmem_bank.allocated_size) >> 16;
- map_banks (&chipmem_dummy_bank, start, dummy, 0);
- map_banks (&chipmem_dummy_bank, start + 16, dummy, 0);
+ map_banks(&chipmem_dummy_bank, start, dummy, 0);
+ map_banks(&chipmem_dummy_bank, start + 16, dummy, 0);
}
} else if (chipmem_bank.allocated_size < 0x200000 && chipmem_bank.allocated_size > 0x100000) {
int dummy = (0x200000 - chipmem_bank.allocated_size) >> 16;
- map_banks (&chipmem_dummy_bank, start, dummy, 0);
+ map_banks(&chipmem_dummy_bank, start, dummy, 0);
}
} else {
int mapsize = 32;
map_banks(cb, 0, mapsize, chipmem_bank.allocated_size);
}
} else {
- map_banks (cb, 0, chipmem_bank.allocated_size >> 16, 0);
+ map_banks(cb, 0, chipmem_bank.allocated_size >> 16, 0);
}
} else {
addrbank *rb = NULL;
if (size < 32 && bogomem_aliasing == 0)
size = 32;
cb = get_mem_bank_real(0xf00000);
- if (!rb && cb && (cb->flags & ABFLAG_ROM) && get_word (0xf00000) == 0x1114)
+ if (!rb && cb && (cb->flags & ABFLAG_ROM) && get_word(0xf00000) == 0x1114)
rb = cb;
cb = get_mem_bank_real(0xe00000);
- if (!rb && cb && (cb->flags & ABFLAG_ROM) && get_word (0xe00000) == 0x1114)
+ if (!rb && cb && (cb->flags & ABFLAG_ROM) && get_word(0xe00000) == 0x1114)
rb = cb;
if (!rb)
rb = &kickmem_bank;
- map_banks (rb, 0, size, 0x80000);
+ map_banks(rb, 0, size, 0x80000);
}
initramboard(&chipmem_bank, &currprefs.chipmem);
overlay_state = chip;
- fill_ce_banks ();
+ fill_ce_banks();
cpuboard_overlay_override();
- if (!isrestore () && valid_address (regs.pc, 4))
- m68k_setpc_normal (m68k_getpc ());
+ if (!isrestore() && valid_address(regs.pc, 4)) {
+ m68k_setpc_normal(m68k_getpc());
+ }
}
// Set a default pattern for uninitialized memory after hard reset.
{
if (!minimized)
minimized = 1;
- set_inhibit_frame(monid, IHF_WINDOWHIDDEN);
if (isfullscreen() > 0 && D3D_resize) {
write_log(_T("setminimized\n"));
D3D_resize(monid, -1);
else if (minimized > 0)
full_redraw_all();
minimized = 0;
- clear_inhibit_frame(monid, IHF_WINDOWHIDDEN);
}
void refreshtitle(void)
int cnt;
mon->render_ok = false;
- if (minimized || ad->picasso_on || monitor_off) {
+ if (ad->picasso_on || monitor_off) {
return mon->render_ok;
}
cnt = 0;
int yy = (mon->currentmode.native_height / mul - srcheight) / 2;
picasso_offset_x = -xx;
picasso_offset_y = -yy;
- mx = mul;
- my = mul;
+ mx = (float)mul;
+ my = (float)mul;
outwidth = srcwidth;
outheight = srcheight;
*mode = 1;