int strobe; /* COPJMP1 / COPJMP2 accessed */
int last_strobe;
int moveaddr, movedata, movedelay;
+ uaecptr moveptr;
};
static struct copper cop_state;
return cant;
}
-static int custom_wput_copper (int hpos, uaecptr addr, uae_u32 value, int noget)
+static int custom_wput_copper (int hpos, uaecptr pt, uaecptr addr, uae_u32 value, int noget)
{
int v;
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
};
-static void copper_write (uae_u32 v)
-{
- custom_wput_copper (current_hpos (), v >> 16, v & 0xffff, 0);
-}
-
/*
CPU write COPJMP wakeup sequence when copper is waiting:
- Idle cycle (can be used by other DMA channel)
if (cop_state.movedelay > 0) {
cop_state.movedelay--;
if (cop_state.movedelay == 0) {
- custom_wput_copper (c_hpos, cop_state.moveaddr, cop_state.movedata, 0);
+ custom_wput_copper (c_hpos, cop_state.moveptr, cop_state.moveaddr, cop_state.movedata, 0);
}
}
cop_state.moveaddr = reg;
cop_state.movedata = data;
cop_state.movedelay = customdelay[cop_state.moveaddr / 2];
+ cop_state.moveptr = cop_state.ip;
} else {
- custom_wput_copper (old_hpos, reg, data, 0);
+ custom_wput_copper (old_hpos, cop_state.ip, reg, data, 0);
}
#endif
}
}
peekdma_data.mask = 0;
#endif
+
switch(mode)
{
case -1:
sr = _T(" ");
if (dr->type == DMARECORD_COPPER) {
- sr = _T("COP ");
+ if (dr->extra == 3)
+ sr = _T("COPW");
+ else
+ sr = _T("COP ");
} else if (dr->type == DMARECORD_BLITTER) {
if (dr->extra == 2)
sr = _T("BLL ");
_stprintf (l2, _T("%4s %03X"), sr, r);
}
if (l3) {
- _stprintf (l3, longsize ? _T("%08X") : _T(" %04X"), dr->dat);
+ uae_u32 v = dr->dat;
+ if (!longsize)
+ v &= 0xffff;
+ _stprintf (l3, longsize ? _T("%08X") : _T(" %04X"), v);
}
if (l4 && dr->addr != 0xffffffff)
_stprintf (l4, _T("%08X"), dr->addr & 0x00ffffff);
if (a2410_vpos == 0) {
tms_vsync_handler2(data, true);
- picasso_getwritewatch(data->a2410_gfxboard, data->a2410_vram_start_offset);
+ picasso_getwritewatch(data->a2410_gfxboard, data->a2410_vram_start_offset, NULL, NULL);
}
if (data->a2410_modechanged || !ad->picasso_on)
}
for (int i = start; i < start + size; i++) {
addrbank *ab = &get_mem_bank(start << 16);
- if (ab != &dummy_bank) {
+ if (ab != &dummy_bank && bank != &dummy_bank) {
error_log(_T("Z2 map_banks(%s) attempting to override existing memory bank '%s' at %08x!\n"), bank->name, ab->name, i << 16);
return false;
}
#define LANG_DLL_FULL_VERSION_MATCH 1
#if WINUAEPUBLICBETA
-#define WINUAEBETA _T("Beta 12")
+#define WINUAEBETA _T("Beta 13")
#else
#define WINUAEBETA _T("")
#endif
-#define WINUAEDATE MAKEBD(2020, 12, 06)
+#define WINUAEDATE MAKEBD(2020, 12, 21)
//#define WINUAEEXTRA _T("AmiKit Preview")
//#define WINUAEEXTRA _T("Amiga Forever Edition")
+Beta 13:
+
+- PCI Voodoo 3 3000 emulation from PCem.
+- Fixed existing PCI bridge emulation memory mapped space address calculations (previous PCI boards were all IO only)
+- According to Alice schematics, AGA delays blitter finished signal until last D write is done (2 cycles later, only if not line mode and D is enabled). Previous chipsets clear blitter busy (and trigger interrupt) when last D write still pending.
+- Added GVP G-Force040. Basically same as G-Force030 (same ROM, same memory config), different internal GVP hardware ID.
+- Fixed GUI debugger hang if something was selected in debugger and then focus was changed.
+- MAST Fireball DMA address pointer handling fix, some address nybbles were decoded incorrectly. (I did say it has really strange DMA address pointer setup)
+- PCem RTG boards didn't always refresh screen fully when switching modes.
+- b12 blitter fixes, start up delay was 1 cycle too long, idle cycle before final D write does not need to be free cycle.
+- b12 blitter fixes, blitter fill mode setup missed some conditions.
+- Mainboard RAM settings disappeared in b11.
+- GD5446 (Picasso IV) blitter fix, "Invert Color Expand Source Sense" bit was not handled correctly in all blitter modes. (For example caused MUI 3.8 "REGISTER NOW" window corruption)
+
+Vooodoo 3 3000 details:
+- 16M VRAM (max supported) First hardware emulated board that supports full HD at 32-bit.
+- PCI board, PCI bridgeboard must be also configured.
+- BIOS ROM seems to be required (at least Mediator Voodoo Picasso96 driver reads some data from BIOS), currently must be in ROM path and named voodoo3.rom. Must be from PCI Voodoo 3 3000.
+- Native/RTG switching is implemented by checking status of SVGA screen blank bit. Might not always work correctly.
+- Hardware accelerated 3D confirmed working.
+- PCI to PCI DMA supported, compatible with Voodoo 3 + SB128 or FM801 sound card Mediator DMA hack.
+
+
Beta 12:
- 68000/010 cycle-exact/prefetch: If long write access, check IPL when first word of long has been written, not after last word. Fixes Made in Croatia / Binary (again).
- Not RDB compatible. Uses same partition table structure as A2090.
- ROM version string: "FireBall 0.4 (10 Mar 1990)"
-
Beta 11:
- S3Trio/S3Virge double scan mode detection fixed. Calculation used size parameters before bit depth specific screen width adjustments.
- $bfff00 debug logging word/long behavior changed. Format string without %l (except pointers: %p, %s and %b) is now consided word even if long was written to $bfff00.
- A2386SX 1.2M floppy error workaround. It expects to read 1.2M and 1.4M floppies using 720k floppy bit rate. 1.4M was already worked around previously. (Software thinks it is using shared Amiga 1760k drive, "Flipper" hardware is not emulated).
-
Beta 10:
- Added workaround for Windows socket behavior difference compared to Unix/Amiga. Windows return truncated data and error status if bsdsocket.library recv/recvfrom() supplied buffer is smaller than available data. Unix/Amiga sockets will also return truncated data but don't return error status.
load_rom_rc(aci->rc, ROMTYPE_SYNTHESIS, 32768, 0, scsi->rom, 65536, LOADROM_EVENONLY_ODDONE | LOADROM_FILL);
memcpy(scsi->acmemory, scsi->rom, sizeof scsi->acmemory);
aci->addrbank = scsi->bank;
+ return true;
}
void synthesis_add_scsi_unit(int ch, struct uaedev_config_info* ci, struct romconfig* rc)
if (fps > 999)
fps = 999;
num1 = fps / 100;
+ num1 %= 10;
num2 = 18;
num3 = (fps - num1 * 100) / 10;
} else {
num1 = fps / 100;
num2 = (fps - num1 * 100) / 10;
num3 = fps % 10;
+ num1 %= 10;
+ num2 %= 10;
if (num1 == 0)
am = 2;
}
num1 = idle / 100;
num2 = (idle - num1 * 100) / 10;
num3 = idle % 10;
+ num1 %= 10;
+ num2 %= 10;
num4 = num1 == 0 ? 13 : -1;
am = 3;
}