"External" (SVGA chip) PCI device BAR size fix if BAR set without alignment detection.

diff --git a/pci.cpp b/pci.cpp
index 3c3ab70ffc6e32056d9fa1cdab8d4b37cc5d9a43..6b99381c9e81e7d497e6a40130b7fc3bbe5e5d52 100644 (file)
--- a/pci.cpp
+++ b/pci.cpp
@@ -542,6 +542,26 @@ static void update_pci_config(uaecptr addr, int size)
                        }
                } else {
                        pcibs->bar[i] = 0;
+                       // pre-set bar size when indirect PCI config
+                       if (pcibs->board->pci_put_config) {
+                               uae_u32 tbar = pcibs->board->pci_get_config(off + 3) << 24;
+                               tbar |= pcibs->board->pci_get_config(off + 2) << 16;
+                               tbar |= pcibs->board->pci_get_config(off + 1) << 8;
+                               tbar |= pcibs->board->pci_get_config(off + 0) << 0;
+                               pcibs->board->pci_put_config(off + 3, 0xff);
+                               pcibs->board->pci_put_config(off + 2, 0xff);
+                               pcibs->board->pci_put_config(off + 1, 0xff);
+                               pcibs->board->pci_put_config(off + 0, 0xff);
+                               uae_u32 bar = pcibs->board->pci_get_config(off + 3) << 24;
+                               bar |= pcibs->board->pci_get_config(off + 2) << 16;
+                               bar |= pcibs->board->pci_get_config(off + 1) << 8;
+                               bar |= pcibs->board->pci_get_config(off + 0) << 0;
+                               pcibs->bar_size[i] = ~((bar & ~1) - 1);
+                               pcibs->board->pci_put_config(off + 3, tbar >> 24);
+                               pcibs->board->pci_put_config(off + 2, tbar >> 16);
+                               pcibs->board->pci_put_config(off + 1, tbar >> 8);
+                               pcibs->board->pci_put_config(off + 0, tbar >> 0);
+                       }
                }
        }
        if (pcibs->board->pci_put_config) {