FAS246 apparently has extended mode always enabled.

diff --git a/ncr9x_scsi.cpp b/ncr9x_scsi.cpp
index 305dc629b01108dfe56056ec1d225104bd2c4b3e..a16cc3bc6588b2bf2bdaae241272ed99dc62a968 100644 (file)
--- a/ncr9x_scsi.cpp
+++ b/ncr9x_scsi.cpp
@@ -2455,7 +2455,7 @@ static void ncr9x_esp_scsi_init(struct ncr9x_state *ncr, ESPDMAMemoryReadWriteFu
        ncr->board_mask = 0xffff;
        ncr->irq_func = irq_func ? irq_func : set_irq2;
        if (!ncr->devobject.lsistate)
-               esp_scsi_init(&ncr->devobject, read, write, mode > 0);
+               esp_scsi_init(&ncr->devobject, read, write, mode > 0 ? mode : 0);
        esp_scsi_reset(&ncr->devobject, ncr);
 }
 
@@ -2539,7 +2539,7 @@ void cpuboard_ncr9x_add_scsi_unit(int ch, struct uaedev_config_info *ci, struct
 void cpuboard_dkb_add_scsi_unit(int ch, struct uaedev_config_info *ci, struct romconfig *rc)
 {
        ncr9x_add_scsi_unit(&ncr_dkb1200_scsi, ch, ci, rc);
-       ncr9x_esp_scsi_init(ncr_dkb1200_scsi, fake_dma_read, fake_dma_write, set_irq2_dkb1200, 0);
+       ncr9x_esp_scsi_init(ncr_dkb1200_scsi, fake_dma_read, fake_dma_write, set_irq2_dkb1200, 2);
 }
 
 void fastlane_add_scsi_unit (int ch, struct uaedev_config_info *ci, struct romconfig *rc)
@@ -2604,7 +2604,7 @@ void scram5394_add_scsi_unit(int ch, struct uaedev_config_info *ci, struct romco
 void rapidfire_add_scsi_unit(int ch, struct uaedev_config_info *ci, struct romconfig *rc)
 {
        ncr9x_add_scsi_unit(&ncr_rapidfire_scsi[ci->controller_type_unit], ch, ci, rc);
-       ncr9x_esp_scsi_init(ncr_rapidfire_scsi[ci->controller_type_unit], fake_dma_read, fake_dma_write, set_irq2, 0);
+       ncr9x_esp_scsi_init(ncr_rapidfire_scsi[ci->controller_type_unit], fake_dma_read, fake_dma_write, set_irq2, 2);
        esp_dma_enable(ncr_rapidfire_scsi[ci->controller_type_unit]->devobject.lsistate, 1);
 }
 

diff --git a/qemuvga/esp.cpp b/qemuvga/esp.cpp
index e73bc91d39315c50960ac012a6994e4c16339ee7..8a1e8f18c4269ecb5138cc03f1d556d2cade553c 100644 (file)
--- a/qemuvga/esp.cpp
+++ b/qemuvga/esp.cpp
@@ -113,7 +113,7 @@ static void fas408_lower_irq(ESPState *s)
 
 static void fas408_check(ESPState *s)
 {
-       if (!s->fas4xxextra)
+       if (!(s->fas4xxextra & 1))
                return;
        bool irq = false;
        int v = 0;
@@ -350,7 +350,7 @@ static void esp_dma_done(ESPState *s)
        s->dma_counter -= s->dma_len;
     s->rregs[ESP_TCLO] = s->dma_counter;
     s->rregs[ESP_TCMID] = s->dma_counter >> 8;
-       if (s->wregs[ESP_CFG2] & 0x40)
+       if ((s->wregs[ESP_CFG2] & 0x40) || (s->fas4xxextra & 2))
                s->rregs[ESP_TCHI] = s->dma_counter >> 16;
     
        esp_raise_irq(s);
@@ -578,7 +578,9 @@ void esp_hard_reset(ESPState *s)
 {
     memset(s->rregs, 0, ESP_REGS);
     memset(s->wregs, 0, ESP_REGS);
-    s->rregs[ESP_TCHI] = s->chip_id;
+    if (!(s->fas4xxextra & 2)) {
+        s->rregs[ESP_TCHI] = s->chip_id;
+    }
     s->ti_size = 0;
     s->ti_rptr = 0;
     s->ti_wptr = 0;
@@ -606,7 +608,7 @@ uint64_t fas408_read_fifo(void *opaque)
 {
        ESPState *s = (ESPState*)opaque;
        s->rregs[ESP_FIFO] = 0;
-       if (s->fas4xxextra && (s->wregs[ESP_REGS + NCR_PSTAT] & NCRPSTAT_PIOM) && (s->fas408_buffer_size > 0 || s->fas408_buffer_offset > 0 || (s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == STAT_DO)) {
+       if ((s->fas4xxextra & 1) && (s->wregs[ESP_REGS + NCR_PSTAT] & NCRPSTAT_PIOM) && (s->fas408_buffer_size > 0 || s->fas408_buffer_offset > 0 || (s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == STAT_DO)) {
                bool refill = true;
                if (s->ti_size > 128) {
                        s->rregs[ESP_FIFO] = s->async_buf[s->ti_rptr++];
@@ -643,7 +645,7 @@ static uint64_t esp_reg_read2(void *opaque, uint32_t saddr)
        ESPState *s = (ESPState*)opaque;
        uint32_t old_val;
 
-       if (s->fas4xxextra && (s->wregs[0x0d] & 0x80)) {
+       if ((s->fas4xxextra & 1) && (s->wregs[0x0d] & 0x80)) {
                saddr += ESP_REGS;
        }
 
@@ -718,7 +720,7 @@ static uint64_t esp_reg_read2(void *opaque, uint32_t saddr)
        case ESP_RES4:
                return 0x80 | 0x20 | 0x2;
        case ESP_TCHI:
-               if (!(s->wregs[ESP_CFG2] & 0x40))
+               if (!(s->wregs[ESP_CFG2] & 0x40) && !(s->fas4xxextra & 2))
                        return 0;
                break;
 
@@ -753,7 +755,7 @@ uint64_t esp_reg_read(void *opaque, uint32_t saddr)
 void fas408_write_fifo(void *opaque, uint64_t val)
 {
        ESPState *s = (ESPState*)opaque;
-       if (!s->fas4xxextra)
+       if (!(s->fas4xxextra & 1))
                return;
        s->fas408_buffer_offset = 0;
        if (s->fas408_buffer_size < 128) {
@@ -778,7 +780,7 @@ void esp_reg_write(void *opaque, uint32_t saddr, uint64_t val)
 {
        ESPState *s = (ESPState*)opaque;
 
-       if (s->fas4xxextra && (s->wregs[ESP_RES3] & 0x80)) {
+       if ((s->fas4xxextra & 1) && (s->wregs[ESP_RES3] & 0x80)) {
                saddr += ESP_REGS;
        }
 
@@ -792,7 +794,7 @@ void esp_reg_write(void *opaque, uint32_t saddr, uint64_t val)
                s->rregs[ESP_RSTAT] &= ~STAT_TC;
                break;
        case ESP_TCHI:
-               if (!(s->wregs[ESP_CFG2] & 0x40))
+               if (!(s->wregs[ESP_CFG2] & 0x40) && !(s->fas4xxextra & 2))
                        val = 0;
                else
                        s->rregs[ESP_RSTAT] &= ~STAT_TC;
@@ -820,14 +822,14 @@ void esp_reg_write(void *opaque, uint32_t saddr, uint64_t val)
             s->rregs[ESP_TCLO] = s->wregs[ESP_TCLO];
             s->rregs[ESP_TCMID] = s->wregs[ESP_TCMID];
             s->rregs[ESP_TCHI] = s->wregs[ESP_TCHI];
-                       if (!(s->wregs[ESP_CFG2] & 0x40))
+                       if (!(s->wregs[ESP_CFG2] & 0x40) && !(s->fas4xxextra & 2))
                                s->rregs[ESP_TCHI] = 0;
         } else {
             s->dma = 0;
         }
         switch(val & CMD_CMD) {
         case CMD_NOP:
-                       if ((val & CMD_DMA) && (s->wregs[ESP_CFG2] & 0x40))
+                       if ((val & CMD_DMA) && ((s->wregs[ESP_CFG2] & 0x40) && !(s->fas4xxextra & 2)))
                                s->rregs[ESP_TCHI] = s->chip_id;
                        break;
         case CMD_FLUSH:
@@ -1149,14 +1151,14 @@ static void esp_register_types(void)
 type_init(esp_register_types)
 #endif
 
-void esp_scsi_init(DeviceState *dev, ESPDMAMemoryReadWriteFunc read, ESPDMAMemoryReadWriteFunc write, bool fas4xxextra)
+void esp_scsi_init(DeviceState *dev, ESPDMAMemoryReadWriteFunc read, ESPDMAMemoryReadWriteFunc write, int fas4xxextra)
 {
        dev->lsistate = calloc(sizeof(ESPState), 1);
        ESPState *s = ESP(dev);
        s->dma_memory_read = read;
        s->dma_memory_write = write;
        s->fas4xxextra = fas4xxextra;
-       s->chip_id = 0x12;
+       s->chip_id = 0x12 | 0x80;
 }
 
 void esp_scsi_reset(DeviceState *dev, void *privdata)

diff --git a/qemuvga/scsi/esp.h b/qemuvga/scsi/esp.h
index a8cf90b90ffc3acf68729709ff2dae4a7b2b8831..fa090e3df5ac89454863802ec93f7f620c033542 100644 (file)
--- a/qemuvga/scsi/esp.h
+++ b/qemuvga/scsi/esp.h
@@ -21,6 +21,7 @@ struct ESPState {
     qemu_irq irq;
        int irq_raised;
     uint8_t chip_id;
+    uint8_t tchi_has_id;
     int32_t ti_size;
        int32_t dma_len;
     uint32_t ti_rptr, ti_wptr;
@@ -52,7 +53,7 @@ struct ESPState {
     ESPDMAMemoryReadWriteFunc dma_memory_write;
     void *dma_opaque;
     int (*dma_cb)(ESPState *s);
-       bool fas4xxextra;
+       int fas4xxextra;
        int fas408sig;
        uint8_t fas408_buffer[128+1];
        int fas408_buffer_size;
@@ -210,7 +211,7 @@ void esp_fake_dma_put(void *opaque, uint8_t v);
 void esp_request_cancelled(SCSIRequest *req);
 void esp_command_complete(SCSIRequest *req, uint32_t status, size_t resid);
 void esp_transfer_data(SCSIRequest *req, uint32_t len);
-void esp_scsi_init(DeviceState *dev, ESPDMAMemoryReadWriteFunc read, ESPDMAMemoryReadWriteFunc write, bool fas4xxextra);
+void esp_scsi_init(DeviceState *dev, ESPDMAMemoryReadWriteFunc read, ESPDMAMemoryReadWriteFunc write, int fas4xxextra);
 void esp_scsi_reset(DeviceState *dev, void *privdata);
 bool esp_dreq(DeviceState *dev);